JPH0621180A - Inspecting method for misregistration of solder-resist layer of printed wiring board - Google Patents
Inspecting method for misregistration of solder-resist layer of printed wiring boardInfo
- Publication number
- JPH0621180A JPH0621180A JP4176921A JP17692192A JPH0621180A JP H0621180 A JPH0621180 A JP H0621180A JP 4176921 A JP4176921 A JP 4176921A JP 17692192 A JP17692192 A JP 17692192A JP H0621180 A JPH0621180 A JP H0621180A
- Authority
- JP
- Japan
- Prior art keywords
- resist layer
- conductive
- solder resist
- marks
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はプリント配線板のソルダ
ーレジスト層の位置ずれ検査方法に係り、特にソルダー
レジスト層の位置ずれを電気的に、かつ高精度に検出す
る方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting a position shift of a solder resist layer of a printed wiring board, and more particularly to a method for electrically detecting a position shift of a solder resist layer with high accuracy.
【０００２】[0002]
【従来の技術】周知のように、プリント配線板の製造工
程においては、所要の接続部（被半田付け部）を除いて
表面に配設・形成されている配線パターン領域を、絶縁
保護などのためソルダーレジスト層で選択的に被覆して
いる。すなわち、所要の配線パターンを形成した後の最
終的な段階で、電子部品のリード（端子）を電気的に接
続する箇所など、将来半田付けを行う接続部を選択的に
露出させ、他の配線パターン領域をソルダーレジストで
選択的に被覆して、選択的な半田付けの可能化と電気的
および外界雰囲気に対する絶縁・保護機能を付与してい
る。そして、前記ソルダーレジストの選択的な被覆は、
換言すると、半田付け・接続部などを高精度に（位置ず
れなく）選択・露出させながら、他の配線パターン領域
をソルダーレジストで確実に被覆することは、プリント
配線板の品質保証などの点で重要な事項といえる。2. Description of the Related Art As is well known, in the manufacturing process of a printed wiring board, a wiring pattern area provided and formed on the surface except for a required connection portion (soldered portion) is subjected to insulation protection or the like. Therefore, it is selectively covered with a solder resist layer. In other words, at the final stage after the required wiring pattern is formed, the connection part to be soldered in the future, such as the place to electrically connect the lead (terminal) of the electronic component, is selectively exposed and other wiring is The pattern area is selectively covered with a solder resist to provide selective soldering and insulation / protection functions against electrical and external atmospheres. And the selective coating of the solder resist is
In other words, it is necessary to surely cover other wiring pattern areas with solder resist while selecting / exposing soldering / connecting parts with high accuracy (without positional deviation) in terms of quality assurance of printed wiring boards. It can be said to be an important matter.
【０００３】このような観点から、前記ソルダーレジス
ト層の選択的な被着・被覆後においては、ソルダーレジ
スト層が位置ずれなく、換言すると、所要領域のみを選
択的に露出させ、他の領域面がソルダーレジスト層で確
実に被覆されているか否かを検出している。つまり、図
４(a) ，(b) に模式的に示すごとく、選択的に露出させ
ておくべき導体パターン（接続部）１に対して、被覆さ
れたソルダーレジスト層２の位置関係を、目視観察ある
いは拡大鏡観察によって検出して、たとえば図４(a) に
平面的に示すように、露出導体パターン１を囲繞するソ
ルダーレジスト層２の端縁位置が一定の場合を位置ずれ
なしと、そして図４(b) に平面的に示すごとく、露出導
体パターン１を囲繞するソルダーレジスト層２の端縁位
置が一定でない場合を位置ずれありと評価・判定してい
る。From such a point of view, after the selective deposition / covering of the solder resist layer, the solder resist layer is not displaced, in other words, only the required region is selectively exposed and the other region surface is exposed. It is detected whether or not is surely covered with the solder resist layer. That is, as schematically shown in FIGS. 4 (a) and 4 (b), the positional relationship of the covered solder resist layer 2 with respect to the conductor pattern (connection portion) 1 to be selectively exposed is visually checked. If the edge position of the solder resist layer 2 surrounding the exposed conductor pattern 1 is constant as detected by observation or magnifying glass observation, as shown in a plan view in FIG. As shown in plan view in FIG. 4B, when the edge position of the solder resist layer 2 surrounding the exposed conductor pattern 1 is not constant, it is evaluated and determined that there is misalignment.
【０００４】[0004]
【発明が解決しようとする課題】しかし、前記プリント
配線板のソルダーレジスト層の位置ずれ検出手段（方
法）の場合は、実際的に次のような不都合な問題があ
る。すなわち、プリント配線板を製造する一連の製造工
程の中において、全数を目視観察あるいは拡大鏡観察し
てソルダーレジスト層の位置ずれ量（通常 0〜 100μm
程度）を検出することは、事実上至難のことであり、ま
たこの結果を検査規格と照合して、製品の合格・不合格
を判断するのにかなりの時間を要するという問題があ
る。特に、プリント配線板においては、近時配線の微細
化や配線の狭ピッチ化（配線の高密度化）が進められて
おり、このような現状からすると、前記目視観察あるい
は拡大鏡観察によって、ソルダーレジスト層の位置ずれ
を検出しての品質保証することや、またその検出手段の
不経済性（非量産的）および検出の信頼性などの点で、
由々しい問題を呈することになる。However, in the case of the means (method) for detecting the positional deviation of the solder resist layer of the printed wiring board, there are actually the following inconvenient problems. That is, in a series of manufacturing steps for manufacturing a printed wiring board, the total amount of misalignment of solder resist layers (usually 0 to 100 μm
It is practically difficult to detect the degree), and there is a problem that it takes a considerable amount of time to judge the pass / fail of the product by checking the result against the inspection standard. In particular, in printed wiring boards, finer wiring and narrower wiring pitch (higher wiring density) are being promoted in recent years. From such a situation, the solder can be observed by the visual observation or the magnifying glass observation. In terms of quality assurance by detecting the positional deviation of the resist layer, uneconomical (non-mass production) of the detecting means, and detection reliability,
It presents a serious problem.
【０００５】本発明は上記事情に対処してなされたもの
で、煩雑な操作を要せずに、かつ量産的でありながら、
被着・形成したソルダーレジスト層の位置ずれを高精度
に検出し、合否の評価が可能なプリント配線板のソルダ
ーレジスト層の位置ずれ検出方法の提供を目的とする。The present invention has been made in view of the above circumstances and requires no complicated operation and is mass-produced.
An object of the present invention is to provide a method for detecting a positional deviation of a solder resist layer of a printed wiring board, which is capable of highly accurately detecting a positional deviation of a deposited / formed solder resist layer and evaluating pass / fail.
【０００６】[0006]
【課題を解決するための手段】本発明に係るプリント配
線板のソルダーレジスト層の位置ずれ検出方法は、プリ
ント配線板の配線パターン形成面に、予め互いに平行
的、かつ一定間隔で位置ずれさせて基準導電マークを含
む複数対の導電マークを設けておき、この導電マークを
含め配線パターン形成面をソルダーレジスト層で選択的
に被覆した後、前記導電マーク形成領域に対応した一定
間隔幅の導電端子を当接して電気的に導通する導電マー
ク対によって、前記被覆したソルダーレジスト層の位置
ずれを検出することを特徴とする。A method for detecting a positional deviation of a solder resist layer of a printed wiring board according to the present invention is arranged such that the wiring pattern forming surface of the printed wiring board is preliminarily displaced in parallel and at regular intervals. A plurality of pairs of conductive marks including a reference conductive mark are provided, and a wiring pattern forming surface including these conductive marks is selectively covered with a solder resist layer, and then conductive terminals having a constant interval width corresponding to the conductive mark forming region. The position shift of the coated solder resist layer is detected by a pair of conductive marks that are in contact with each other and are electrically connected.
【０００７】[0007]
【作用】上記本発明に係るソルダーレジスト層の位置ず
れ検出方法によれば、ソルダーレジスト層を被着・形成
する配線パターン形成面に、予め設けてある互いに平行
的に、かつ一定間隔で位置ずれさせて基準導電マークを
含む複数対の導電マーク領域にも、ソルダーレジスト層
が選択的に被着・形成される。そして、この領域におい
ても、配線パターン形成面におけるソルダーレジスト層
の位置ずれに対応して露出する領域（部分）が変化す
る。したがって、配線パターン形成面におけるソルダー
レジスト層に位置ずれがない場合は、対をなす基準導電
マーク以外の他のいずれかの導電マークが露出して、こ
の導電マークによる導電が検出されることになる。一
方、配線パターン形成面におけるソルダーレジスト層に
位置ずれがある場合は、前記基準導電マークが露出し
て、この露出した基準導電マークによる導電が検出さ
れ、位置ずれの方向や程度（位置ずれ量）が分かる。つ
まり、互いに平行的に位置ずれ・配置された基準導電マ
ークを含む複数対の導電マークのうち、いずれの対の導
電マークが導電に寄与（関与）しているか電気的に検知
して、位置ずれの有無や位置ずれ量などを容易・確実
に、かつ精度よく検出し得るので、プリント配線板の信
頼性ないし品質検証の向上も図り得る。According to the method for detecting the positional deviation of the solder resist layer according to the present invention, the positional deviation is provided at predetermined intervals in parallel with each other on the wiring pattern forming surface on which the solder resist layer is deposited / formed. Thus, the solder resist layer is selectively deposited / formed also on the plurality of pairs of conductive mark regions including the reference conductive mark. Also in this area, the exposed area (portion) changes corresponding to the positional deviation of the solder resist layer on the wiring pattern forming surface. Therefore, when there is no displacement in the solder resist layer on the wiring pattern formation surface, any conductive mark other than the pair of reference conductive marks is exposed, and the conductivity due to this conductive mark is detected. . On the other hand, when the solder resist layer on the wiring pattern formation surface has a positional deviation, the reference conductive mark is exposed, and the conductivity due to the exposed reference conductive mark is detected, and the direction and degree of the positional deviation (positional deviation amount). I understand. In other words, among a plurality of pairs of conductive marks that include reference conductive marks that are displaced / arranged in parallel to each other, electrically detecting which pair of conductive marks contributes to (contributes to) the conductivity, and shifts the position. Since it is possible to detect the presence or absence and the amount of positional deviation easily, accurately, and accurately, it is possible to improve the reliability or quality verification of the printed wiring board.
【０００８】[0008]
【実施例】以下図１〜図３を参照して本発明の実施例を
説明する。Embodiments of the present invention will be described below with reference to FIGS.
【０００９】先ず、所定の配線パターンおよびその配線
パターン近傍に、互いに平行して、かつ一定間隔（たと
えば20μm 程度）で位置ずれさせて基準導電マークを含
む複数対の導電マークを設けたプリント配線板を用意し
た。次いで、常套の手段に従って、前記配線パターンお
よび導電マークを形成した面に、シルクスクリーン法に
よりソルダーレジスト層を被着・形成した。図１はこの
ようにして、ソルダーレジスト層を被着・形成したプリ
ント配線板３の要部構成を平面的に示したもので、4aは
一定間隔（たとえば 1mm程度）で対向配置された対を成
す基準導電マーク、4b，4b′はそれぞれ一定間隔で対向
配置され、かつ一定間隔（たとえば20μm 程度）で位置
ずれさせた対を成す他の導電マーク（非基準導電マー
ク）、５はソルダーレジスト層、6a，6b，6b′は前記基
準導電マーク4aおよび他の導電マーク4b，4b′にそれぞ
れ電気的に接続する導体ランド（電気検査ブロープ用）
であり、これらの導体ランド6a，6b，6b′面は露出して
いる。そして、この図１の場合は、互いに平行的、かつ
一定間隔で位置ずれ配置された複数対の導電マークのう
ち、基準導電マーク4aはソルダーレジスト層５で全面的
に被覆されており、他の導電マーク4b，4b′のいずれか
一方がそれぞれ露出している。つまり、配線パターン形
成面においては、位置ずれを起こさずソルダーレジスト
層５が被着・形成されており、露出させておくべき導体
パターン（接続部）は、選択的な半田付けが可能に露出
し、その他の導体パターン領域面はソルダーレジスト層
５によって、確実に被覆され所要の保護機能を備えてい
る。First, a printed wiring board having a predetermined wiring pattern and a plurality of pairs of conductive marks including a reference conductive mark which are parallel to each other and are displaced at regular intervals (for example, about 20 μm) in the vicinity of the predetermined wiring pattern. Prepared. Then, a solder resist layer was deposited and formed on the surface on which the wiring pattern and the conductive mark were formed by a silk screen method according to a conventional method. FIG. 1 is a plan view showing the main structure of the printed wiring board 3 on which the solder resist layer is deposited and formed in this manner. 4a is a pair of opposingly arranged at regular intervals (for example, about 1 mm). The reference conductive marks 4b and 4b 'that are formed are opposed to each other at regular intervals, and a pair of other conductive marks (non-reference conductive marks) that are displaced at regular intervals (for example, about 20 μm) and 5 are solder resist layers. , 6a, 6b, 6b 'are conductor lands electrically connected to the reference conductive mark 4a and the other conductive marks 4b, 4b' (for electrical inspection probe).
The surfaces of these conductor lands 6a, 6b, 6b 'are exposed. In the case of FIG. 1, the reference conductive mark 4a is covered entirely with the solder resist layer 5 among a plurality of pairs of conductive marks which are displaced in parallel and displaced at a constant interval. Either one of the conductive marks 4b and 4b 'is exposed. In other words, on the wiring pattern forming surface, the solder resist layer 5 is deposited and formed without causing positional displacement, and the conductor pattern (connection portion) to be exposed is exposed so that selective soldering can be performed. , The other conductor pattern area surface is surely covered with the solder resist layer 5 and has a required protection function.
【００１０】したがって、この形態ないし状態におい
て、前記導電マーク4a，4b，4b′の領域に、たとえば導
電性ゴムや導電性樹脂の成型体、導電性金属ブロックな
どの導電体７を配置する一方、前記導電マーク4a，4b，
4b′に対応する導体ランド6a，6b，6b′面に検査ブロー
ブを当接し、この導電体を介して所要の電圧を印加して
導電状態を検出すると、導電マーク4b，4b′間の導電が
得られ、基準導電マーク4aと導電マーク4bもしくは4b′
間の導電は得られないので、ソルダーレジスト層５に位
置ずれが生じていないことが分かる。つまり、前記導電
検査でいずれの導電マーク間で導電を生じたかを確認
し、その結果を予め設定しておいた検査規格と対比する
ことによって、ソルダーレジスト層５を被覆したプリン
ト配線板の合格，不合格を瞬時に判定・評価し得る。Therefore, in this form or state, a conductor 7 such as a molded body of conductive rubber or conductive resin or a conductive metal block is arranged in the area of the conductive marks 4a, 4b, 4b ', while The conductive marks 4a, 4b,
When the inspection probe is brought into contact with the surfaces of the conductor lands 6a, 6b, 6b 'corresponding to 4b', and a required voltage is applied via this conductor to detect the conductive state, the conductive between the conductive marks 4b, 4b 'is detected. Obtained, the reference conductive mark 4a and the conductive mark 4b or 4b '
Since no electrical conductivity is obtained between them, it can be seen that the solder resist layer 5 is not displaced. That is, it is confirmed by the conductive test which conductive mark has been generated between the conductive marks, and the result is compared with a preset inspection standard to determine whether the printed wiring board coated with the solder resist layer 5 passes. The failure can be judged and evaluated instantly.
【００１１】一方、前記ソルダーレジスト層５の被着・
形成において、ソルダーレジスト層５の位置ずれがある
と、図２に要部構成を平面的、また図３に要部構成を断
面的にそれぞれ示すごとくなる。すなわち、図２および
図３に図示された場合は、互いに平行的に、かつ一定間
隔で位置ずれ配置された複数対の導電マークのうち、基
準導電マーク4aおよび他の導電マーク4b，4b′のいずれ
も一方は、ソルダーレジスト層５で全面的に被覆されて
おり、基準導電マーク4aおよび他の導電マーク4b，4b′
のいずれも他方は一部ないし全体が露出している。つま
り、配線パターン形成面においては、位置ずれを起こし
てソルダーレジスト層５が被着・形成されており、露出
させておくべき導体パターン（接続部）も選択的な半田
付けが可能な状態に露出しておらず、一部が被覆された
状態を成しているため、ソルダーレジスト層５は本来の
保護機能を呈していない。On the other hand, deposition of the solder resist layer 5
When the solder resist layer 5 is misaligned during the formation, the configuration of the main part is shown in plan view in FIG. 2 and the configuration of the main part in cross section in FIG. That is, in the case shown in FIG. 2 and FIG. 3, the reference conductive mark 4a and the other conductive marks 4b and 4b 'are included among a plurality of pairs of conductive marks that are displaced in parallel and at regular intervals. One of them is entirely covered with the solder resist layer 5, and the reference conductive mark 4a and the other conductive marks 4b, 4b '.
In either case, the other part is partially or entirely exposed. In other words, on the wiring pattern forming surface, the solder resist layer 5 is deposited and formed due to the positional deviation, and the conductor pattern (connecting portion) to be exposed is also exposed in a state in which selective soldering is possible. However, the solder resist layer 5 does not exhibit the original protection function because it is partially covered.
【００１２】したがって、この形態ないし状態におい
て、前記導電マーク4a，4b，4b′の領域に、たとえば導
電性ゴムや導電性樹脂の成型体、導電性金属ブロックな
どの導電体７を配置する一方、前記導電マーク4a，4b，
4b′に対応する導体ランド6a，6b，6b′面に検査ブロー
ブを当接し、この導電体を介して所要の電圧を印加して
導電状態を検出すると、導電マーク4b，4b′間の導電が
得られ、かつ基準導電マーク4aと導電マーク4bもしくは
4b′間の導電が得られるので、ソルダーレジスト層５に
位置ずれが生じていることが分かる。この例示の場合に
おいては、導電マーク4a，4b，4b′の右側導体ランド6
a，6b，6b′に導電が全て得られるので、ソルダーレジ
スト層が正常な位置よりも20μm 以上ズレていること
が、容易に検出される。Therefore, in this form or state, a conductor 7 such as a molded body of conductive rubber or conductive resin or a conductive metal block is arranged in the area of the conductive marks 4a, 4b, 4b ', while The conductive marks 4a, 4b,
When the inspection probe is brought into contact with the surfaces of the conductor lands 6a, 6b, 6b 'corresponding to 4b', and a required voltage is applied via this conductor to detect the conductive state, the conductive between the conductive marks 4b, 4b 'is detected. Obtained and reference conductive mark 4a and conductive mark 4b or
It can be seen that since the conduction between 4b 'is obtained, the solder resist layer 5 is displaced. In the case of this example, the right conductor land 6 of the conductive marks 4a, 4b, 4b '
Since all conductivity is obtained in a, 6b, and 6b ', it is easy to detect that the solder resist layer is displaced by 20 μm or more from the normal position.
【００１３】なお、上記においては、導電マーク4a，4
b，4b′３対を配置した構成の例を示したが、この導電
マークの対をさらに増加・設定してもよし、対を成す導
電マークの対向する間隔などの設定も任意であり、前記
導電マーク対の増加・設定によりソルダーレジスト層の
位置ずれを、さらに高精度に検出（検査）することが可
能である。In the above, the conductive marks 4a, 4a
Although an example of a configuration in which 3 pairs of b and 4b 'are arranged is shown, the number of pairs of the conductive marks may be further increased / set, and the interval between the conductive marks forming the pair may be arbitrarily set. By increasing / setting the number of conductive mark pairs, it is possible to detect (inspect) the positional deviation of the solder resist layer with higher accuracy.
【００１４】[0014]
【発明の効果】上記説明したように、本発明に係るソル
ダーレジスト層の位置ずれ検出方法によれば、配線パタ
ーン形成面におけるソルダーレジスト層の位置ずれに対
応して変化する導電マーク群領域の露出状態を巧みに利
用して、位置ずれの方向や位置ずれ量を容易・迅速に、
かつ正確に検出することができる。つまり、配線パター
ン形成面におけるソルダーレジスト層に位置ずれがない
場合、あるいは位置ずれがある場合により、基準導電マ
ークの露出が生じたり生じなかったりするので、これら
導電マーク間（特に基準導電マークを中心にして）の導
電の検出によって、ソルダーレジスト層の位置ずれ方向
や程度を容易に検出し得る。そして、このソルダーレジ
スト層の位置ずれ検査（検出）は、いわゆるプリント配
線板の製造ラインにおいても容易に行い得るので、前記
精度の高さに伴うプリント配線板（製品）の信頼性向
上、量産的なことなどと相俟って実用上多くの利点をも
たらすものといえる。As described above, according to the method of detecting the positional deviation of the solder resist layer according to the present invention, the exposure of the conductive mark group area which changes corresponding to the positional deviation of the solder resist layer on the wiring pattern forming surface. By skillfully utilizing the state, it is possible to easily and quickly determine the direction of displacement and the amount of displacement.
And it can be detected accurately. In other words, if the solder resist layer on the wiring pattern formation surface is not displaced, or if there is displacement, the reference conductive marks may or may not be exposed. It is possible to easily detect the direction and degree of displacement of the solder resist layer by detecting the conductivity of (1). Further, since the positional deviation inspection (detection) of the solder resist layer can be easily performed even in a so-called printed wiring board manufacturing line, the reliability of the printed wiring board (product) is improved due to the high accuracy, and the mass production In combination with such things, it can be said that it brings many practical advantages.
【図１】本発明に係るソルダーレジスト層の位置ずれ検
出方法の実施態様例の要部を示す平面図。FIG. 1 is a plan view showing a main part of an embodiment of a method for detecting a positional deviation of a solder resist layer according to the present invention.
【図２】本発明に係るソルダーレジスト層の位置ずれ検
出方法の他の実施態様例の要部を示す平面図。FIG. 2 is a plan view showing a main part of another embodiment example of the method for detecting the positional deviation of the solder resist layer according to the present invention.
【図３】図２に図示した実施態様例の要部を示す断面
図。FIG. 3 is a sectional view showing a main part of the embodiment example shown in FIG.
【図４】プリント配線板のソルダーレジスト層の位置ず
れを模式的に示したもので、(a) は位置ずれの起きてい
ない状態を示す平面図、(b) は位置ずれの起きている状
態を示す平面図。4A and 4B are schematic views showing the positional deviation of the solder resist layer of the printed wiring board, where FIG. 4A is a plan view showing a state where the positional deviation has not occurred, and FIG. 4B shows a state where the positional deviation has occurred. FIG.
１…露出させておく導体パターン（接続部） ２，５
…ソルダーレジスト層 ３…プリント配線板 4a…基準導電マーク 4b，4
b′…非基準導電マーク 6a，6b，6b′…導体ランド
７…導電端子（導電体）1 ... Conductor pattern to be exposed (connection part) 2, 5
... Solder resist layer 3 ... Printed wiring board 4a ... Reference conductive marks 4b, 4
b '... Non-reference conductive mark 6a, 6b, 6b' ... Conductor land 7 ... Conductive terminal (conductor)
Claims (1)
に、予め互いに平行的、かつ一定間隔で位置ずれさせて
基準導電マークを含む複数対の導電マークを設けてお
き、この導電マークを含め配線パターン形成面をソルダ
ーレジスト層で選択的に被覆した後、前記導電マーク形
成領域に対応した一定間隔幅の導電端子を当接して電気
的に導通する導電マーク対によって、前記被覆したソル
ダーレジスト層の位置ずれを検出することを特徴とする
プリント配線板のソルダーレジスト層の位置ずれ検査方
法。1. A plurality of pairs of conductive marks including a reference conductive mark are provided in advance on a wiring pattern forming surface of a printed wiring board in parallel with each other and displaced at regular intervals, and the wiring pattern including the conductive marks is provided. After selectively covering the formation surface with a solder resist layer, a position of the covered solder resist layer is provided by a conductive mark pair electrically contacted by contacting conductive terminals having a constant interval width corresponding to the conductive mark formation region. A method for inspecting a position shift of a solder resist layer of a printed wiring board, which is characterized by detecting a shift.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4176921A JPH0621180A (en) | 1992-07-03 | 1992-07-03 | Inspecting method for misregistration of solder-resist layer of printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4176921A JPH0621180A (en) | 1992-07-03 | 1992-07-03 | Inspecting method for misregistration of solder-resist layer of printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0621180A true JPH0621180A (en) | 1994-01-28 |
Family
ID=16022096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4176921A Withdrawn JPH0621180A (en) | 1992-07-03 | 1992-07-03 | Inspecting method for misregistration of solder-resist layer of printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0621180A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112818624A (en) * | 2021-01-06 | 2021-05-18 | 深圳沸石智能技术有限公司 | Method for generating printed circuit board design drawing, printed circuit board and manufacturing method thereof |
| CN113834827A (en) * | 2020-06-24 | 2021-12-24 | 江苏长电科技股份有限公司 | Multilayer circuit board and offset detection method thereof |
-
1992
- 1992-07-03 JP JP4176921A patent/JPH0621180A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113834827A (en) * | 2020-06-24 | 2021-12-24 | 江苏长电科技股份有限公司 | Multilayer circuit board and offset detection method thereof |
| CN113834827B (en) * | 2020-06-24 | 2024-04-12 | 江苏长电科技股份有限公司 | Multilayer circuit board and offset detection method thereof |
| CN112818624A (en) * | 2021-01-06 | 2021-05-18 | 深圳沸石智能技术有限公司 | Method for generating printed circuit board design drawing, printed circuit board and manufacturing method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19991005 |