JPS59106192A - Thick film multilayer board - Google Patents

Thick film multilayer board

Info

Publication number
JPS59106192A
JPS59106192A JP57215402A JP21540282A JPS59106192A JP S59106192 A JPS59106192 A JP S59106192A JP 57215402 A JP57215402 A JP 57215402A JP 21540282 A JP21540282 A JP 21540282A JP S59106192 A JPS59106192 A JP S59106192A
Authority
JP
Japan
Prior art keywords
thick film
film multilayer
resistor
conductor
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57215402A
Other languages
Japanese (ja)
Inventor
矢萩 覚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57215402A priority Critical patent/JPS59106192A/en
Publication of JPS59106192A publication Critical patent/JPS59106192A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の利用分野j 本発明は、抵抗体が絶縁基板上の絶縁層に内層化され、
搭載部品が該絶縁層上の上層パターン上に配置される厚
膜多層基板に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention j The present invention provides a method in which a resistor is internally layered in an insulating layer on an insulating substrate,
The present invention relates to a thick film multilayer substrate in which mounted components are arranged on an upper layer pattern on the insulating layer.

〔従来技術〕[Prior art]

従来、セラミブク基板などの絶縁基板上に回路パターン
が形成され、該回路パターンを被傑した絶縁層上に、ト
ランジスタ、ICなどの部品上塔載して(以下、かかる
部品を塔載部品という)回路パターンと電気的に接続し
、所望の電子回路全形成する厚膜混成集積回路?得るこ
とができるようにした厚膜多層基板が矧られている。か
かる厚膜多層基板には、回路パターン勿所望に形成する
ことがでさるとともに、数多くの搭載部品ケ取付けるこ
とができることから、複雑な電子回路をコンパクトに形
成することができるというオU点勿有している。
Conventionally, a circuit pattern is formed on an insulating substrate such as a ceramic board, and parts such as transistors and ICs are mounted on the exposed insulating layer (hereinafter, such parts are referred to as mounted parts). A thick film hybrid integrated circuit that electrically connects with circuit patterns to form the entire desired electronic circuit? Thick-film multilayer substrates that can be obtained are now available. Such a thick film multilayer board has the advantage that it is possible to form a circuit pattern as desired, and also to be able to attach a large number of mounted components, making it possible to form complex electronic circuits in a compact manner. are doing.

しかしながら、近年、電子装置などの小型、多機能化が
進むにつれ、厚膜多層基板にょっ1形成される電子回路
の規模ケ大型化する必要が生じ、このために、厚膜多層
基板も大型化するとともに、組み込1れる回路素子の数
も非常に増加し1いる。
However, in recent years, as electronic devices have become smaller and more multifunctional, it has become necessary to increase the scale of electronic circuits formed on thick film multilayer substrates, and for this reason, thick film multilayer substrates have also become larger. At the same time, the number of circuit elements that can be incorporated has also increased significantly.

そこで、(m米、搭載部品として厚膜多層基板の絶縁層
上に搭載きれていた抵抗体は、絶縁基板上に形成される
回路パターンに組み込まれ、その分だけ、搭載部品の数
を増やすことができるようにしている3、 第1図はかかる従来の厚膜多層基板の一例會示す断面図
であつ1.1はセラミ・ツク基板、2は下層導体、3は
抵抗体、4は絶縁層、5は上層導体、6はバイアホール
である。
Therefore, the resistors that could not be mounted on the insulating layer of the thick film multilayer board as mounted components will be incorporated into the circuit pattern formed on the insulated board, increasing the number of mounted components accordingly. 3. Figure 1 is a cross-sectional view showing an example of such a conventional thick film multilayer board, in which 1.1 is a ceramic substrate, 2 is a lower conductor, 3 is a resistor, and 4 is an insulating layer. , 5 is an upper layer conductor, and 6 is a via hole.

このような厚膜多層基板は、次のようにして形成される
Such a thick film multilayer substrate is formed as follows.

まず、セラミック基板1上に、下層導体2と抵抗体3と
からなる回路パターンが印刷焼成され、その上にガラス
などの絶縁層4が印刷焼成されて回路パターンが被覆さ
れる。この際、絶縁層4にはパイヤホール6も同時に形
成される。次に、絶縁層4上に、所定のパターンで上層
導体5が印刷焼成されるとともに、パイヤホール6に導
体の充填焼成がな芒れる。したがって、上層導体5は、
パイヤホール6を通して回路パターンの所定の位置の下
層導体2と電気的に接続されろ、このLうにして、厚膜
多層基板が完成する。
First, a circuit pattern consisting of a lower conductor 2 and a resistor 3 is printed and fired on a ceramic substrate 1, and an insulating layer 4 made of glass or the like is printed and fired thereon to cover the circuit pattern. At this time, a pie hole 6 is also formed in the insulating layer 4 at the same time. Next, the upper layer conductor 5 is printed and fired in a predetermined pattern on the insulating layer 4, and the conductor is filled and fired into the pie holes 6. Therefore, the upper layer conductor 5 is
It is electrically connected to the lower layer conductor 2 at a predetermined position of the circuit pattern through the wire hole 6. In this way, a thick film multilayer board is completed.

上層導体5は、塔載部品の取付ランドあるいは配線ラン
ドとなるものであって、欧句ランドには、塔載部品の端
子が半田によシ取付けられ、厚膜混成集積回路が形成さ
れる。
The upper layer conductor 5 serves as a mounting land or a wiring land for tower-mounted components, and terminals of tower-mounted components are attached to the lands by solder to form a thick film hybrid integrated circuit.

ところで、セラミック基板1上に形成される抵抗体3の
抵抗値は、印刷焼成されたときの抵抗体3の幅、厚ζな
どに依存するものであるから、印刷の不備などにより、
設定すべき抵抗値と大きく異なることもあり得るもので
あシ、抵抗体3の夫々についてチェックをする必要があ
る。
By the way, the resistance value of the resistor 3 formed on the ceramic substrate 1 depends on the width, thickness ζ, etc. of the resistor 3 when printed and fired.
It is possible that the resistance value differs greatly from the resistance value that should be set, so it is necessary to check each resistor 3.

ところが、上に述べたように、従来の厚膜多層基板にお
いては、抵抗体3の夫々は絶縁層4に内層化されている
ものであるから、個々の抵抗体3會直接チエヴクするこ
とができない。そこで、厚膜多層基板上に必要な全ての
搭載部品ケ取付け、半田付けなどにより組立てケ行なっ
た後、形成された電子回路の性能をチェックして厚膜多
層基板の良否を確認する方法がとられている。しかるに
、不良厚膜多層基板の発見は最終工程によって行なわれ
ることになり、不良な厚膜多層基板およびこれに取付け
たすべての塔載部品ケ廃棄せざる會得ず、塔載部品全無
駄にするばか力でなく、廃棄すべき不良な厚膜多層基板
に塔載部品ケ取付けるという無駄な作業時間ケ費やすこ
とになり、結局、厚膜多層基板ケもとに形成される厚膜
混成集積回路のコストアップケまねくことになる。
However, as mentioned above, in the conventional thick-film multilayer substrate, each of the resistors 3 is layered inside the insulating layer 4, so it is not possible to directly check each resistor 3. . Therefore, after assembling all the necessary components on the thick film multilayer board by attaching and soldering them, there is a method of checking the performance of the formed electronic circuit to confirm the quality of the thick film multilayer board. It is being However, since the defective thick film multilayer board is discovered in the final process, the defective thick film multilayer board and all the mounted parts attached to it have to be discarded, resulting in all the mounted parts being wasted. Not only is it a waste of effort, but a lot of wasted work time is wasted attaching components to a defective thick film multilayer board that should be discarded, and in the end, the thick film hybrid integrated circuit formed on the thick film multilayer board is damaged. This will lead to an increase in costs.

〔発明の目的j 本発明の目的は、上記従来技術の欠点を除き、絶縁層に
内層化された抵抗体音直接チェックすることができるよ
うにした厚膜多層基板ケ提供するにある。
[Object of the Invention] An object of the present invention is to provide a thick film multilayer substrate which eliminates the drawbacks of the above-mentioned prior art and allows direct checking of the resistance body sound built into the insulating layer.

〔発明の概要J この目的を達成するために、本発明は、絶縁層に内層化
された全ての抵抗体について、該絶縁層上に、該抵抗体
の端子に電気的に接続された上層導体r設けた点に特徴
がある。
[Summary of the Invention J To achieve this object, the present invention provides that for every resistor layered in an insulating layer, an upper layer conductor is provided on the insulating layer electrically connected to a terminal of the resistor. It is characterized by the provision of r.

〔発明の実施例j 以下、本発明の実施例7図面について説明する。[Embodiments of the invention j Embodiment 7 Drawings of the present invention will be described below.

第2図は本発明による厚膜多層基板の一実施例を示す断
面図であって、5′はチェック用上層導体、6′はバイ
アホールであシ、第1図に対応部分には同−符号全つけ
て説明會一部省略する・42図において、2つの抵抗体
3.3間に形成されている下層導体(これケ符号2′で
表わす月1.2つの抵抗体3.3の接触面近傍が、夫々
の抵抗体3.3の端子でもある。そし1、絶縁層4の下
履導体2′ヲ被覆する部分の一部に貫通する〕(イヤホ
ール6′ケ設け、絶線層4上に、)(イヤホール6′に
充填した導体金通して下層導体2′に電気的に接続され
たチェック用上層導体5′會設けている。かかるチェッ
ク用上層導体5′は、絶縁層4に内層化された各抵抗体
3ごとに設けるが、取付ランドや配線ランドとなる上層
導体5が接続された抵抗体3の端子に、新ためてチェづ
り用上層導体5′を接続すべく設ける必要はない。
FIG. 2 is a sectional view showing an embodiment of the thick film multilayer board according to the present invention, in which 5' is an upper layer conductor for checking, 6' is a via hole, and the parts corresponding to those in FIG. All the symbols are attached and some explanations are omitted. In Figure 42, the lower conductor formed between the two resistors 3 and 3 (this is denoted by the symbol 2') is the contact between the two resistors 3 and 3. The area near the surface is also the terminal of each resistor 3. An upper layer conductor 5' for checking is electrically connected to the lower layer conductor 2' through the conductor metal filled in the ear hole 6'. It is provided for each inner layered resistor 3, but it is necessary to newly connect the upper layer conductor 5' for chain hanging to the terminal of the resistor 3 to which the upper layer conductor 5, which serves as a mounting land or wiring land, is connected. There isn't.

そこで、抵抗体3は全て、その両端の端子が必ス上層導
体5、あるいは、チェック用上層導体5′のいずれかに
電気的に接続されていることになり、抵抗体3が絶縁層
4に内層化されていても、上層導体5、チェック用上層
導体5′によシ、各抵抗体3の抵抗清音1負接、かつ、
容易に測定することができる。しかるに、搭載部品ケ取
付ける前に、厚膜多層基板の簀、全なるチェックケ行な
うことがでさ、良品の厚膜多層基板についてのみ搭載部
品の取41け、組立てが可能となって、厚膜多層基板を
もとにした厚膜混成集積回路の歩留りが向上する。
Therefore, the terminals at both ends of all the resistors 3 are electrically connected to either the upper layer conductor 5 or the check upper layer conductor 5', and the resistors 3 are connected to the insulating layer 4. Even if it is an inner layer, the upper layer conductor 5, the upper layer check conductor 5', the resistance clear sound 1 negative connection of each resistor 3, and,
Can be easily measured. However, before mounting the mounted parts, it is not possible to thoroughly check the thickness of the thick film multilayer board. The yield of thick film hybrid integrated circuits based on multilayer substrates is improved.

不良な厚膜多層基板に、塔載部品を取付けるというよう
な無駄な作業を回避することができる。
It is possible to avoid wasteful work such as attaching mounting components to a defective thick film multilayer board.

なお、この実施例では、第1図に示した従来の厚膜多層
基板ケ作成するのと同じ方法で作成することができ、製
造工程が増加することはない。また、この実施例では、
上層導体5′(第2図)′に特別にチェック用としたが
、これを必要に応じて塔載部品の取付ランドとして用い
ることができ、この場合にも、チヱプク用としても機能
することはもちろんのことである。
Note that this embodiment can be manufactured by the same method as the conventional thick film multilayer substrate shown in FIG. 1, and the number of manufacturing steps is not increased. Also, in this example,
Although the upper layer conductor 5' (Fig. 2)' is specially used for checking, it can also be used as a mounting land for tower-mounted parts if necessary, and in this case, it can also function as a chip. Of course.

〔発明の効果J 以上説明したように、本発明によれは、絶縁層に内層化
をれた各抵抗体を、@接、かつ、容易にチェヴクするこ
とができ、しかるに、塔載部品の取付は前に良品、不良
品のチェヴク紮児全に行なうことができτ、形成される
厚膜混成集積回路の歩留シが向上するとともにコストダ
ウンヶはかることができ、上記従来技術の欠点を除いて
優れた機能の厚膜多層基板を提供することができる。
[Effect of the Invention J As explained above, according to the present invention, each resistor layered inside the insulating layer can be connected and easily checked, and the installation of tower-mounted parts can be easily performed. This method can be used to completely differentiate between good and defective products, improves the yield of thick film hybrid integrated circuits, and reduces costs. A thick film multilayer substrate with improved functions can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の厚膜多層基板の一例會示す断面図、第2
図は本発明による厚膜多層基板の一実施例を示す断面図
でおる。 1・・・セラミプク基板、2.2′・・・下層導体、3
・・・抵抗体、4・・・絶縁層、5・・・上層導体、5
′・・・チェック用上層導体、6.6′・・・バイアス
ホール。
Figure 1 is a cross-sectional view showing an example of a conventional thick-film multilayer board;
The figure is a sectional view showing an embodiment of the thick film multilayer substrate according to the present invention. 1... Ceramic board, 2.2'... Lower layer conductor, 3
...Resistor, 4...Insulating layer, 5...Upper layer conductor, 5
'... Upper layer conductor for checking, 6.6'... Bias hole.

Claims (1)

【特許請求の範囲】[Claims] 絶縁基板上に形成された抵抗体と下層導体とによる回路
パターンか絶縁層により被葎され、該絶縁層上に、バイ
アホール全通して前記回路パターンの前記下層導体と電
気的に接続された上層導体が形成された厚膜多層基板に
おいて、前記バイアホールおよび前記上層導体を前ロピ
抵抗体の端子ごとに設け、前記抵抗体の端子全前記絶縁
層の外部に導出することができるように構成したこと全
特徴とする厚膜多層基板。
A circuit pattern consisting of a resistor and a lower conductor formed on an insulating substrate is covered by an insulating layer, and an upper layer is electrically connected to the lower conductor of the circuit pattern through the entire via hole on the insulating layer. In the thick film multilayer substrate on which a conductor is formed, the via hole and the upper layer conductor are provided for each terminal of the front resistor, and all the terminals of the resistor can be led out to the outside of the insulating layer. Thick film multilayer substrate with all the features.
JP57215402A 1982-12-10 1982-12-10 Thick film multilayer board Pending JPS59106192A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57215402A JPS59106192A (en) 1982-12-10 1982-12-10 Thick film multilayer board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57215402A JPS59106192A (en) 1982-12-10 1982-12-10 Thick film multilayer board

Publications (1)

Publication Number Publication Date
JPS59106192A true JPS59106192A (en) 1984-06-19

Family

ID=16671726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57215402A Pending JPS59106192A (en) 1982-12-10 1982-12-10 Thick film multilayer board

Country Status (1)

Country Link
JP (1) JPS59106192A (en)

Similar Documents

Publication Publication Date Title
US5953213A (en) Multichip module
JPS62216259A (en) Manufacture and structure of hybrid integrated circuit
US4697204A (en) Leadless chip carrier and process for fabrication of same
KR920007120B1 (en) Manufacturing method of wiring substrate for surface mounting
JPH0210571B2 (en)
JPS59106192A (en) Thick film multilayer board
JP2925609B2 (en) Method for manufacturing semiconductor device
JPS5814621Y2 (en) printed wiring board
JPH05259372A (en) Hibrid ic
JPS63283051A (en) Substrate for hybrid integrated circuit device
JPS5823956B2 (en) Insatsu High Senban
US20040119155A1 (en) Metal wiring board and method for manufacturing the same
JPS6153852B2 (en)
JPH0722730A (en) Composite electronic component
JPH1051094A (en) Printed wiring board, and its manufacture
JPH0639479Y2 (en) Printed wiring board
JPH03136396A (en) Electronic circuit component, manufacture thereof and electronic circuit apparatus
JP3002857B2 (en) Bump electrodes and components with bump electrodes
JP2556412B2 (en) Circuit board for semiconductor device
JPH05259214A (en) Semiconductor device
JPS63226053A (en) Hybrid integrated chip module
JPH03116797A (en) Thick film surface package circuit
JPH0231794Y2 (en)
JPH04111460A (en) Hybrid integrated circuit device
JPH03255691A (en) Printed wiring board