JPS59105617A - Production of liquid crystal display device - Google Patents

Production of liquid crystal display device

Info

Publication number
JPS59105617A
JPS59105617A JP57216318A JP21631882A JPS59105617A JP S59105617 A JPS59105617 A JP S59105617A JP 57216318 A JP57216318 A JP 57216318A JP 21631882 A JP21631882 A JP 21631882A JP S59105617 A JPS59105617 A JP S59105617A
Authority
JP
Japan
Prior art keywords
gate
bar
electrode
transparent conductive
conductive film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57216318A
Other languages
Japanese (ja)
Other versions
JPH0334045B2 (en
Inventor
Hiroaki Kato
博章 加藤
Hirosaku Nonomura
野々村 啓作
Masataka Matsuura
松浦 昌孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP57216318A priority Critical patent/JPS59105617A/en
Publication of JPS59105617A publication Critical patent/JPS59105617A/en
Publication of JPH0334045B2 publication Critical patent/JPH0334045B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device

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  • Physics & Mathematics (AREA)
  • Liquid Crystal (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)

Abstract

PURPOSE:To display in high contrast without spoiling the visibility on a matrix liquid crystal display surface by forming a thin film transistor (TFT) using an anodizable metal for its gate electrode and a transparent conductive film for its gate bar and source bar on a substrate. CONSTITUTION:Electrode lines in line and row directions are formed of a gate bar 8 and a source bar 9 consisting of a transparent conductive film, and a gate electrode 10 is connected to the bar 8. A semiconductor layer 12 of a TFT is built up on said electrode through a gate insulating film 11. A source-drain electrode 13 is further formed, then the source electrode and the bar 9 are connected and the drain electrode and a picture element electrode 14 are connected, thereby constituting a TFT substrate. The bars are formed of a metal in this case and the gate bar of the transparent conductive film is formed by etching off the unnecessary part after the anodization of the required part and therefore even if a pinhole is generated in a resist, there is no obstruction in the growth of the anodized film and the yield is improved.

Description

【発明の詳細な説明】 く技術分野〉 本発明は各画素にスイッチング素子と[2て薄膜トラン
ジスタ(Thin Film Transistor、
以下’r F Tと略す)を配置した7トソツクス型液
晶表示装置の製造技術に関するものである。
[Detailed Description of the Invention] Technical Field> The present invention includes a switching element and a thin film transistor (Thin Film Transistor) in each pixel.
The present invention relates to a manufacturing technology for a 7-socks type liquid crystal display device in which a 7-socket type liquid crystal display device (hereinafter abbreviated as 'rFT) is arranged.

、〈従来技術〉 薄膜トランジスタは、近年、EL素子や液晶等を用いる
表示装置のスイッチング素子としてその応用か検討され
ている。しかし、本来の半導体デバイスに比べて特性が
劣りまた信頼性も低いため、未だ実用するには至ってい
ない。
, <Prior Art> In recent years, the application of thin film transistors as switching elements for display devices using EL elements, liquid crystals, etc. has been studied. However, they have inferior characteristics and low reliability compared to original semiconductor devices, so they have not yet been put into practical use.

一般に、T P Tは第1図に示すような構造である。Generally, TPT has a structure as shown in FIG.

lは絶縁基板、2はベースコート、3はゲート電極、4
はゲート絶縁膜、5,6は電極でソース、ドレインに対
応する。7はチャネルを形成する半導体層である。
l is an insulating substrate, 2 is a base coat, 3 is a gate electrode, 4
1 is a gate insulating film, and 5 and 6 are electrodes corresponding to a source and a drain. 7 is a semiconductor layer forming a channel.

絶縁基板IV?cはセラミックやガラスが用いらオする
。ベースコート2は、下地をなめらかな表面Vこするこ
と及び絶縁基板1から素子部へ汚染物質又は不純物イオ
ンが拡散するのを阻止するために設けられ、5i02 
、Si3N4 、A120BやTa205などが使われ
る。ゲート電極3は金属たとえばAu 、Cr 、AI
あるいはTaなどで蒸着によって形成される。ゲート絶
縁膜4としては、たとえば]0,5i02 。
Insulating substrate IV? C is made of ceramic or glass. The base coat 2 is provided to prevent the smooth surface V of the base from being rubbed and to prevent contaminants or impurity ions from diffusing from the insulating substrate 1 to the element portion, and is 5i02
, Si3N4, A120B, Ta205, etc. are used. The gate electrode 3 is made of metal such as Au, Cr, AI.
Alternatively, it is formed by vapor deposition of Ta or the like. The gate insulating film 4 is, for example, ]0,5i02.

A1203 、’ra205等が真空蒸着、CVDある
いは陽極酸化法等によって形成される。特に、絶縁性が
良好なことから、A1203やTa205等の陽極酸化
膜か広く用いられるO半導体7は、例えばa−8i(ア
モルファスシリコン)、p−5i(多結晶シリコン)。
A1203, 'ra205, etc. are formed by vacuum evaporation, CVD, anodic oxidation, or the like. In particular, the O semiconductor 7, which is widely used as an anodic oxide film such as A1203 or Ta205 due to its good insulation properties, is, for example, a-8i (amorphous silicon) or p-5i (polycrystalline silicon).

CdS、CdSe、Te等の一つを成分とし、真空蒸着
Vacuum evaporation using one of CdS, CdSe, Te, etc. as a component.

イオンプレーティンク、スパッタリンク、クロー放電等
の7種々の方法で形成される。電極5,6は例えばNi
、Cr、Auなとの金属の蒸着等で形成される。
It can be formed using seven different methods such as ion plating, sputter linking, and claw discharge. The electrodes 5 and 6 are made of Ni, for example.
, Cr, Au, etc., by vapor deposition.

TPTの動作は電界効果トランジスタと同じで、ソース
電極5とドレイン電極6間で半導体7中に流れる電流を
ゲート電極3に印加する電圧で制御する。
The operation of the TPT is the same as that of a field effect transistor, and the current flowing in the semiconductor 7 between the source electrode 5 and the drain electrode 6 is controlled by the voltage applied to the gate electrode 3.

このようなrFrは、その特徴として、ガラス基板上に
真空蒸着、スパンタリング、CVD等の確立さi上だ技
術により比較的容易に形成することかでき、前述の表示
装置Vこ適用した場合V(表示面の大形化を達成するこ
とができると期待さ肛る0上述の拐料でr F Tを形
成12、例えばTN−FEM(ツイストネマティック電
界効果)型のマトリックス型液晶表示装置の各画素にス
イッチング素子として配置した場合、ゲート・バー及び
ソース・バーもそれぞれゲート電極及びソース電極と同
じ金属材料を用いると、各画素の周囲に金属の枠が現わ
れ、表示が暗くなると同時に視角によ−ってはそれぞれ
のバーの反射のために表示品位を著しく低下させること
になり、スイッチング素子を具備することによる利点よ
りも逆にこの点での欠点が目立つ結果になる。その対策
としてT P Tの電極の部分のみに金属を用い、ゲー
ト・バー及びソース・バーに透明導電膜を用いれば上述
の欠点を解消することができる。TPTを用いたマトリ
・ノクス型液晶表示装置において、ゲートバー及びソー
スバーを透明導電膜で形成する方式については特願昭5
7−15201:3号にて出願されている。
A characteristic of such rFr is that it can be formed relatively easily on a glass substrate using established techniques such as vacuum evaporation, sputtering, and CVD. (It is expected that it will be possible to achieve a larger display surface.) Forming rFT with the above-mentioned nanoparticles12, for example, each of the TN-FEM (twisted nematic field effect) type matrix type liquid crystal display devices. When arranged as a switching element in a pixel, if the gate bar and source bar are made of the same metal material as the gate electrode and source electrode, respectively, a metal frame will appear around each pixel, darkening the display and changing the viewing angle. -, the display quality will be significantly degraded due to the reflection of each bar, and the disadvantages of this point will be more noticeable than the advantages of providing the switching elements.To counter this, T P The above-mentioned drawbacks can be overcome by using metal only for the electrode portion of TPT and using a transparent conductive film for the gate bar and source bar.In a Matri-Nox type liquid crystal display device using TPT, the gate bar and Regarding the method of forming the source bar with a transparent conductive film, a patent application was filed in 1973.
No. 7-15201:3.

第2図はゲートバー及びソースバーをそれぞれ透明導電
膜で形成したマドl)ックス型液晶表示装置の薄膜トラ
ンジスタ及びその周辺部の拡大構成図である。透明導電
膜から成るゲート・バー8とソース・バー9で行及び列
方向の電極ラインを構成し、ゲート・バー8にゲート電
極10を連結し。
FIG. 2 is an enlarged configuration diagram of a thin film transistor and its peripheral portion of a Madox type liquid crystal display device in which a gate bar and a source bar are each formed of a transparent conductive film. A gate bar 8 and a source bar 9 made of a transparent conductive film constitute electrode lines in the row and column directions, and a gate electrode 10 is connected to the gate bar 8.

てこの上にゲート絶縁膜11を介してTPTの半導体層
12を堆積し、更にソース・ドレイン電極13を形成す
るとともにソース電極とソース・バー9を連結しドレイ
ン電極と表示の絵素電極14を連結することにより T
 P Tの基板が構成されている。TPTの動作に応答
して絵素電極14に印加される電圧によりトントマトリ
ックス表示が実行される。以下、従来の方式に即Y7て
第2図Vこ示すゲート・バーとソース・バーをそれぞれ
透明導電膜で形成したTPT及びマトリックス型液晶表
示装置の製造方法について説明する。
A TPT semiconductor layer 12 is deposited on the lever via a gate insulating film 11, and a source/drain electrode 13 is further formed, the source electrode and the source bar 9 are connected, and the drain electrode and a display pixel electrode 14 are formed. By connecting T
A PT substrate is constructed. Tonto matrix display is performed by the voltage applied to the picture element electrode 14 in response to the operation of the TPT. Hereinafter, a method of manufacturing a TPT and matrix type liquid crystal display device in which the gate bar and source bar shown in FIG.

第3図は薄膜トランジスタ部の各製作工程を示す断面図
である。まずガラス等の絶縁基板15上にベースコート
16を施し、その上にI To (In20a→−5n
02) 、 5n02等の透明導電膜17を蒸着やスパ
ッタ等で500〜2000^程度の厚さに付着し、この
透明導電膜上に有機感光性材料により所望形状のマスク
パターンを形成した後、不要部分をエツチングすること
によりゲート・バーが形成される(第3図(A))。次
に陽極酸化されるべき金属、例えばAI、Ta等を蒸着
、スパッタやイオンブレーティング等で1000〜20
00λ程度付け、ゲート・バー上に薄膜トランジスタ部
となる領域を残し、不要となる領域をウェット・エンチ
ングあるいはドライ・エツチングにより除去してゲート
のパッド18を形成する(第3図(B))。上記基板上
に基板との密着性に優れかつ耐圧の大きいホトレジスト
19(例えばポジタイプのホトレジス1としてシブレイ
ファーイースト社のAZ−1850゜AZ−1470、
AZ1470Zや+300−37タイプ。
FIG. 3 is a cross-sectional view showing each manufacturing process of the thin film transistor section. First, a base coat 16 is applied on an insulating substrate 15 such as glass, and I To (In20a→-5n
02) A transparent conductive film 17 such as 5n02 is deposited to a thickness of approximately 500 to 2000^ by vapor deposition or sputtering, and a mask pattern of a desired shape is formed using an organic photosensitive material on this transparent conductive film. Gate bars are formed by etching the portions (FIG. 3A). Next, the metal to be anodized, such as AI, Ta, etc., is deposited by vapor deposition, sputtering, ion blasting, etc.
The gate pad 18 is formed by etching the gate pad 18 by etching about 00λ, leaving a region that will become a thin film transistor portion on the gate bar, and removing the unnecessary region by wet etching or dry etching (FIG. 3(B)). A photoresist 19 with excellent adhesion to the substrate and high pressure resistance is applied on the substrate (for example, as a positive type photoresist 1, AZ-1850゜AZ-1470 manufactured by Sible Far East Co., Ltd.
AZ1470Z and +300-37 types.

メルク社の5electiluxN 、コダック社のK
MPR−809等があり、ネガタイプのレジストとして
東京応化のOMR−83や感光性ポリイミド前駆体であ
る東しの)AトニースUR3100、メルク社の5el
ectilux HT R等の如く各種商品名のものが
市販されている。)を塗布し、ゲート電極上の所望の部
分に開口部を設けるように[7たマスクパターンを形成
する(第3図ニ))。上記開口部のゲート電極の金属を
ホウ酸アンモニウム水溶液、リン酸、クエン酸等の電解
液中にて電圧値約50〜200V程度で陽極酸化し、膜
厚500〜2000λの絶縁膜を形成してこの膜をゲー
ト絶縁膜2oとする(第3図(D))。ゲート絶縁膜2
oを形成した後、レジスト膜を剥離液や有機溶剤で除去
する(第3図(E))。
Merck's 5electiluxN, Kodak's K
There are products such as MPR-809, Tokyo Ohka's OMR-83 as a negative type resist, Higashino's Atonis UR3100, a photosensitive polyimide precursor, and Merck's 5el.
Various product names such as ectilux HTR etc. are commercially available. ) and form a mask pattern (FIG. 3D)) so as to provide an opening at a desired portion on the gate electrode. The metal of the gate electrode in the opening is anodized in an electrolytic solution such as ammonium borate solution, phosphoric acid, citric acid, etc. at a voltage of about 50 to 200 V to form an insulating film with a thickness of 500 to 2000 λ. This film is used as a gate insulating film 2o (FIG. 3(D)). Gate insulating film 2
After forming the resist film, the resist film is removed using a stripping solution or an organic solvent (FIG. 3(E)).

半導体膜21とソース・ドレイン電極22.23をそれ
ぞり、膜付着とエツチングやリフトオフ等によってパタ
ーン化する。また第3図(A)にて形成された透明導電
膜のソース・バー(図示せず)とソース電極を連結する
(第3図(F))。
The semiconductor film 21 and source/drain electrodes 22 and 23 are each patterned by film deposition, etching, lift-off, or the like. Further, the source bar (not shown) of the transparent conductive film formed in FIG. 3(A) and the source electrode are connected (FIG. 3(F)).

以上の工程により薄膜トランジスタが形成さオLる0 次に上記薄膜トランジスタを保護するためにSi3N4
.5i02または配向膜を兼用した有機膜等をCVD法
、フリダマCVD法、蒸着法または塗布法等により形成
し、ラビングまたは斜方蒸着法等による配向処理を行な
った後、対向基板とシール拐を介して貼り合わせること
により液晶セルが形成される。この液晶セルに液晶を注
入し、注入口を封止17て7トリンクス型液晶表示装置
が作製される。
Through the above steps, a thin film transistor is formed. Next, to protect the thin film transistor, Si3N4 is used.
.. 5i02 or an organic film that also serves as an alignment film is formed by a CVD method, a Fridama CVD method, a vapor deposition method, a coating method, etc., and after an alignment treatment is performed by rubbing or an oblique vapor deposition method, etc., it is bonded to a counter substrate through a seal strip. By bonding them together, a liquid crystal cell is formed. Liquid crystal is injected into this liquid crystal cell and the injection port is sealed 17 to produce a 7-Trinks type liquid crystal display device.

次にゲート電極の金属とゲート−パッドの透明導電膜を
連結する他の従来方式について第4図を参照[7ながら
説明する。基板24上にベースコ−1・25を施し、そ
の上に透明導電膜を付けたのちゲート・バー26及びソ
ース・バー(図示せず)となるべきパターンをホトレジ
ストにょ9パターン化し透明導電膜をエツチングする(
第4図(A))。
Next, another conventional method for connecting the metal of the gate electrode and the transparent conductive film of the gate-pad will be described with reference to FIG. Base coats 1 and 25 are applied on the substrate 24, and a transparent conductive film is attached thereon. After that, patterns that are to become gate bars 26 and source bars (not shown) are made into nine patterns using photoresist, and the transparent conductive film is etched. do(
Figure 4(A)).

この場合、第3図の例と異なり、ゲート絶縁膜が形成さ
れる部分には透明導電膜は存在しない。次に陽極酸化き
れるべき金属を付けた後エツチングによりパターン化し
、透明導電膜で形成したゲート中パー26間に架設する
ことにょ9ゲート電極27とし、ゲート電極27とゲー
ト・バー26を連結させる(第4図(B))。次に陽極
酸化する領域以外の部分をレジスト28でマスクして陽
極酸化処理し、ゲート絶縁膜29を形成する(第4図(
C)(D))。レジスト28を剥離し、ゲート電極27
゜ゲート絶縁膜29及びゲート・バー26の形成が完了
する(第4図(E))。半導体層30.ンース電4斐3
1及びドレイン電極32を形成し、薄膜トランジスタが
形成される(第4図(F))。以後の工程はt?iJ述
した辿りである。この方式ではゲート絶縁膜の下に透明
導電膜がなく、これによって、陽極酸化時に陽極酸化さ
iする金属のピンホールによる透明導電膜と電解液との
接触に起因する酸素発生とそれに伴う化成膜の損傷は免
れる。しかしながら、透明導電膜上のマスクのレジスト
にピンホールがあるかあるいは陽極酸化時の電圧に対し
てレジストの一部分に弱い部分があれば、レジストが絶
縁破壊を起し、電解液と下の透明導電膜とが接触して短
絡するため陽極酸化膜の成長に支障をきたす場合がある
In this case, unlike the example shown in FIG. 3, there is no transparent conductive film in the area where the gate insulating film is formed. Next, after applying a metal that can be anodized, it is patterned by etching, and is installed between the holes 26 in the gate formed of a transparent conductive film to form a gate electrode 27, and the gate electrode 27 and the gate bar 26 are connected ( Figure 4(B)). Next, a portion other than the area to be anodized is masked with a resist 28 and anodized to form a gate insulating film 29 (see FIG. 4).
C) (D)). The resist 28 is peeled off and the gate electrode 27 is removed.
The formation of the gate insulating film 29 and the gate bar 26 is completed (FIG. 4(E)). Semiconductor layer 30. Nsu Den 4hi 3
1 and a drain electrode 32 are formed to form a thin film transistor (FIG. 4(F)). The subsequent steps are t? This is the path described in iJ. In this method, there is no transparent conductive film under the gate insulating film, and this causes oxygen generation due to contact between the transparent conductive film and the electrolyte through pinholes in the metal being anodized during anodic oxidation, and the accompanying chemical formation. Damage to the membrane is avoided. However, if there are pinholes in the resist of the mask on the transparent conductive film or parts of the resist are weak against the voltage during anodic oxidation, the resist will cause dielectric breakdown and the electrolyte and the transparent conductor underneath will Contact with the film may cause a short circuit, which may hinder the growth of the anodic oxide film.

〈発明の目的〉 本発明は上記TPTを有する液晶表示装置に於いて、特
にゲート電極に陽極酸化可能な金属、ゲートバーに透明
導電膜を用いたTPTを基板上に形成し、マトリックス
型液晶表示装置を作製する製造技術を提供することを目
的とするものである。
<Object of the Invention> The present invention relates to a liquid crystal display device having the TPT described above, in particular, a matrix type liquid crystal display device in which a TPT using an anodizable metal for the gate electrode and a transparent conductive film for the gate bar is formed on a substrate. The purpose of this research is to provide a manufacturing technology for producing .

〈実カイ1汐り〉 第5図は本発明の一実施例を説明するTPT基板の製造
工程図であり、(A)乃至(H)は断面図、(A’)乃
至(H’)はそれぞれ対応する平面図である。ベースコ
ートを施した基板33上に陽極酸化可能な金属を付け、
エツチングによりゲート・バー34を形成する(第5図
(A)(Aつ)。次にゲート・バー34上のゲート絶縁
膜となる領域以外の部分をホトレジスト35でマスクす
る(第5図(B) (B’ ) )。露出しているゲー
ト・バー34の陽極酸化を行なって厚さ500〜300
0λ程度のゲート絶縁膜36を形成する(第5図(C)
 (C’) )。次にマスクのホトレジストを剥離液ま
たは有機溶剤で取り除く(第5図(D) (D’) )
。ゲート・バー34の陽極酸化した部分及びその両端の
陽極酸化されていない金属のうち、後に形成される透明
導電膜のゲート・バーと連結するために必要な部分をホ
トレジスト37でマスクする(第5図(E) (E’)
 )。マスクされた部分以外のゲート・バー34をエツ
チングで除去した後、ホトレジスト87を取り除く(第
5図CF) (F’) )。
<Actual scale 1> Fig. 5 is a manufacturing process diagram of a TPT substrate explaining one embodiment of the present invention, (A) to (H) are cross-sectional views, and (A') to (H') are cross-sectional views. FIG. 3 is a corresponding plan view. A metal that can be anodized is attached on the base coated substrate 33,
A gate bar 34 is formed by etching (FIG. 5(A) (A). Next, a portion of the gate bar 34 other than the region that will become the gate insulating film is masked with a photoresist 35 (FIG. 5(B)). ) (B') ).Exposed gate bar 34 is anodized to a thickness of 500 to 300 mm.
A gate insulating film 36 with a thickness of about 0λ is formed (FIG. 5(C)).
(C') ). Next, remove the photoresist on the mask using a stripper or organic solvent (Figure 5 (D) (D')).
. Of the anodized portion of the gate bar 34 and the non-anodized metal at both ends thereof, the portion necessary for connection with the gate bar of the transparent conductive film to be formed later is masked with a photoresist 37 (fifth Figure (E) (E')
). After removing the gate bar 34 other than the masked portion by etching, the photoresist 87 is removed (FIG. 5CF) (F')).

この上にITO,5n02等の透明導電膜38を蒸着法
あるいはスパッタリング法等で堆積する(第5図(G)
 (G’) )。透明導゛屯膜38をホトレジストでマ
スクした後、エツチングすることによりパターン化し7
ゲート・/<−とする。ゲート・パーは金属部と透明導
電膜とが重なった状態で連結される(第5図(+1) 
(H’) )。以後の工程は前述[7た如くであり、ゲ
ー)・絶縁膜36上VC硫化物、セレン化物、Te、ア
モルファスシリコン、多結晶シリコン等の半導体層を堆
積1〜だ後、ソース電極及びドレイン電極を形成[7、
T P Tとする。TPTの基板への配置d第2図と同
様な構成と[7、これを液晶表示装置のセル基板の一方
としてこのTPT基板に対向基板を接着し7、その間隙
にツイストネマティック溝端等の液晶層を注入する。T
 P Tを動作させるとともに液晶層の電気光学効果を
利用することによりドツトマトリックス型の表示を実行
することかできる。従来では金属のゲート電極と透明導
電膜のゲート・パーを形成したのちVこ陽極酸化を行な
ったか、本実施例では金属でパーを形成し、必要部分を
陽極酸化したのち、不要な部分を工・ンチングで取V除
き透明導電膜のゲート・パーを形成する。従って、マス
クのレジストにピンホールか生じて陽極酸化時Vこ電解
液がレジスト中に滲みこんでも、接触するのは陽極酸化
可能な金属であるのでその部分は直ちに陽極酸化されて
絶縁膜となりカバーされるため本来の陽極酸化膜の成長
に支障をきたさない。またピンホール部の絶縁膜は面積
か小さいのでのちの不要金属部のエツチング時にリフト
オフされ、工程の歩留りの点でも本実施例の製造方法は
優れた結果を得ることができる。
A transparent conductive film 38 of ITO, 5n02, etc. is deposited on this by vapor deposition or sputtering (see Fig. 5(G)).
(G') ). After masking the transparent conductive film 38 with photoresist, it is patterned by etching.
Gate /<-. The gate pad is connected with the metal part and the transparent conductive film overlapping (Figure 5 (+1)
(H') ). The subsequent steps are as described in [7] above.After depositing semiconductor layers such as VC sulfide, selenide, Te, amorphous silicon, and polycrystalline silicon on the insulating film 36, source and drain electrodes are formed. form [7,
T P T. Arrangement of TPT on the substrate dA structure similar to that shown in Fig. 2 [7. This is used as one of the cell substrates of a liquid crystal display device, and a counter substrate is bonded to this TPT substrate 7. A liquid crystal layer such as twisted nematic groove ends is placed in the gap between the two. inject. T
By operating the PT and utilizing the electro-optic effect of the liquid crystal layer, it is possible to perform a dot matrix type display. Conventionally, after forming a metal gate electrode and a gate/par of a transparent conductive film, anodization was performed.・Remove V by nching to form a gate/par of transparent conductive film. Therefore, even if a pinhole occurs in the resist of the mask and the electrolyte seeps into the resist during anodic oxidation, the contact is made with a metal that can be anodized, so that part is immediately anodized and becomes an insulating film to cover it. This does not interfere with the growth of the original anodic oxide film. Further, since the area of the insulating film in the pinhole portion is small, it is lifted off later when unnecessary metal portions are etched, and the manufacturing method of this embodiment can obtain excellent results in terms of process yield.

〈発明の効果〉 以上詳述した製造方法でパーの部分を透明導電膜にして
マトリックス型液晶表示装置を製作[7たところ、薄膜
゛トランジスタ自体は安定な電気的特性か再現性良く得
られ、その上に表示装置と[7てもTN−FEMのみな
らずゲストホスト型や反射型、透過型のいかなる表示モ
ードに対しても表示面の「見え」を損うことなく高コン
トラストの表示が可能になり、TPTを備えたことによ
る利点を大いに発揮することができた。
<Effects of the Invention> Using the manufacturing method detailed above, a matrix type liquid crystal display device was manufactured by using a transparent conductive film in the outer part. On top of that, the display device and [7] can display high contrast without impairing the "visibility" of the display surface, not only in TN-FEM but also in any display mode such as guest-host type, reflective type, and transmissive type. , and was able to take full advantage of the benefits of having TPT.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は′rF′Fの一般的な構造の1例を示す断面図
である。第2図はマトリックス型液晶表示装置のT I
” T及びその周辺部の拡大構成図である0第3図及0
・第4図はそれぞれ従来のI’FTの各製作二[程を示
す断面図である。 第5図は本発明の一実施例を説明するT P T基板の
製造工程図である。 33・・基板、34・・ゲート・パー、36・・ゲート
絶縁膜、38 ・透明導電膜。 代理人 弁理士 福 士 愛 彦(他2名)第 l 図 (Aj −一一一一一二;〜へy
FIG. 1 is a sectional view showing an example of a general structure of 'rF'F. Figure 2 shows the T I of a matrix type liquid crystal display device.
” Figure 3 and 0 are enlarged configuration diagrams of T and its surroundings.
・FIG. 4 is a sectional view showing each step of manufacturing a conventional I'FT. FIG. 5 is a manufacturing process diagram of a TPT substrate explaining one embodiment of the present invention. 33... Substrate, 34... Gate par, 36... Gate insulating film, 38 - Transparent conductive film. Agent Patent attorney Aihiko Fukushi (and 2 others) Figure l (Aj -111112;~hey

Claims (1)

【特許請求の範囲】[Claims] 1 基板上に形成されたゲート電極となる金属に陽極酸
化してゲート絶縁膜を形成した後、透明導電膜を堆積し
、前記金属の陽極酸化されない両端部と前記透明導電膜
から成る電極ラインを連結してゲート電極ラインを形成
し、前記ゲート絶縁膜上に薄膜トランジスタを構成する
とともに前記基板を一方のセル基板として液晶表示セル
を作製することを特徴とする液晶表示装置の製造方法。
1. After anodizing the metal that will become the gate electrode formed on the substrate to form a gate insulating film, a transparent conductive film is deposited, and an electrode line consisting of both ends of the metal that is not anodized and the transparent conductive film is formed. 1. A method of manufacturing a liquid crystal display device, characterized in that a gate electrode line is formed by connecting the substrates, a thin film transistor is formed on the gate insulating film, and a liquid crystal display cell is manufactured using the substrate as one cell substrate.
JP57216318A 1982-12-08 1982-12-08 Production of liquid crystal display device Granted JPS59105617A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57216318A JPS59105617A (en) 1982-12-08 1982-12-08 Production of liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57216318A JPS59105617A (en) 1982-12-08 1982-12-08 Production of liquid crystal display device

Publications (2)

Publication Number Publication Date
JPS59105617A true JPS59105617A (en) 1984-06-19
JPH0334045B2 JPH0334045B2 (en) 1991-05-21

Family

ID=16686644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57216318A Granted JPS59105617A (en) 1982-12-08 1982-12-08 Production of liquid crystal display device

Country Status (1)

Country Link
JP (1) JPS59105617A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01219721A (en) * 1988-02-19 1989-09-01 Internatl Business Mach Corp <Ibm> Metal insulator construction and liquid crystal display device
EP0556822A2 (en) * 1992-02-19 1993-08-25 Hitachi, Ltd. Reflective type liquid crystal display
US6713783B1 (en) 1991-03-15 2004-03-30 Semiconductor Energy Laboratory Co., Ltd. Compensating electro-optical device including thin film transistors
US6839098B2 (en) * 1987-06-10 2005-01-04 Hitachi, Ltd. TFT active matrix liquid crystal display devices
CN100378782C (en) * 2003-11-29 2008-04-02 三星Sdi株式会社 Light emitting display device and display panel thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2813187C (en) 2010-11-18 2018-09-11 Teijin Frontier Co., Ltd. Woven fabric and garment

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6839098B2 (en) * 1987-06-10 2005-01-04 Hitachi, Ltd. TFT active matrix liquid crystal display devices
US6992744B2 (en) 1987-06-10 2006-01-31 Hitachi, Ltd. TFT active matrix liquid crystal display devices
US7196762B2 (en) 1987-06-10 2007-03-27 Hitachi, Ltd. TFT active matrix liquid crystal display devices
US7450210B2 (en) 1987-06-10 2008-11-11 Hitachi, Ltd. TFT active matrix liquid crystal display devices
JPH01219721A (en) * 1988-02-19 1989-09-01 Internatl Business Mach Corp <Ibm> Metal insulator construction and liquid crystal display device
US6713783B1 (en) 1991-03-15 2004-03-30 Semiconductor Energy Laboratory Co., Ltd. Compensating electro-optical device including thin film transistors
EP0556822A2 (en) * 1992-02-19 1993-08-25 Hitachi, Ltd. Reflective type liquid crystal display
EP0556822A3 (en) * 1992-02-19 1994-08-31 Hitachi Ltd
CN100378782C (en) * 2003-11-29 2008-04-02 三星Sdi株式会社 Light emitting display device and display panel thereof

Also Published As

Publication number Publication date
JPH0334045B2 (en) 1991-05-21

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