JPS59105359A - Image pick-up element - Google Patents

Abstract

PURPOSE:To contrive the great improvement of sensitivity by a method wherein the signal accumulated capacitance of each photosensitive cell arranged along at least one line close to a memory part is made larger than that of each photosensitive cell arranged along other lines. CONSTITUTION:The photosensitive part 1 has the number of photosensitive cells in a vertical direction, i.e., number of lines of the arrangement of lines and rows set at the number nearly equal to that of scanning lines constituting a television frame, about 490. For the number of the cells in a horizontal direction, i.e., number of the rows of the arrangement of lines and rows, the number corresponding to a color sub carrier frequency, generally about 390 or 570, is adopted. The memory part 3 has the number equal to that of the rows of the arrangement of the photosensitive cells in the photosensitive part 1 for the number of the memory cells in a horizontal direction, i.e., number of the rows of the arrangement of lines and rows. In the arrangement of the photosensitive cells in the photosensitive part 1, each photosensitive cell arranged along the final line close to the memory part 3 is so set as to have the signal accumulated capacitance 1.5-2 time as large as that of each photosensitive cell arranged along other lines represented by numerals 2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an image sensor, and particularly to a photosensitive section having a plurality of photosensitive cells arranged in rows and columns, and a storage section for storing signals from the photosensitive section. The invention relates to an image sensor equipped with a metal fitting.

(Prior Art) The above-mentioned image sensor is well known as a frame transfer type image sensor. Conventionally, in a frame transfer type image sensor, the number of photosensitive cells in the vertical direction of the photosensitive section is limited. (
For example, in the case of the NTSC system, the number of scanning lines constituting one television frame is 52.
The number of signals is 245, which is about half of the five, and since each photosensitive cell has the functions of exposure and transfer, the signal that can be accumulated at one time is equivalent to 245 scanning lines, that is, one frame. After reading out the signal for one field, the effective photosensitive area of the photosensitive cell is moved and imaged.
If you read out the signal for one new field next time,
An image of 4 minutes per frame was obtained using interlace operation.

This type of system is extremely suitable for interlaced television systems, and can provide high-resolution images despite the small number of photosensitive cells.

However, the size of each photosensitive cell and its sensitivity are naturally limited, and therefore the imaging sensitivity of the photosensitive section is limited. Although various efforts have been made to improve the sensitivity of elements, no definitive solution has yet been found.

(Purpose) The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a novel image sensor as described above, which can dramatically improve its sensitivity. This is its main purpose.

Another object of the present invention is to provide an image sensor suitable for frame recording in a 2-field-1-frame still video system.

That is, in recent years, a still video camera, or video photography, is used to capture an image using a solid-state image sensor such as a CCD instead of a conventional silver halide film, and magnetically record the still video signal. Research and development efforts have begun to be carried out, but if the above-mentioned conventional movie/video system frame-transfer type image sensor is used in such a system, If you try to record frames to obtain high image quality, one frame will be temporally shifted by a small amount of L7, for example, if you think of a television signal, it will be 176.
This has the disadvantage of being composed of two fields shifted by 0 seconds, resulting in an unsightly image when a moving subject is captured.However, another object of the present invention is to The object of the present invention is to provide an image pickup device suitable for frame recording in a still video system that can eliminate such inconveniences.

Other objects of the invention will become apparent from the description that follows, with reference to the accompanying drawings, in which: FIG.

(Embodiment) First, reference will be made to FIG. 1 showing a schematic configuration of an embodiment of the present invention. For example, in this element, N
When considering the application of the TSC method to a television system, the number of photosensitive cells in the vertical direction, that is, the number of rows in the row and column arrangement, is approximately equal to the number of scanning lines constituting one television frame. An equal number, approximately 490, is set. That is,
It has approximately twice the number of rows of photosensitive cells as a conventional 7-frame transfer type image sensor. The number of cells in the horizontal direction, that is, the number of columns in the row and column arrangement, is usually about 390 or 570.
The number corresponding to the color sub-carrier frequency is adopted. In FIG. 1, only eight and four cells in the vertical (column) and horizontal (row) arrays (ie, an 8×4 array) are shown for ease of explanation.

3 is a memory for storing signals from the photosensitive section 1;
The number of storage cells in the horizontal direction, ie, the number of columns in the row and column arrangement, is equal to the number of columns in the arrangement of photosensitive cells in the photosensitive section 1.

On the other hand, the number of memory cells in the vertical direction, ie, the number of rows in the row and column arrangement, is half the number of rows in the arrangement of photosensitive cells in the photosensitive section 1, that is, about 245.

Of course, these numbers may be changed somewhat as necessary.

For simplicity, FIG. 1 shows only four cells in each of the vertical (column) and horizontal (row) arrays (ie, a 4×4 array). Therefore, this memory section 3 is composed of the same number of memory cells as the number of memory cells in the memory section (C) of the conventional frame transfer type CCD image sensor.

Here, in the arrangement of the photosensitive cells in the photosensitive section 1,
According to the invention, each photosensitive cell arranged along at least the last row near the storage section 3, denoted 2',
Its signal storage capacity is about 1 for the signal storage capacity of each photosensitive cell arranged along the other rows, denoted by 2.
．． It is set to have a signal storage capacity of about 5 to 2 times. Further, each memory cell indicated by 4 in the memory section 3 is set to have a signal storage capacity approximately equal to that of the photosensitive cell 2'.

That is, in this embodiment, as will be described in detail later, although the photosensitive section 1 generates a signal equivalent to one television frame,
When transferring this to the storage section 3, the addition of two rows of signals is performed in the last row, which has a large-capacity photosensitive cell 2' array, so that about half the number of scanning lines for one frame is added. The system is designed to improve the effective imaging sensitivity of the photosensitive section 1 by forming a signal corresponding to the number of scanning lines, that is, a signal for one field, and obtaining this signal through the storage section 3. According to calculations, the sensitivity is doubled. Of course, the combination of the two lines to be added is changed between the 17th yield and the second field, and as a result, an interlace effect is obtained.

Here, the addition of the row signals obtained by the photosensitive section 1 is
Among these, the one that utilizes the arrangement of the photosensitive cells 2' will be described in detail later.Normally, the photosensitive section 1 is provided with an anti-blooming section for each predetermined column. , even if signal overflow occurs due to signal addition, the overflow is prevented by the anti-pluming section.
This is because the aim is to have the advantage that the flow can be absorbed and pluming can be prevented. Therefore, from this point of view, it is easy to understand that the signal addition section is not particularly limited to the last row of the photosensitive section 1. however,
Providing an adder in the middle of a column has the disadvantage of having to increase the capacity of the cells in subsequent rows, so it is easy to understand that the last row is best. Further, as a modification thereof, it is also possible to have a configuration in which the number of 10 rows of the photosensitive section is increased by, for example, one row, this is used as an adding section, and this is also shielded from light together with the storage section.

Increasing the capacity of the photosensitive cell 2' in the photosensitive section 1 and the memory cell 4 in the storage section 3 relative to the photosensitive cell 2 is achieved by the above-mentioned 2.
This configuration is required to form a shift field signal by adding signals for rows. In FIG. 1, the photosensitive cell 2' and the memory cell 4 are shown with different sizes compared to the photosensitive cell 2, but this conceptually shows the size relationship of the signal storage capacity; It is not necessarily the case that the dimensions differ so greatly.

5 is a horizontal output register for reading signals from the storage section 3, and the number of cells in the horizontal direction of the photosensitive section 1 and the storage section 3;
That is, it is configured as a column of charge transfer registers having charge transfer cells 6 of approximately the same number as the number of columns. 7 is an amplifier that converts the charge transferred from the horizontal output register 5 into a voltage.

8 is a transfer unit additionally provided between the photosensitive section 1 and the storage section 3 when the image pickup device of the present invention is applied to frame recording in a 2-field-1-frame still video system. and an intermediate register for output, which is configured as a row of charge transfer registers having charge transfer cells 9 of which the number is approximately equal to the number of cells in each horizontal direction of the photosensitive section 1 and the storage section 3, that is, the number of columns. has been done.

As will be described in detail later, this intermediate register 8 alternately stores each row signal from the photosensitive section 1 in the storage section 3 when applied to frame recording in a 2-field-1-frame still video system. The signal of the first field is transmitted through the amplifier 10 and outputted through the output amplifier 10.
The second field signal is obtained through the amplifier 7, and the signal for one frame generated at the same time in the photosensitive section 1 is divided into two fields and taken out, thereby solving the above-mentioned problem. In other words, the inconveniences that occur when a field compatible image pickup device applied to a movie video system is used for frame recording in a still video system can be solved.

Incidentally, when the above-mentioned image pickup device is applied to a movie video system, the above-mentioned intermediate register 8 is operated exclusively to transfer the accumulated signal of the photosensitive cell 2' of the photosensitive section 1 to the storage section 3. Therefore, the signal storage capacity of each charge transfer cell 9 constituting the intermediate register 8 is set to be approximately equal to that of the photosensitive cell 2' and the memory cell 4. Although the explanation will be given later, this also applies to the charge transfer cells 6 constituting the horizontal output register 5.

Now, conventionally, there are several methods for transferring charge in such a frame transfer type image sensor (COD), such as a single-phase drive method, a two-phase drive method, a three-phase drive method, and a four-phase drive method. Although any of these can be applied to the configuration of the image sensor of this embodiment, in order to simplify the explanation below, we will take the case where a single-phase drive method is adopted as an example and use the photosensitive method shown in FIG. The specific configuration of the section 1, intermediate register 8, storage section 3, and horizontal output register 5 will be explained using FIG.

The single-phase drive method employed here is, for example, the method described in Japanese Patent Laid-Open No. 11394/1983, and its details will be discussed in the description of the configuration of the image sensor of this example. , is not necessary and will be omitted.

In Figure 2, C8 is a channel stop to prevent charge mixing between cells in the horizontal direction, AB is an anti-plumbing no (1 NOA), and OG is an overflow drain. - Gate and OD indicate overflow drain, respectively.

In addition, with the configuration shown in Fig. 2, the chain stop C
8, Anti Blooming / (1 Noah AB, Over Flow Drain Kate OG, Over Flow Drain
The reason for arranging the drain OD is that it is possible to easily reduce the size of the element and increase the number of pixels without significantly reducing the element sensitivity, and in addition, it is possible to obtain a high-quality television signal. be. Incidentally, such a configuration is described in, for example, Japanese Patent Laid-Open No. 55-56789.

Reference numeral 21 indicates a portion of the photosensitive portion 1 where the polysilicon electrode force is applied, and this electrode portion 21 consists of regions I and H having different potential states in silicon. Reference numeral 22 denotes a portion where a virtual electrode is formed in the silicon, and is made up of regions 1 and 2 having different potential states in the silicon. In the vertical direction, one photosensitive cell is constructed from the regions I to IV.

23 indicates an area of the intermediate register 8. This region is formed in a comb-tooth shape with diagonal lines applied to the polysilicon electrode, and the potential state under this polysilicon electrode is different.

It is divided into areas ′ and ita. Here, the potentials of the regions ■' and I'a are the same, but
Separated by channel stop. ■′ and ■′
The areas 1 and 2 of the virtual electrode section 22 of the photosensitive section l are respectively
The potential is set to be the same as the area of . 24.2
5 denotes an electrode section and a virtual electrode section of the storage section 3 which are configured similarly to the electrode section 21 and the virtual electrode section 22 of the photosensitive section 1, respectively, and III, 1ull, III, r
Each region of v"' is 1, I[, II in the photosensitive section 1, respectively.
This corresponds to regions I and IV.

Note that one memory cell is constructed from regions III to IVII.

FIG. 3 shows the internal potential state of the image sensor having the configuration shown in FIG.

In FIG. 3, 30 is a polysilicon electrode of the photosensitive section 1 corresponding to the area 21 of FIG. is applied. The area below this polysilicon electrode 3° is divided into regions I and 2, as explained in FIG. 2, and the region 2 has a higher potential state than the region H.

The dotted line in FIG.

As for the potential of the virtual electrode portion 22 in FIG. 2, the potential in the area marked with ■ is slightly higher than that in the area marked with Ar, as shown in FIG. Further, the potential of this portion is always kept constant, independent of the voltage applied to the polysilicon electrode 3°. Therefore, polysilicon electrode 3o
If a constant voltage is applied, that is, if a high negative voltage as in the previous example is applied, charges will be accumulated in the region of the virtual electrode section 22, and a pulsed voltage will be applied to momentarily lower the potential of the electrode 30. If the potential is set to a negative or positive state, charge is transferred.

31 indicates a polysilicon electrode of the second intermediate resistor 8. This polysilicon electrode 31 is connected to the polysilicon electrode 30 of the photosensitive section 1. etc., and an independent voltage is applied. The potential of each region of this intermediate register 8 is as shown below the polysilicon electrode 31 in the figure.

32 indicates a polysilicon electrode of the storage section 3; The potential of each area of this storage section 3 is similar to that of the photosensitive section 1. 33 indicates a polysilicon electrode of the horizontal output register 5. The configuration of this horizontal output register 5 is similar to that of the intermediate register 8, but there is a slight difference in that the portion indicated by 34 on one side is closed by a channel stop cs.

The movement of charges in the intermediate register 8 will be explained below. The electric charges accumulated in the region 3 of the photosensitive section 1 can be removed by applying a pulse voltage to the polysilicon electrode 30.
As shown by the solid line in FIG. 3, the potential in the areas 1 and ] decreases and is transferred to the next area IV. If this 1V region is in contact with the 1' and '' regions of the intermediate resistor 8, and a negative or positive potential is applied to the polysilicon '14131 of the intermediate resistor 8, I' and ■
The potential in the area ' becomes the potential state shown by the solid line in FIG. 3, and the charge in the area ■ enters the area ■' through the area ■'. Next, when a high negative potential is applied to this polysilicon electrode 31, each potential in the regions ■' and ■' becomes the state shown by the dotted line in FIG.
The charges in the region ' are transferred to the region ■' (having a constant potential, indicated by a dotted line) through the region ■' (having a constant potential, indicated by a dotted line). At this time, storage unit 3
When a slightly negative or positive voltage is applied to the polysilicon electrode 32 of
The potential in the region IIl decreases as shown by the solid line in Figure 3, and the charge in the region ■' passes through the region Itr.
will be transferred to the area of

In this way, the charges transferred to the Ill region of the storage section 3 are transferred to the potentials of the I'' and 1ull regions as shown in FIG. As shown by the dotted line, the data is transferred to the IVI+ area through the area ■'.

Therefore, when a voltage as a drive signal is applied to the polysilicon electrode 32, the accumulated charge from K becomes ■''→Ir1l→■l
+ and finally reaches the horizontal output register 5, and can be read out to the outside through this horizontal output register 5.

The charge transfer mechanism described above is based on the conventional single-phase drive frame transfer type C which is not equipped with an intermediate register 8.
This is exactly the same as in the case of a CD image sensor.

Next, the flow of charges when a signal is read out to the outside through the intermediate register 8 will be explained.

The charges transferred to the ff' area of the intermediate register 8 are:
In the above operation, a slightly negative or positive potential is applied to the polysilicon electrode 32 of the storage section 3 and transferred to the storage section 3, and this high negative voltage on the polysilicon electrode 321C is applied to maintain the potential in the Ill and I'll areas of the storage unit 3 as shown by the dotted line in FIG.
By applying a pulsed voltage to the polysilicon electrode 31 of the intermediate resistor 8, the potentials in the regions 1' and ■' are alternately shifted to the states shown by the solid lines and dotted lines in FIG. The charge is transferred to the ■“→■′→■′→■′ area in the horizontal direction (direction perpendicular to the plane of the paper in Figure 3),
It is output as a voltage to the outside through the amplifier 10 in FIG.

Next, the operation when actually applied as an image sensor in a camera will be explained using FIG. 4.

FIG. 4(a) shows the operation sequence when applying the above image sensor to a still video camera and FIG. 4(b) shows the operation sequence when applying the image sensor to a conventional movie video camera. The operation sequences for each are shown below.

First, the operation when applied to a still video camera will be explained.

In a-1 of FIG. 4(a), immediately before exposure, i.e., imaging, charges accumulated due to dark current etc. are cleared through the over-70-drain OD (FIG. 2), or
This shows an all-clear mode in which the image sensor is operated at high speed and the charge is discharged to the outside for clearing.

Next, the shutter opens at a-2, and the exposure state, that is, the signal generation/accumulation mode is entered at the photosensitive area l, and then,
At step a-3, the intermediate register 8 changes to the read mode of the first field's worth of signals.

In this mode, after a predetermined exposure time, the shutter is closed, image signals (charges) are generated and accumulated in each photosensitive cell of the photosensitive section 1, and then the accumulated charges of the cells of the photosensitive section 1 are transferred two rows at a time. do. That is, in the case of the example shown in FIG.
, 4) are transferred to the memory cells indicated by [:4.1] to [4,4) in the storage section 3 through the intermediate register 8, The accumulated charge of the photosensitive cell, denoted by ', is transferred to the intermediate register 8. (Hereinafter, for a photosensitive cell, its address is indicated by (X, Y),
Furthermore, for memory cells, the address will be indicated from the tail (CX, Y)]. ) Similarly, the accumulated contents of the photosensitive cells in each of the other rows are also transferred two rows at a time. This results in (3
,1)~(3,4),(4,t)~(4°4),(5,
1) ~ (5, 4), (6, 1) ~ (6, 4), (7, 1
,)~(7,4), (8°1)~(8,4) The accumulated charges of each photosensitive cell are (1,1)~(1,4), (2
, 1) to (2, 4), (3, 1) to (3, 4), (4° 1) to (4, 4), (5, 1) to (5, 4).

The signals are transferred to photosensitive cells indicated by (6,1) to (6,4).

After charges are transferred for two rows in this manner, the charges transferred to the intermediate register 8 are outputted to the outside as a voltage via the amplifier 10. That is, as described above, the intermediate register 8
The accumulated charges of the photosensitive cells shown as (2.degree. 1) to (2, 4) transferred to are serially converted into voltages and output.

Thereafter, the charges accumulated in each photosensitive cell of the photosensitive section 1 are transferred again for two rows. As a result, the charges transferred to the photosensitive cells shown as (1,1) to (1,4), that is, (3,1) to
The accumulated charge of the photosensitive cell shown as (3, 4) is stored in the intermediate register 8.
The charges transferred to the memory cells indicated by ('4.1E to [4,4] in the memory unit 3 through Time (4,1)
The accumulated charge of the photosensitive cell indicated by .about.(4,4) is transferred to the intermediate register 8. Also, at this time, the charges transferred to the storage cells of each row of the storage section 3 are transferred for one row. Therefore, last time [4
,1:]~C4,4],
That is, the charges accumulated in the photosensitive cells indicated by (1,1) to (1,4) during exposure are transferred to the memory cells indicated by [3,1) to (3,4). After this, the readout operation of the charges transferred to the intermediate register 8 is performed again, and the accumulation of charges in the photosensitive cells shown at (4, 1) to (4, 4) at the time of exposure, transferred to the intermediate register 8 as described above. Charge is serially converted into voltage and output. Thereafter, in the same manner, the charges accumulated in each photosensitive cell of the photosensitive section 1 are transferred for two rows, and the charges transferred to each memory cell of the storage section 3 are transferred for one row, and at this time, the intermediate By alternately performing the operation of reading out the charges transferred to the register 8, the charges (2, 2,
1) ~ (2,4), (4,1) ~ (4°4), (6,1
) to (6,4) and (8,1) to (8,4) are sequentially output as voltages. That is, the first field is read. On the other hand, during exposure, (1,1) to (1,4), (3,1) to (3°4), (5,1) to (s,4), (7,1) to (7, 4
) The charge 12 accumulated in the photosensitive cell shown in ), the storage part 3 (
1,1E~[,4:1. ['2.1] ~ (2,4), [
3,11) to [3,4:) and [4°1] to C4,4), and are stored therein. After reading out the first field in this way, a in Figure 4(a)
The mode shifts to the second field read mode indicated by -4. In this a-4, after the charges transferred to the storage cells of each row of the storage unit 3 are transferred for one row, the horizontal output register 5
By reading the charges transferred to the horizontal output register 5, (1, 1) to (1, 4), (a
, 1) ~ (3° 4), (5, 1) ~ (5, 4), (7,
The charges accumulated in the photosensitive cells 1) to (7, 4) are output as voltages, and the second field is read out.

As described above, according to the image sensor of this embodiment, two fields -
As a function to support frame recording in a one-frame still video system, one frame worth of image signals formed on the photosensitive section 1 at the same time can be recorded as a normal television.
As in the system, first, the first field signal,
Next, it becomes possible to read out the two fields separately, such as the signal of the second field interlaced therewith.

Next, the operation when the above image pickup device is applied to a normal movie/video camera will be explained.

b-1 in FIG. 4(b) corresponds to the mode a-1 in FIG. 4(a), that is, the all clear mode.

However, this mode is not essential.

When applied to a movie/video camera, /// is not necessary, and the operation is to repeatedly accumulate and read out charges. Both b-2 and b-2' indicate the accumulation mode, b-2Fi indicates accumulation in the first field, and b-2' indicates accumulation in the second field. b-3, b-3
' indicates read mode, the charge (first field) accumulated in b-2 is read out in b-3, and b-2
The charge (second field) accumulated at ' is read out at b-3'.

b-4, the charge generated and accumulated in the photosensitive section 1 is stored in the storage section 3.
Indicates the mode to be transferred to.

In the image sensor of this embodiment, for example, the number of photosensitive cells (number of rows) in the vertical direction of the photosensitive section 1 is about 490, and the number of memory cells in the same vertical direction of the storage section 3 is about 245, so it is different from the conventional image sensor.
The operation and interlacing method when transferring charges from the photosensitive section 1 to the storage section 3 are different from those of a bulk transfer type image sensor.

First, in the period shown by b-2 in FIG.
The accumulated charge of the photosensitive section 1 is stored in the storage section 3 during the period indicated by -4.
Transfer to. Regarding this transfer operation, first, the photosensitive section 1
The electric charge accumulated in each photosensitive cell is 1 in the photosensitive section 1.
Transfer line by line. That is, at this time, no pulse voltage is applied to the intermediate register 8 and the storage section 3, and therefore, (2, 1
), (2,2), (2,3), and (2°4), the accumulated charge of the photosensitive cell is (1,1).

The charges are transferred to the photosensitive cells indicated by (1,2), (1,3), and (1,4), and are added to the accumulated charges of the photosensitive cells indicated by these (1,1) to (1,4). After the completion, the operation of transferring the charges accumulated in the photosensitive section 1 in b-2' to the storage section 3 is executed in b-4. In this case, since it is a read operation for the second field, the row to be added is set to the first field.
Shifting one line from the case of the field, photosensitive area 1
The transfer and addition of two lines is performed.

That is, the second field first includes the photosensitive section 1.

A pulse voltage 7 (7) is applied to the intermediate register 8 and the storage section 3 to transfer the charges of each row of the photosensitive section 1 one row at a time.As a result, (1.1) to (1.4) during exposure, (2.
1)~(2.4),...

The accumulated charges of the photosensitive cell shown in (8.1) to (8.4) are:
Transfer cells (1) to (4) of the intermediate register 8 and (1.1) to (1.4) of the photosensitive section 1, respectively.

. . . will be transferred to the photosensitive cells shown in (7.1) to (7.4).

Next, a pulse voltage is applied only to the photosensitive section 1, and the charges of each row are transferred again only within the photosensitive section 1, one by one.As a result, (3.1) to (3.4)
(2.1) to (2
．． The accumulated charge of the photosensitive cell shown in 4) is (1.1) to (1.
4), where this (1.

It is added to the accumulated charge of the photosensitive cells shown in (2.1°) to (2.4) at the time of exposure, which has been transferred to the photosensitive cells shown in 1) to (1, 4), and is accumulated. . However, due to this, (4.1) to (4.4) during exposure,...
・, (3.1) to (3.4), which correspond to the accumulated charges of the photosensitive cell shown in (8.1) to (8.4),...
, (7.1) to (7.4) are respectively (2.1) to (2.4), (6.1)
) to ('6.4).

Next, when a pulse voltage is again applied to the photosensitive section 1, the intermediate register 8, and the storage section 3, the voltage of the photosensitive section 1 at the time of exposure is (1.1) ~
The accumulated charges of the intermediate register 8 corresponding to the accumulated charges of the photosensitive cell shown in (1.4) are (4.1) to (4,4) of the storage section 3.
), and the photosensitive area 1i ( 2
.

(1.1) corresponds to the sum of the accumulated charges of the photosensitive cell shown in 1) to (2.4) and (3.1) to (3.4).
The accumulated charge of the photosensitive cell shown by ~(1.4) is transferred to the intermediate register 8, and the accumulated charge of the photosensitive cell 1 shown by (4.1) ~ during exposure is transferred to the intermediate register 8.
(4.4).

. . . (2.1) to (2.4) correspond to the accumulated charges of the photosensitive cell shown in (8.1) to (8.4).

......, the accumulated charges of the photosensitive cell shown in (6.1) to (6.4) are (1.1) to (1.4), ....-
・.

It is then transferred to the photosensitive cells shown in (5.1) to (5.4).

Next, when the Norculus voltage is again applied only to the photosensitive section 1, within the photosensitive section 1, (5) at the time of exposure.

The accumulated charges in the photosensitive cell shown in (2.1) to (2.4), which correspond to the accumulated charges in the photosensitive cell shown in 1) to (5.4), are (
1. i) to the photosensitive cells shown in (1, 4), where the cells previously transferred were transferred.

The charge is added to the charge accumulated in the photosensitive cell shown in (4.1) to (4.4) during exposure, and is accumulated.

It's a trench, at this time, (6.1) to (6.4) at the time of exposure...
..., (3.1) to (, 3, 4.), which correspond to the accumulated charges of the photosensitive cell shown in (8.1) to (8.4).

..., the accumulated charges of the photosensitive cells shown by (s, 1) to (5.4) are (2.1) to (2.4), respectively.
・.

It is transferred to the photosensitive cells shown in (4.1) to (4.4).

Thereafter, by repeating the operation of applying a pulse voltage to the photosensitive section 1, the intermediate register 8, and the storage section 3, and the operation of applying a pulse voltage only to the photosensitive section 1, 2(n-1 ) line and 2. n-1'fi'th (n is 1
(natural numbers above) are accumulated in (1.1) to (1.1).
After being added in the photosensitive cell shown in 4), n of the storage section 3
It will be memorized in the row. That is, Cl,1 in the storage section 3
) to [1.4] of the photosensitive section 1 (1.1
) to (1.4), the charge of the photosensitive cell is [:2.1:
] to (2,4) have memory cells (2.1) to (2.
4) and (3.

The added charge of the photosensitive cell shown in 1) to (3.4) is [3.
The memory cells indicated by 1E to [3.4] have (4.1) to (4
．． 4) and (5.1) to (5.

The added charge of the photosensitive cell shown in 4) is then, [4°1]
The memory cell indicated by ~(4,4) has (6,1)~(6,4
) and (7,1) to (7,4)
．． Each charge is memorized. In addition, (s, i) ~ (
The charge of the photosensitive cell indicated by 8,4) comes to be stored in the intermediate register 8.

Thereafter, the mode shifts to b-2 and b-3, and the exposure and accumulation operations for the first field are performed, and the charges stored in the storage section 3 as described above are sequentially output horizontally by - rows. The signal is transferred to the register 5, horizontally transferred by the horizontal output register 5, and output from the amplifier 7 as voltage information. This causes the second field to be read.

As described above, the charges obtained in the photosensitive section 1 are added for two rows at a time using the photosensitive cells (1, 1) to (1, 4) in the last row. When transferring to
By relatively shifting the lines to be added between the field and the second field by one line, an effectively interlaced two-field signal can be obtained, thus making it possible to apply it to movie video systems. become. In this case, a similar effect in which the sensitivity of the image sensor is improved by several steps can be obtained. Further, the place where charges are added is set in the photosensitive section 1, and this photosensitive section 1
As explained in FIG. 2, an anti-pluming section consisting of an overflow drain gate OG and an overflow drain QD is provided for each predetermined column. - Even if a flow occurs, the overflow is absorbed by the anti-blooming section, and blooming can be prevented.

Next, an example of a driving circuit for driving the image sensor of the present embodiment described above will be described. In FIG.
Items with the same numbers as those in the figure have the same configuration. Reference numeral 100 indicates a drive circuit, and the drive circuit 100 is configured to drive the photosensitive portion 1 of the element 101, for example, when the number of horizontal pixels (number of photosensitive cells) is 785 and the number of vertical pixels (number of photosensitive cells) is 490. The pulse φPI applied to the polysilicon electrode 30° (FIG. 3) of section 1 is applied to the polysilicon electrode 31 (FIG. 3) of intermediate register 8 having, in addition to 785 bits, for example, 2 dummy bits. The applied pulse φS・, for example, 785 in the horizontal direction and 24 in the vertical direction
A pulse φps is applied to the polysilicon electrode 32 (FIG. 3) of the storage section 3, which is formed by arranging 5 storage cells.

and a pulse φS to be applied to the polysilicon electrode of the horizontal output register 5 having, for example, 2 dummy bits in addition to 785 bits.

Now, regarding the operation of the image sensor 101, there is a movie mode that supports moving images and in which a frame signal in which two fields are interlaced is obtained continuously, and a movie mode that supports still images and in which there is no time lag on the screen between two fields. Consider the stale mode to obtain a frame signal that intertonoses without any interference. In the movie mode, for example, assuming the NTSC system, it is necessary to obtain a field signal interlaced every 1/60 seconds to create a signal format similar to that of a normal television camera. on the other hand,
In the stale mode, it is necessary to use a two-field-one-frame signal format with no time lag on the screen between two fields interlaced by - times of exposure.

First, in the movie mode, clock pulses φPI and φ6 are applied from the drive circuit 100 to the image sensor 101.
1. The timing of φP8 and φS will be explained with reference to FIGS. 6, 7, and 8.

FIG. 6 shows the vertical timing, FIG. 7 shows details of the vertical timing, and FIG. 8 shows the horizontal timing.

First, the operation from the time when exposure for 1/60 second is completed, indicated by T1 in FIG. 6, will be explained. The drive circuit 100 first applies a pulse φPI of 2.0454 to the photosensitive section 1.
51 (489 clock pulses of llz are given to the intermediate register 8) pulse φsT and the pulse φps given to the storage unit 3 is 1.0227 which is half the frequency.
Outputs 245 pulses of 5 ilz. Also, the pulse φS given to the horizontal output register 5 is 14.318
Outputs a pulse of 18 ilz. As a result, charges for 245 rows added as a pair of the 2n-1st row and the 2nth row of the photosensitive section 1 are stored in the storage section 3, and at the same time, the charges in the horizontal output register 5 are cleared. By the way, the frequency of these transfer lock pulses is 2.045.
The reason why the distance is 451i11z and 1.02275 is to reduce the influence of smear since the photosensitive portion 1 is exposed to light even during this transfer, and the higher the frequency, the better. Note that the clock pulse φPI given to the photosensitive section 1
The reason why the frequency of the clock pulses φS and φps applied to the intermediate register 8 and the storage section 3 are twice different is that the intermediate register is 8 and the storage section 3 for one row transfer, the sum of charges for two rows of the photosensitive section 1 is transferred to the storage section 3.

Thereafter, during the horizontal blanking period three horizontal periods before the end of the vertical blanking period, the clock pulse φPs and the clock pulse φS are sent from the drive circuit 100 to the storage section 3 and the horizontal output register 5 as shown in FIG. is 1 each
The charges in the first row of the storage section 3 are transferred to the horizontal output register 5 by applying a pulse. Then, by applying 787 pulses of clock pulse φS of 14.31818 1 Glz from the drive circuit 100 to the horizontal output register 5, the first horizontal scanning line (the ninth line of the odd field in television 1/- (from the eyes) is read out.

Next, during the horizontal blanking period, a clock pulse φ is sent from the drive circuit 100 to the storage section 3 and the horizontal output register 5.
One pulse each of Ps and clock pulse φS is given,
The charges in the next row of storage section 3 are transferred to horizontal output register 5. After that, similarly, the drive circuit 10 is sent to the horizontal output register 5.
The second horizontal scanning line is read by applying 787 clock pulses φS of 0 to 14.31818 Mllz.

By repeating this operation 245 times, the field signal corresponding to the odd field is output from the horizontal output register 5 in less than 1/60 second.

On the other hand, while the field signal of the odd field is being read out from the storage section 3, the clock pulse φPr is not applied to the photosensitive section 1 from the drive circuit 100, so that the photosensitive section 1 receives the charge of the next even field. It has been accumulated. Next, at a time point indicated by T2 in FIG. 6, when 1/60 second has elapsed from the above T1, a clock pulse φPI is applied to the photosensitive section 1.
As a result, the clock pulse drive circuit 100 starts outputting 491 pulses of 2.045456 clock pulses to the storage section 3.
Charges for 245 lines are stored in the storage unit 3, which is the sum of the (n-1)th row and the 2n-1th row as a pair. By the way, in this case, the storage section 3 stores the 2 data from the photosensitive section 1.
The clock pulses φps and φS supplied from the drive circuit 100 to the storage unit 3 and the intermediate register 8 are The phase relationship is reversed when reading odd fields (see FIG. 7).

After that, after waiting for the end of vertical blanking, the drive circuit 100 transfers the charges of each row of the storage section 3 to the horizontal output register 5 sequentially in accordance with the horizontal period, and the drive circuit 100 outputs a clock signal of 14.31818 to the horizontal output register 5. - By supplying the pulse φS, through the horizontal output register 5,
It becomes possible to read field signals of even fields in the same manner as for odd fields.

Next, in the stay mode, each clock pulse φpr applied from the drive circuit 100 to the image sensor 101
, φS·, φps, and φS will be explained with reference to FIGS. 9 and 10. FIG. 9 shows the vertical timing, and FIG. 10 shows the horizontal timing.

First, when the photosensitive section 1 is exposed to an appropriate amount of light, which is controlled by an exposure control device (not shown), the photosensitive section 1 accumulates charges corresponding to the image obtained during the exposure.

Thereafter, at the time point indicated by T3 in FIG. 9, that is, during the horizontal blanking period three horizontal periods before the end of the vertical blanking period, first, the first row of the photosensitive section 1, the switching, and the television screen are displayed.・The charge of the 9th line is transferred to the intermediate register 8 at the rate.
In order to transfer the data to the photosensitive section 1. One pulse drive circuit 100 outputs clock pulses φPI, φS·, and φI'S to the intermediate register 8 and the storage section 3, respectively.

After that, in the horizontal period, 14.3 is stored in intermediate register 8.
1818 Mtlz clock pulse φsT is 787
By applying pulses from the drive circuit 100, the reading of the first line signal of the odd field is performed through the intermediate register 8. As described above, when the reading of one line is completed, the next horizontal block is read out. When entering the ranking period, the drive circuit 100 transfers the charges on the second row of the photosensitive section 1 to the storage section 3 and the charges on the third row of the photosensitive section l to the intermediate register 8. Clock pulse φp to 1 and intermediate register 8
■.

and φS' are applied with two pulses each, and one clock pulse φps is applied to the storage section 3.

Next, from the drive circuit 100 to the intermediate register 8, 14.31
When 787 pulses of the 81811 Hz clock pulse φS' are applied, the signal on the second line of the odd field is read out.

In such an operation, during the horizontal blanking period, the photosensitive section 1
The operation of transferring the charges in the odd-numbered rows to the intermediate register 8 and simultaneously transferring the charges in the even-numbered rows to the storage unit 3, and reading out the charges transferred to the intermediate register 8 in the following horizontal period is repeated. As a result, an odd field signal is obtained from the intermediate register 8, and charges corresponding to an even field are stored in the storage section 3. During this time, the drive circuit 100 is connected to the horizontal output register 5.
14.318181111z clock pulse φ
S continues to be applied, and charges are cleared.

After the reading of the odd field signal is completed, a time period shorter than a certain vertical blanking period by 3 horizontal scanning periods elapses, and the next reading of the even field signal begins at time T shown in FIG. However, this is performed by reading the charges from the horizontal output register 5 while transferring the charges from the storage section 3 to the horizontal output register 5. In other words,
During the horizontal blanking period, the data from the drive circuit 100 to the storage unit 3
One clock pulse φps and one clock pulse φS are applied to the horizontal output register 5 and the horizontal output register 5, and the charge for one row of the storage section 3 is transferred to the horizontal output register 5. During the following horizontal period, the drive circuit 100 is applied to the horizontal output register 5. From 14.31818 1
By repeating the operation of applying 787 clock pulses φS of 111z, an even field signal can be obtained through the horizontal output register 5.

In the still mode, while the even field is being read out, the photosensitive area l is able to accumulate charges corresponding to the next image, so during this period the time corresponding to the exposure time ( However, the time shorter than 1/60th of a second)
By opening the shutter, etc., it is possible to immediately read out the odd field of the next frame.

In other words, it is possible to continuously obtain 30 still frame images per second.

Next, the details of the drive circuit 100 described above will be explained in the eleventh section.
This will be explained with reference to the figures.

In Figure 11, 102 is 14.318181! flz
.

In other words, the oscillator 104 has an oscillation frequency four times that of the color subcarrier in the NTSC standard.
106 is a 1/7 frequency divider circuit that divides the output of 02 by 7 to generate a clock of 2°04545 Mllz, and 106 divides the output of 1/7 frequency divider 104 by 2 to generate a clock of 1.022751'Jl.
A 1/2 frequency divider circuit that generates a clock of z, 108 is a 1/2 frequency divider circuit that generates a clock of
a 1/130 frequency divider circuit that divides the output of the 7 frequency divider circuit 104 by 1/130 to generate a divided output for one horizontal period fH;
110 is the output of the 1/130 frequency divider circuit 108 to 11525
11 which divides the frequency and generates a divided output related to one vertical period fV.
525 frequency divider circuit, 112 is based on the output of the 1/130 frequency divider circuit 108, in addition to various pulses necessary for the horizontal scanning period, such as horizontal synchronization signal, horizontal blanking signal, equivalent pulse, burst flag, etc. A horizontal decoder 114 generates pulses necessary for a well-known signal processing circuit for television cameras, and a horizontal decoder 114 generates various pulses necessary for the vertical scanning period, such as a vertical synchronizing signal and a vertical block, based on the output of the 11525 frequency dividing circuit 110. In addition to ranking signals, well-known TV
A vertical decoder 116 generates pulses necessary for the signal processing circuit for the camera, and 116 generates pulses such as a composite synchronization signal and composite blanking signal corresponding to the television rate based on the outputs of the horizontal decoder 112 and the vertical decoder 114. A horizontal/vertical decoder 118 generates the outputs of the horizontal decoder 112 and the vertical decoder 114, the state of the switch 130 that commands movie mode or still mode, and a control circuit (not shown).

Based on the accumulation start command 0, etc., the clock pulse φ-1. Gate signals 01 to G4 and clock pulses φpr, for controlling φ8・, φPa + φS,
φS.

φps, decoder logic for generating φ8 original signals 81 to S4, 120, 122, 124° 126 U
1/7 frequency divider circuit 104. The clock signal from the 1/2 frequency divider circuit 106 and the decoder logic 118 is selectively inverted based on the gate signal from the decoder logic 118, and as necessary. A gate circuit for output, 128 is a 1/4 frequency divider circuit that divides the output of the oscillator 102 into 1/4 and generates color subcarriers SC1, 5C2 (two signals with a 90' phase shift). It is.

In such a configuration, the outputs of the horizontal decoder 112, vertical decoder 114, horizontal/vertical decoder 116, and 1/4 frequency divider circuit 128 are connected to a well-known video signal processing system, servo circuit system, recording gate, head switching control system, etc. and are used for their respective functions.

On the other hand, decoder logic 118 uses switch 130 to distinguish between movie mode and still mode.

First, in the movie mode, the television signal frequency is supplied from the gate circuits 120 to 126 in Figures 6 to 8.
Clock pulses ψPI, φS・, φP as shown in the figure
8, as φ8 is output, the lock signals 81 to S4 and the gate signals 01 to G4 are generated.

On the other hand, in the stay mode, lif? based on the accumulation command signal ■? Continuously or consecutively gate circuit 1
Clock pulses φPI, φsl, φps as shown in FIGS. 9 and 10 from 20 to 126.

As φS is output, lock signals S1 to S4 and gate signals 01 to G4 are generated. Incidentally, in the stay mode, a synchronizing signal (2) for shutter control is sent to a shutter control circuit (not shown).

Next, in the configuration of FIG. 11, the decoder logic 118
The operation will be explained in more detail by dividing it into movie mode and still mode. FIGS. 12 and 13 show the clock pulse φPI in movie mode and still mode, respectively.

φS・, φps, and φS are schematically shown.

First, the movie mode will be described with reference to FIG. 12. The decoder logic 118 decodes X for one frame of the television signal.

Y, Z, P, P', XV)6) (D operation mode)"t-
In the odd field, x, y, z, p, z.

The operation mode is switched in the order of P, .

. . . The operation mode is switched in the order of p and z. By the way, in Figure 12, 2M is 2.04545 k! fi
Clock pulse of z, 1M is 1.02275M) lz
IM is a clock pulse 180° out of phase with IM, 14M is 14.31818Mlt
z glue lock pulse, IP indicates 1 pulse, and 2P indicates 2 pulses.

5 clears charges.

Next, in Y mode, all clock pulses φPI
, φS・, φPa + φS enters the 3rd period when the vertical blanking period ends, and the clock
The charge of the 14Mth bar is transferred to the intermediate register 8 as a pulse φS. After that,
L motor attack (enter, clock pulse φS, close 14
M pulses are applied to the intermediate register 8, and the signal of the next line of the odd field is output. M mentioned above
The L mode and the L mode are repeatedly executed alternately, and the operation of the odd field is completed in the L' mode mode of 1/2 period.

In the next even field readout, the clock pulse φPI applied to the photosensitive section 1 is stopped, and as long as the shutter is open, images can be stored.

On the other hand, the clock pulse φsl is applied to the intermediate register 8.
A pulse of 14 M is applied continuously to clear the charges.

On the other hand, for storage unit 3, 12 clocks are input in Q mode.
The application of the pulse φps is cut off, and a 14M pulse is applied as the clock pulse φS to the horizontal output register 5, and the charges in the horizontal output register 5 are cleared. This operation is repeated until three horizontal periods before the end of the vertical blanking period.

In the next N mode, the clock pulse φ or 8. φS
One pulse is output in both cases, and the charges in the first row of the storage section 3 are transferred to the horizontal output register 5. After that, the clock pulse φS is applied only to the horizontal output register 5 in the L“ mode.
By applying 14M pulses as , the horizontal output register 5 outputs a scanning signal for one horizontal period. The N mode and the LrH mode are carried out alternately, and the reading of the even field image signal is completed after the Ll+ mode in which reading is performed for one last horizontal period.

Note that valid odd field signals are output from the intermediate register 8 only in L and L' modes.
During this period, or as shown in FIG. 13, L, M, L'
By passing the output of the intermediate register 8 only in each mode, the invalid signal from the intermediate register 8 can be cut. On the other hand, since valid even field signals are sent from the horizontal output register 5 only in the Lll mode, only during this period or in the N and L'' modes as shown in FIG. , the invalid signal from the horizontal output register 5 can be cut by passing the output of the horizontal output register 5. On the other hand, by mixing the gated outputs of the horizontal output register 5 and the intermediate register 8, It is possible to obtain an image signal for one frame.

Incidentally, in order to perform the above-mentioned operation, the gate circuits 120 to 126 are connected to the 2P, 'l from the divide-by-7 circuit 104.
pulse, IM pulse from the 1/2 frequency divider circuit 106,
The original signal S 1 =-84 including 14M pulses from the oscillator 102, the 1) pulse signal IP from the tecoder logic 118, and the 2-pulse signal 2P is controlled by gate signals 01 to G4 that set each mode. The output configuration is as follows. The logical configuration of each gate circuit 120-126 is shown in FIGS. 14-17, respectively.

32'; In the configurations shown in FIGS. 14 to 17, the one-pulse signal IP and the two-pulse signal 2P are output at the timings shown in FIGS. 6 to 101\1 for each mode. In addition, since FIGS. 14 to 17 only show the logical configurations, we will also discuss circuits that shape variations in the delay time of rising and falling clocks, such as synchronous output circuits and logical configurations for preventing the occurrence of glitches. Although not shown, the details are omitted here because it can be fully implemented within the well-known technical range.

(Effects) As detailed above, according to the present invention, as an image sensor for a video camera, especially a movie camera, that follows the 2-field-1-frame interlace method, the element sensitivity can be dramatically improved compared to the conventional one. However, its effectiveness as an image sensor for this type of camera is quite impressive.

[Brief explanation of drawings]

FIG. 1 is a diagram schematically showing the configuration of an embodiment of an image sensor according to the present invention, and FIG. 2 is a photosensitive section, a storage section, and a transfer and output section between them of the image sensor shown in FIG. 1. Figure 3 shows the internal potential state of the image sensor shown in Figure 1, and Figure 4 shows the image sensor shown in Figure 1. FIG. 5 is a diagram showing an outline of an imaging system including the imaging device and disturbance circuit shown in FIG. 1, FIGS. 6, 7, and 8. , Figures 9 and 10
The figures are a timing chart showing the output pulses of the drive circuit shown in Fig. 5, Fig. 11 is a diagram showing a specific configuration of an example of the drive circuit shown in Fig. 5, and Figs. 12 and 13 are Figures 14, 15, 16, and 17 schematically show how the control signals are generated, respectively.
FIG. 3 is a diagram showing a specific configuration of four gate circuits shown in the figure. 1...°photosensitive section, 2.2'...photosensitive cell (2' is a photosensitive cell with a relatively small signal capacity), 3...memory section, 4
...Storage cell, 5...Horizontal output register, 8.°.
Transfer and output section (intermediate register), OG, OD... Components of anti-pluming section (overflow and
drain gate and overflow drain). Agent Marushima Bo-O Takeshi 4th 22nd

Claims (6)

[Claims] (1) In an image sensor comprising a photosensitive section having a plurality of photosensitive cells arranged along rows and columns, and a storage section for storing signals from the photosensitive section, in the photosensitive section, The signal storage capacity of each photosensitive cell arranged along at least one row near the storage section is made smaller than that of each photosensitive cell arranged along other rows. image sensor. (2) The storage section is configured by arranging a plurality of storage cells in rows and columns, and in this case, the number of columns is equal to the number of columns in the array of photosensitive cells, and The image sensor according to claim 1, wherein the number of rows is approximately half the number of rows of the photosensitive cell array. (3) The image pickup device according to claim (2), wherein the signal storage capacity of each of the memory cells is approximately equal to the signal storage capacity of the photosensitive cell having a relatively small signal storage capacity. (4) Any of claims (1) to (3) in which the number of rows of the photosensitive cell array is approximately equal to the number of scanning lines constituting one television frame. The image sensor according to item 1. (5) The image pickup device according to any one of claims (1) to (4), wherein an anti-pluming portion is provided between predetermined columns of the photosensitive cell array. (6) Between the photosensitive section and the storage section, a line from the photosensitive section [
Any of claims (1) to (5), which is provided with a transfer and output unit for selectively transferring related signals to a storage unit and selectively outputting them to the outside. The image sensor according to item 1.