JPS5893324A - Semiconductive device - Google Patents
Semiconductive deviceInfo
- Publication number
- JPS5893324A JPS5893324A JP19253081A JP19253081A JPS5893324A JP S5893324 A JPS5893324 A JP S5893324A JP 19253081 A JP19253081 A JP 19253081A JP 19253081 A JP19253081 A JP 19253081A JP S5893324 A JPS5893324 A JP S5893324A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- oxide film
- contact window
- aluminum
- cvd oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000011521 glass Substances 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052782 aluminium Inorganic materials 0.000 abstract description 12
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 238000005260 corrosion Methods 0.000 abstract description 4
- 230000007797 corrosion Effects 0.000 abstract description 4
- 239000012535 impurity Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 239000005365 phosphate glass Substances 0.000 abstract 3
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置において、特に信頼性の向上に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to improving reliability in semiconductor devices.
半導体装置の一例として、電界効果トランジスタの一例
を第１図に示す。第１図は一主面側にソースおよびゲー
ト電極を設け、他主面側にドレイン電極を設けた、縦型
電界効果トランジスタが、Ｎ型半導体基板１内に、Ｐ型
層２．Ｎ生型層３．ゲート酸化膜４およびゲート電極５
を形成ｌ、ゲート電極５とソース電極９との絶縁のため
ＩＣＣＶＤ酸化膜６が形成される。その後信頼性向上の
ために、ＣＶＤ 酸化膜６上に！Ｊ７ガ’）スＣＰ８Ｇ
＞層がＰＯＣ／３拡散等により形成され、電極とのコン
・タクト窓８がフォトリソグラフィー技術にて形成され
る。従来の、アルミニウムソース電極９下にリンガラス
（ｐｓｏ）層７が形成された構造では、ＰＥＧ中のリン
が溶は出し、水分によるアルミニウム腐食を促進し、ア
ルミニウム電極が断線したり。As an example of a semiconductor device, an example of a field effect transistor is shown in FIG. In FIG. 1, a vertical field effect transistor is provided with a source and a gate electrode on one main surface and a drain electrode on the other main surface, and a P-type layer 2. N green mold layer 3. Gate oxide film 4 and gate electrode 5
An ICCVD oxide film 6 is formed to insulate gate electrode 5 and source electrode 9. Afterwards, to improve reliability, a CVD oxide film 6 was applied! J7ga')suCP8G
> layer is formed by POC/3 diffusion etc., and contact window 8 with the electrode is formed by photolithography technique. In the conventional structure in which the phosphorus glass (pso) layer 7 is formed under the aluminum source electrode 9, phosphorus in the PEG is leached out, promoting aluminum corrosion due to moisture, and causing the aluminum electrode to break.
誤動作することがらり九〇
本発明は、これらの欠点を除去するためＫなされたもの
である。The present invention has been made to eliminate these drawbacks.
本発明の特徴は、半導体装置において第１のＣＶＤ酸化
膜を形成した後、リンガラス層（Ｐ２Ｏ）を形成し、電
極との接続のためのコンタク）Ｉｌｌを形成後、第２の
ＣＶＤ酸化膜を形成し、電極との接続のためのコンタク
ト窓を再度形成したのち電極を形成した半導体装置にあ
る。すなわち、コンタクト窓を形成した後、不純物の＃
１とんど含まないＣＶＤ膜を形威し、再度コンタクト窓
を形成したのちアルミニウム電極を形成したもので、以
下図面について詳細に説明する。A feature of the present invention is that in a semiconductor device, after forming a first CVD oxide film, a phosphorus glass layer (P2O) is formed, and after forming a contact (Ill) for connection with an electrode, a second CVD oxide film is formed. A semiconductor device is provided in which electrodes are formed after forming contact windows for connection with electrodes. That is, after forming the contact window, # of impurities is
A CVD film that does not contain any of the above components is formed, a contact window is formed again, and an aluminum electrode is then formed.The drawings will be described in detail below.
第２図は本発明の実施例であり、１はＮ型基板。FIG. 2 shows an embodiment of the present invention, where 1 is an N-type substrate.
２はＮ型基板１内に形成されたＰ型拡散層を示す。2 indicates a P-type diffusion layer formed within the N-type substrate 1. As shown in FIG.
３はＰ型拡散層２内に形成されたＮ＋型型数散層４はゲ
ート酸化膜、５はゲート電極、６はＣＶＤ酸化膜、７は
リンガラス（Ｐ２Ｏ）層、８は電極とのコンタクト窓、
１１は以上形成後に不純物をほとんど含まないＣＶＤ酸
化膜を形成後、再度コンタクト窓８を空けＣＶＤ酸化膜
１１を形成した後。3 is an N+ type scattering layer 4 formed in the P type diffusion layer 2 is a gate oxide film, 5 is a gate electrode, 6 is a CVD oxide film, 7 is a phosphorus glass (P2O) layer, and 8 is a contact with the electrode. window,
11 is after forming a CVD oxide film containing almost no impurities after the above formation, and after forming the contact window 8 again and forming a CVD oxide film 11.
アルミソース電極９を形成したものである。１０は他主
面に形成され九ドレン電極１０である。An aluminum source electrode 9 is formed. Numeral 10 is a nine drain electrode 10 formed on the other main surface.
本構造によれば、従来のようにアルミソース電極とは離
れてＰ２Ｏ膜があるため、従来のようＫは、アルミ腐蝕
を促進しないため寿命の長い信頼性の高い製品が得られ
効果が大きい。According to this structure, since there is a P2O film apart from the aluminum source electrode as in the conventional case, K does not promote aluminum corrosion as in the conventional case, so a highly reliable product with a long life can be obtained, which is highly effective.
なお本発明は、実施例として電界効果トランジスタにつ
いて述べたが、勿論ＩＣｓＣｓバイポーラトランジスタ
も適用できる。Although the present invention has been described using a field effect transistor as an example, it is of course applicable to an ICsCs bipolar transistor.
第１図は従来の電界効果トランジスタの断面図。
第２図は本発明実施例による構造を各々示す。
なお図面において、ｌ・・・・・・Ｎ型半導体基板、２
・・・・・・Ｐ型領域、３・・・・・・Ｎ＋型領領域４
・・・・・・ゲート酸化膜、５・・・・・・ゲート電極
％ ６，１１・・・・・・ＣＶＤ酸化酸化膜子・・・・
・・リンガラス（Ｐ２Ｏ）層、８・・・・・・コンタク
ト窓％９・・・・・・アルｉニクムソース電極％ｌＯ・
・・・・・ドレイン電極、である。FIG. 1 is a cross-sectional view of a conventional field effect transistor. FIG. 2 shows structures according to embodiments of the present invention. In the drawings, l...N-type semiconductor substrate, 2
...P type region, 3...N+ type region 4
...Gate oxide film, 5...Gate electrode% 6,11...CVD oxide oxide film...
...Phosphorus glass (P2O) layer, 8...Contact window%9...Aluminum source electrode%lO.
...Drain electrode.
Claims (1)
成され、該第１のＣＶＤ酸化膜上にリンガラス層（ＰＥ
Ｇ）が形成されて、電極との接続のためのコンタクト窓
が形成され、さらに第２のＣＶＤ酸化膜が形成されて前
記電極との接続のためのコンタクト９９が再度形成され
たのちに電極が形成されていることを特徴とする半導体
装置。In a semiconductor device, a first CVD oxide film is formed on a substrate, and a phosphor glass layer (PE) is formed on the first CVD oxide film.
G) is formed to form a contact window for connection with the electrode, and a second CVD oxide film is formed to again form a contact 99 for connection to the electrode. A semiconductor device characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19253081A JPS5893324A (en) | 1981-11-30 | 1981-11-30 | Semiconductive device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19253081A JPS5893324A (en) | 1981-11-30 | 1981-11-30 | Semiconductive device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5893324A true JPS5893324A (en) | 1983-06-03 |
Family
ID=16292807
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19253081A Pending JPS5893324A (en) | 1981-11-30 | 1981-11-30 | Semiconductive device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5893324A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6276536A (en) * | 1985-09-27 | 1987-04-08 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| WO2016063630A1 (en) * | 2014-10-24 | 2016-04-28 | 住友電気工業株式会社 | Silicon carbide semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52104087A (en) * | 1976-02-27 | 1977-09-01 | Hitachi Ltd | Preparation of inter-layer insulation film utilized in multi-layer wir ing of electronic parts |
| JPS52131481A (en) * | 1976-04-28 | 1977-11-04 | Hitachi Ltd | Manufactuer fo semiconductor device |
| JPS5460558A (en) * | 1977-10-24 | 1979-05-16 | Hitachi Ltd | Electrode forming method |
-
1981
- 1981-11-30 JP JP19253081A patent/JPS5893324A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52104087A (en) * | 1976-02-27 | 1977-09-01 | Hitachi Ltd | Preparation of inter-layer insulation film utilized in multi-layer wir ing of electronic parts |
| JPS52131481A (en) * | 1976-04-28 | 1977-11-04 | Hitachi Ltd | Manufactuer fo semiconductor device |
| JPS5460558A (en) * | 1977-10-24 | 1979-05-16 | Hitachi Ltd | Electrode forming method |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6276536A (en) * | 1985-09-27 | 1987-04-08 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| WO2016063630A1 (en) * | 2014-10-24 | 2016-04-28 | 住友電気工業株式会社 | Silicon carbide semiconductor device |
| JP2016086064A (en) * | 2014-10-24 | 2016-05-19 | 住友電気工業株式会社 | Silicon carbide semiconductor device |
| CN106716609A (en) * | 2014-10-24 | 2017-05-24 | 住友电气工业株式会社 | Silicon carbide semiconductor device |
| US10014258B2 (en) | 2014-10-24 | 2018-07-03 | Sumitomo Electric Industries, Ltd. | Silicon carbide semiconductor device having gate electrode |
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