JPS5890748A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5890748A
JPS5890748A JP7694182A JP7694182A JPS5890748A JP S5890748 A JPS5890748 A JP S5890748A JP 7694182 A JP7694182 A JP 7694182A JP 7694182 A JP7694182 A JP 7694182A JP S5890748 A JPS5890748 A JP S5890748A
Authority
JP
Japan
Prior art keywords
brazing
brazing material
wall member
metal
stad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7694182A
Other languages
Japanese (ja)
Other versions
JPS6236391B2 (en
Inventor
Shinzo Anazawa
穴沢 信造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7694182A priority Critical patent/JPS5890748A/en
Publication of JPS5890748A publication Critical patent/JPS5890748A/en
Publication of JPS6236391B2 publication Critical patent/JPS6236391B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body

Abstract

PURPOSE:To obtain specified brazing strength without deterioration of electrical and mechanical characteristics by providing a metal which is easily wet by brazing material at the brazing area and by providing a means for repelling the brazing material to the brazing-free area. CONSTITUTION:On the occasion of coupling a stad 16 and an insulated wall member 17, for example, with the Silver-Copper eutectic braze 14, the surface of stad 16 is plated by the Ni 15, for example, which is easily wet by the braze 14, the Ni 15 is partly removed exposing the surface of stad 16 which repels the braze and a groove 21 or extrusion 22 is provided therein. Thereby, the fitting area of semiconductor element is not in contact with the brazing material at the wall member fitting area. Accordingly, corrosion of brazing material and deterioration of coupling by chemical reactions based on mixture of them can be prevented and the specified brazing strength can be acquired easily.

Description

【発明の詳細な説明】 本発明は半導体装置とくにろう何部を有する半導体装置
に係るものである0 小型電子回路装置、特に混成集積回路或いは高周波用半
導体装置の発展に伴い種々の絶縁材料が使用される様に
なった0周知の如く最近電子回路の小製化の強−と電気
的特性面からの要求から、使用される材料並びに物理的
な構造に大きな制約がかかり、要求される特性の全てを
満足せしめる為にはかなり困難な問題が存する◇その内
の重要な問題はろう付である。電子回路用基板又は容器
等の限られたmsに被ろう何体をろう付する際、所定の
ろう付強度を確保する為柘はその構成材料の特質、メタ
ライズ技術、ろう付技術の調和がとれていないといすな
いが、一方晶周波時性等の電気的な面からあるいは単な
るろう付技術の面からのみ考慮しただけではその解決と
はならないこきが多い。例えは第1図に示す如く絶縁基
板1の表面にメタライズ層2を施し、該層2に平型のり
−ド3をろう付する場合に、Jl!求されるろう付強度
を得る為にはメタライズ層の幅、リードの幅、ろう材4
の量を適宜に選択しなければならない。例えば絶縁基板
lとして、誘電率が低く且つ熱放散のよいべIJ リア
セラミックを採用し、所望の特性インピーダンスを保有
せしめる電子回路基板を製作する場合には、電気的特性
を優先せしめる必要からメタライズ層の機、リードの幅
に制版をうけ、所定のメタライズ強度、ろう付強度を得
る事が困J11な拳が多い。特に高周波領域に使用する
電子回路に於いてその影醤は顕著である。この解決の為
に今迄種々提案されている方法さして、第2図に示す如
く絶縁基板1の上に設けられたメタライズ層2に外部引
出リード3をろう材4でろう付する際に出来るたけろう
付部にろう材4が溜まる様にして歪の緩和を計るきか、
戚いは第3図に示す如く絶縁基板1の側面の一部にメタ
ライズ層!を設けてろう付の際のろう溜を生じせしめて
ろう付強度を増加せしめる方法かある。その他外部引出
リード3のろう何部分に孔を設けたり又は第4図に示す
如き形状にしてろう材4が溜り易くしたりする方法も提
案されている〇 しかしながら第2図の場合は実質的にろう材4が外部引
出リード3の他の部分に流れてし才うのでろう溜を歩留
よくつくる事は困難であり、又第3図の如き構成の場合
には絶縁基@1の側面メタライズ層2′と裏面メタライ
ズ2′の間の実質的静電容量を増加せしめて電気的特性
を損わしめる欠点がある。又外部引出リードの形状に工
夫をこらしても多少ろう溜歩留がよくなるたけで本質的
な解決は得られない。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device having a wax part. With the development of small electronic circuit devices, especially hybrid integrated circuits or high-frequency semiconductor devices, various insulating materials are being used. As is well known, the recent trend toward miniaturization of electronic circuits and demands for electrical properties have placed significant restrictions on the materials and physical structures used, and it has become difficult to achieve the required properties. There are quite difficult problems to be solved in order to satisfy all requirements. One of the most important problems is brazing. When brazing a soldering element that covers a limited space such as an electronic circuit board or a container, in order to ensure the specified brazing strength, it is necessary to balance the characteristics of the constituent materials, metallization technology, and brazing technology. However, in many cases, the problem cannot be solved simply by considering electrical aspects such as crystal frequency characteristics or simply from the aspect of brazing technology. For example, when a metallized layer 2 is applied to the surface of an insulating substrate 1 as shown in FIG. 1, and a flat glue 3 is brazed to the layer 2, Jl! In order to obtain the required brazing strength, the width of the metallized layer, the width of the lead, and the brazing material4
The amount must be selected accordingly. For example, when manufacturing an electronic circuit board that uses ceramic with a low dielectric constant and good heat dissipation as an insulating substrate and has a desired characteristic impedance, it is necessary to give priority to electrical characteristics, so a metallized layer is There are many J11 fists that are difficult to obtain the specified metallization strength and brazing strength due to the plate width of the lead. This effect is particularly noticeable in electronic circuits used in high frequency ranges. To solve this problem, various methods have been proposed up to now.As shown in FIG. Is it possible to alleviate the strain by allowing the brazing filler metal 4 to accumulate in the brazed part?
As shown in Figure 3, there is a metallized layer on a part of the side surface of the insulating substrate 1! There is a method of increasing brazing strength by creating a brazing pool during brazing. Other methods have also been proposed, such as providing a hole in the brazing part of the external lead 3 or creating a shape as shown in FIG. 4 to make it easier for the brazing material 4 to accumulate. However, in the case of FIG. Since the brazing filler metal 4 flows to other parts of the external lead 3, it is difficult to make a solder reservoir with a good yield, and in the case of the structure shown in FIG. It has the disadvantage of increasing the substantial capacitance between the layer 2' and the backside metallization 2', impairing the electrical properties. Also, even if the shape of the external lead is modified, the wax yield may be slightly improved, but no essential solution will be obtained.

一方電子回路の組立面から考えた場合に、ろう材が流出
して電子回路素子をマウントする所又は金属細線等でボ
ンディングする所に樵々のトラブル例えばマウント又は
ボンディングが不可能であるとか或いはマウントが出来
ても熱抵抗を増大せしめるとか、接続浮遊容量を増すと
か又はボンディングが出来てもボンディング強度が弱い
とか、長期の時分試験でボンデインク強度が洛ちてくる
等の欠点がある0とくに半導体素子を気密刺入す□  
る際使用される壁部材のろう付構造としては有効な手段
が提案されていなかった。
On the other hand, when considering the assembly of electronic circuits, lumberjacks may experience problems such as failure to mount or bond the electronic circuit elements due to leakage and mounting or bonding with thin metal wires, etc. Even if bonding is possible, there are disadvantages such as increasing thermal resistance, increasing connection stray capacitance, or even if bonding is possible, bonding strength is weak, and bonding ink strength decreases in long-term time tests. Especially for semiconductors. Insert the element airtight□
No effective method has been proposed for the brazing structure of wall members used in this process.

本発明の目的は、とくに壁部材のろう付構造においてそ
の他の電気的、機械的特性を劣化させることなく、所定
のろう付強度を容易に確保することができる新規な半導
体装置を提供することにある0 本発明は、壁部材および半導体素子を金属体上に取り付
けた半導体装置において、前記半導体素子板付は面と前
記壁部材取り付は面とに対向する部分の前記金属体上に
ろう材にぬれやすい金属部材を設け、前記半導体素子取
付は部と前記壁部材取付は部との間に前記壁部材取付は
用ロウ材をはじく手段を設けたことを特徴とする〇 本発明はこの樟にろう付部にはろう材が濡れ易い(なじ
み易い)金属部材を設け、ろう材の流出してはならない
部分にその境界を定めるべくろう材をはじく手段を設け
ているので、素子取付は用ろう材と壁部材取付は用ろう
材とが接触することがなく、内置の混合による化学的反
応に基づくろう材の腐食や、マウント性の劣化等を防止
できるOSえばろう材をはじく手段としてろう材にぬれ
にくい全極表面(とくにこれを金属体表面を使う)を露
出させるべく、みぞを作ったりダムを作ったりすればよ
い。この結果、ろう何場所にのみろう溜が容易に出来る
と同時に、従来の技術に於いて生ずるろう材の流出に基
づく前記の如き穫々の障害を防止するものである。
An object of the present invention is to provide a novel semiconductor device that can easily secure a predetermined brazing strength without deteriorating other electrical and mechanical properties, especially in the brazing structure of a wall member. 0 The present invention provides a semiconductor device in which a wall member and a semiconductor element are mounted on a metal body, in which a brazing material is applied to a portion of the metal body that faces a surface on which the semiconductor element plate is attached and a surface on which the wall member is attached. A metal member that is easily wetted is provided, and a means for repelling the brazing material used for the wall member mounting is provided between the semiconductor element mounting portion and the wall member mounting portion. The brazing part is equipped with a metal member that the brazing material easily wets (easily adapts to), and a means for repelling the brazing material is provided to define the boundary of the area where the brazing material should not flow out, so it is not necessary to attach the element. There is no contact between the brazing material and the wall material used, and corrosion of the brazing material due to chemical reactions caused by internal mixing and deterioration of mounting properties can be prevented. All you have to do is make a groove or a dam to expose the entire surface that is difficult to get wet (especially if you use a metal surface). As a result, it is possible to easily form a wax sump only in the soldering area, and at the same time, it is possible to prevent the above-mentioned problems due to the leakage of the soldering material that occurs in the conventional technique.

また換言すれば、本発明は、ろう材はろう材はじき手段
によってその拡散が防止されるとともにろう材はじき手
段によってむしろろう付されるべき場所へとはじかれる
ので、非常に有効なろう付ができる。
In other words, in the present invention, the brazing material is prevented from spreading by the brazing material repelling means and is rather repelled to the place where it should be brazed by the brazing material repelling means, so that very effective brazing can be achieved. .

次−こ本発明の主旨を更に具体的に明白にする為6ζ実
施例に基き第5図および第6図を参照しながら説明する
Next, in order to clarify the gist of the present invention more specifically, a description will be given based on a 6ζ embodiment with reference to FIGS. 5 and 6.

第5図は本発明の一実施例における断面図である0 この例では、スタッド(放熱体)16(例えば銅)に通
常の積層セラミック技術に着いた絶縁壁部材17(例え
ばアルミナ)(該絶縁部材17には容器の電極となるべ
きメタライズ層謁及び前記スタッド16にろう付する為
のメタライズ層lFIが設けられている)を取付け、か
つ壁部材には外部引出リード13をろう付して容器を形
成し、蚊容器の内部に半導体素子19(例え−jf )
ランジスタ)をマウントし金属細線(例えば金線)−鐘
、加′によって前記半導体素子19の電量と該半導体容
器とを電気的に接続してなる半導体装置例えばPETに
於いて、スタッド16と絶縁壁部材17とをろう材14
(例えば銀銅共晶ろう)でろう付の際に、スタッド16
の表面にろう材14が濡れ易い金属層15 (例えばN
i)をメッキ等で施した彼に、販金属層15の一部を除
去してろう材の濡れにくい金槁層を露出せしめ、即ち例
えば切削等により#121を設けたり、或いは第6図に
示す如くスタッド16に突出部22を設ける。これらの
溝21又は突出部ηをろう材にぬれζこくいスタッドで
形成すれば、半導体素子のマウント部及び金属#1線の
ボンディング部は壁部材のろう材からは完全にし中へい
される。
FIG. 5 is a cross-sectional view of one embodiment of the present invention. In this example, an insulating wall member 17 (e.g. alumina) (e.g. alumina) applied to a stud (heat spreader) 16 (e.g. copper) using conventional multilayer ceramic technology The member 17 is provided with a metallized layer to serve as an electrode of the container and a metallized layer IFI to be brazed to the stud 16, and an external lead 13 is brazed to the wall member to form the container. A semiconductor element 19 (e.g. -jf) is formed inside the mosquito container.
In a semiconductor device, for example, PET, in which a thin metal wire (e.g., gold wire) is mounted and the capacitance of the semiconductor element 19 is electrically connected to the semiconductor container by means of a thin metal wire (e.g., gold wire), the stud 16 and the insulating wall are connected. The member 17 and the brazing material 14
(for example, silver-copper eutectic solder), when brazing the stud 16
A metal layer 15 (for example, N
After applying i) by plating or the like, a part of the solder metal layer 15 is removed to expose the metal layer that is difficult to wet with the brazing material, that is, for example, by cutting etc., #121 is provided, or as shown in FIG. As shown, a protrusion 22 is provided on the stud 16. If these grooves 21 or protrusions η are formed with thick studs wetted with the brazing material, the mounting portion of the semiconductor element and the bonding portion of the metal #1 wire are completely hidden from the brazing material of the wall member.

尚ろう材の流れ防止の為にろう流れ防止剤の款布とか、
或いは硝子とかば化層を部分的に設ける等の方法も考え
られるが、ろう流れ防止剤の塗布、除去に高度の技術か
要求されるし、又硝子とか酸化層の設置は酸化雰囲気還
元雰囲気のサイクルによる材質劣化を惹起し、且つ該層
の設置、除去等に高度の技術が要求される事、及び両技
術共に着しい工数がかかる等の理由により望ましい方法
とは言えない。
In addition, to prevent the wax from flowing, apply a wax flow prevention agent, etc.
Alternatively, a method such as partially forming a glass and fogging layer can be considered, but it requires advanced technology to apply and remove the wax flow preventive agent, and installing a glass or oxidized layer requires an oxidizing atmosphere or a reducing atmosphere. This is not a desirable method because it causes material deterioration due to cycles, requires advanced technology for the installation and removal of the layer, and requires a considerable number of man-hours for both techniques.

Iた、第5図において例えろう材14かみそ内に入り込
んでも、入り込んだろう材ははじき出されるので、これ
が悪影響をおよぼすことはない0その上、みぞ周辺でろ
う材は金属層14@に収縮するようにtiするため、接
続強度を著しく向上させることができる。この効果は、
第6図の突出部にもいえることであり、ここではろう材
がはい上がりを全くみせないため、突出部上へのボンデ
ィングを良好にできる0ざらにボンディング線が突出部
の分だけ短かくてよいので、高周波特性に迄影曽をおよ
ぼすインダクタンスを大きく低減できる。
In addition, in Fig. 5, even if the filler metal 14 gets into the groove, the filler metal that has entered will be thrown out, so this will not have any adverse effects.In addition, the filler metal will shrink to the metal layer 14 around the groove. Therefore, the connection strength can be significantly improved. This effect is
The same can be said for the protrusion in Figure 6, where the brazing material does not creep up at all, making bonding on the protrusion better. Therefore, it is possible to greatly reduce the inductance that affects the high frequency characteristics.

以上本発明はその良好な実施例について説明されたが、
それは単なる例示的なものであって制限的意味を有する
ものでr7いことは勿論である。従って本発明の精神及
び範囲から逸脱することなしに本発明は種々の変更を加
えて実施し得るが、それらはすべて前記した本願特許請
求の範囲内に包含されるものである。
Although the present invention has been described above with respect to its preferred embodiments,
Of course, this is merely an example and does not have a restrictive meaning. Accordingly, the present invention may be practiced with various modifications without departing from the spirit and scope of the invention, but all such modifications are included within the scope of the claims hereinbefore set forth.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はろう付技術に於ける基本因、第2〜第4図は従
来のろう付技術を説明する為の図、第5図および#!6
図は本発明の実施例による半導体装置の断面図である。 1・・・・・・絶縁基板、2.12・・・・・・メタラ
イズ層、3.13・・・・・・外部引出リード、4.1
4・・・・・・ろう材、5.15・・・・・・ろう材が
濡れ鳥い金属層、16・・・・・・スタッド、17・・
・・・・絶縁壁部材、  18・・・・・・メタライズ
層、  19・・・・・・半導体素子、 加・・・・・
・金属細線、21・・・・・・溝、 η・・・・・・突
出部早1 目        第2 日・ 第5m 第、5 図 第 6 口 手続補正書(方側 57.12.29 特許庁長官 殿 1、事件の表示   昭和57年  特許願第7694
1号2、発明の名称   半導体装置 3、補正をする者 事件との関係       出 願 人東京都港区芝五
丁目33番1号 4、代理人 〒108  東京都港区芝五丁目37番8号 住人三田
ビル6 補正の対象 図面 7 補正の内容 特願昭49−100939号に関し、昭和57年5月7
日付で分割出願を2件(41願@57−76941号。 特願昭57−76942号)提出致しまし九が、事務上
の錯誤により図面を差し違えて添付してしまいまし几。 本補正書にて正しい図面を添付致しますので、再度ご精
査の程、お願い申し上げます。 −〕・ ニー 蕗l 目       第 25 $3 目        ¥4餡
Figure 1 shows the basic factors in brazing technology, Figures 2 to 4 are diagrams for explaining conventional brazing technology, Figure 5 and #! 6
The figure is a sectional view of a semiconductor device according to an embodiment of the present invention. 1... Insulating substrate, 2.12... Metallized layer, 3.13... External lead, 4.1
4...brazing metal, 5.15...metal layer with wet brazing metal, 16...stud, 17...
... Insulating wall member, 18 ... Metallized layer, 19 ... Semiconductor element, Addition ...
・Thin metal wire, 21...Groove, η...Protrusion 1st day 2nd day 5mth 5th figure 6 Oral procedure amendment (side 57.12.29 Patent Director-General of the Agency 1, Indication of the case 1981 Patent Application No. 7694
No. 1, No. 2, Title of the invention: Semiconductor device 3, Relationship to the amended person case Applicant: 5-33-1-4, Shiba 5-chome, Minato-ku, Tokyo, Agent: 5-37-8 Shiba, Minato-ku, Tokyo 108 Resident Mita Building 6 Drawing subject to amendment 7 Contents of amendment Regarding patent application No. 100939/1982, May 7, 1982
I have submitted two divisional applications (Application No. 41 @ No. 57-76941; Japanese Patent Application No. 57-76942) on the same date, but due to a clerical error, I attached the wrong drawings. We have attached the correct drawings in this amendment, so please review them again. -〕・ Knee butterfly 25th $3rd ¥4 bean paste

Claims (1)

【特許請求の範囲】[Claims] 金属体上に半導体素子とこれを気密Iこ封入する壁部材
とをろう付した半導体装置において、前記壁部材および
半導体素子をろう付する部分の前記金属体表面にはろう
材にぬれやすい金属部材が設けられ、前記半導体素子と
壁部材との間には壁部材を取り付けるろう材を壁部材側
へはじく手段が設けられていることを%黴とする半導体
装置0
In a semiconductor device in which a semiconductor element and a wall member that hermetically encapsulates the semiconductor element are brazed onto a metal body, a metal member that is easily wetted by the brazing material is provided on the surface of the metal body in a portion where the wall member and the semiconductor element are brazed. 0, and a means for repelling a brazing material for attaching the wall member toward the wall member is provided between the semiconductor element and the wall member.
JP7694182A 1982-05-07 1982-05-07 Semiconductor device Granted JPS5890748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7694182A JPS5890748A (en) 1982-05-07 1982-05-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7694182A JPS5890748A (en) 1982-05-07 1982-05-07 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP49100939A Division JPS5819385B2 (en) 1974-09-04 1974-09-04 Rouzukehouhou

Publications (2)

Publication Number Publication Date
JPS5890748A true JPS5890748A (en) 1983-05-30
JPS6236391B2 JPS6236391B2 (en) 1987-08-06

Family

ID=13619764

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7694182A Granted JPS5890748A (en) 1982-05-07 1982-05-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5890748A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61107751A (en) * 1984-10-30 1986-05-26 Nec Kansai Ltd Resin mold type semiconductor device
US4618879A (en) * 1983-04-20 1986-10-21 Fujitsu Limited Semiconductor device having adjacent bonding wires extending at different angles

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5128555A (en) * 1974-09-04 1976-03-10 Nippon Electric Co

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5128555A (en) * 1974-09-04 1976-03-10 Nippon Electric Co

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4618879A (en) * 1983-04-20 1986-10-21 Fujitsu Limited Semiconductor device having adjacent bonding wires extending at different angles
JPS61107751A (en) * 1984-10-30 1986-05-26 Nec Kansai Ltd Resin mold type semiconductor device

Also Published As

Publication number Publication date
JPS6236391B2 (en) 1987-08-06

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