JPS5885557A - Hybrid thick film integrated circuit - Google Patents
Hybrid thick film integrated circuitInfo
- Publication number
- JPS5885557A JPS5885557A JP56183812A JP18381281A JPS5885557A JP S5885557 A JPS5885557 A JP S5885557A JP 56183812 A JP56183812 A JP 56183812A JP 18381281 A JP18381281 A JP 18381281A JP S5885557 A JPS5885557 A JP S5885557A
- Authority
- JP
- Japan
- Prior art keywords
- thick film
- soldering
- measuring
- integrated circuit
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は混成厚膜集積回路の絶縁性樹脂コーI5ドパタ
ーンに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulating resin code I5 code pattern for a hybrid thick film integrated circuit.
混成集積回路は最近、特圧小型化、高密度実。Hybrid integrated circuits have recently become extremely compact, high-density, and practical.
装の傾向にあり、厚膜基板に塔載する電気部品の数も非
常に多くなってきている。このため、半田付のパッド間
の間隔が狭くなり1半田付の際に半田ブリッヂが生じ半
田付によるシホート″不良が問題となっている。The number of electrical components mounted on thick film substrates is also increasing. For this reason, the spacing between the soldering pads becomes narrower, and a solder bridge occurs during one soldering process, causing a problem of "shout" defects due to soldering.
第1図(al % fbl 、第2図(al、(bl従
来技術を示し゛、第1図(atは厚膜回路基板の要部平
面図、第1図゛fblは第1図fatのA−A’断面図
であり、第2図(a+’は第1図(alの厚膜回路基板
に電気部品を塔載し、半田付した場合の混成集積回路の
部品組立図で゛あす、第2(b)は第2図[alのB−
B’断面図を示し・たものである。Figure 1 (al % fbl, Figure 2 (al, (bl) shows the prior art, Figure 1 (at is a plan view of main parts of a thick film circuit board, Figure 1 fbl is A of Figure 1 fat) -A' is a sectional view, and Figure 2 (a+' is a component assembly diagram of a hybrid integrated circuit in which electrical components are mounted on a thick film circuit board made of aluminum and soldered). 2(b) is B- in Fig. 2 [al.
This is a cross-sectional view taken along B'.
第1図(alに示す厚膜回路は、セラミック基板01上
に、導体2から構成される導体を印刷焼成。The thick film circuit shown in FIG. 1 (al) is made by printing and firing a conductor consisting of a conductor 2 on a ceramic substrate 01.
して形成した後、抵抗体3を印刷焼成して形成。After that, the resistor 3 is printed and fired.
し必要に応じて抵抗体乙のトリミング後、絶縁性樹脂コ
ート4を印刷加熱硬化して形成する。After trimming the resistor B if necessary, the insulating resin coat 4 is printed and cured by heating.
第1図(atに示す厚膜回路基板にトランジスタ51−
。The transistor 51- is mounted on the thick film circuit board shown in FIG.
.
コンデンサ6等の電気部品暑塔載して半田付して混成集
積回路を形成する際に、電気部品用接続パッド7a〜7
eと素子測定用バンド80間隔が狭いため、半田付工程
で第2図falの電気部品接続用パッド7bと素子測定
用パッド8の間でハンダブリッヂ部10が生じ、半田付
ショー゛トの不良が発生していた。When forming a hybrid integrated circuit by mounting and soldering electrical components such as a capacitor 6, the electrical component connection pads 7a to 7
Because the distance between e and the device measurement band 80 is narrow, a solder bridge portion 10 occurs between the electrical component connection pad 7b and the device measurement pad 8 shown in FIG. was occurring.
本発明の目的は、上記した従来技術の欠点をなく丁ため
、厚膜回路基板において半田付時に。The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art when soldering thick film circuit boards.
おける半田ブリッヂを軽減させ、混成集積回路−・の組
立作業性の向上を図るものである。The present invention aims to reduce the number of solder bridges in the circuit and improve the ease of assembly of hybrid integrated circuits.
本発明は、上記目的を実現するため、厚膜回路基板にお
ける複数個の電気部品接続用パッドと素子測定用バッド
の中で、半田付と無関係の素子測定用バッドのみを絶縁
性樹脂コートで覆1)い、半田耐着箇所を減らすもので
ある。In order to achieve the above object, the present invention covers only the device measurement pads unrelated to soldering among the plurality of electrical component connection pads and device measurement pads on a thick film circuit board with an insulating resin coat. 1) It reduces the number of places where solder adheres.
第6図は本発明の一実施例の厚膜回路基板であり、第4
図(」は第6図の厚膜回路基板に電気部品を塔載し半田
付を行なった混成集積回路の要部組立平面図である。第
4(b)は第4(a)のC−Cl断面図である。FIG. 6 shows a thick film circuit board according to an embodiment of the present invention;
4(b) is an assembly plan view of the main parts of a hybrid integrated circuit in which electrical components are mounted and soldered on the thick film circuit board of FIG. 6. It is a Cl cross-sectional view.
第6図の厚膜回路基板は、アルミナ基板上に導体ペース
トv印刷焼成して配線導体2からなる導体を形成した後
、抵抗ペーストを印刷、焼成して抵抗体3を形成して厚
膜基板を得て必要に応じて抵抗体3の抵抗値を精度良ク
トリミングを行なってから、次に熱硬化性樹脂ペースト
を印刷、加熱硬化して完成する。第3図において部品接
続用パッド7と素子測定用パッド8の゛うち、素子測定
用パッド8は上記したトリミンー゛グ工程を経た後は必
要でないばかりでなく、半・口付工程においてショート
する危険を有するものである。そこで第6図に示す様に
素子測定用・パッド8を絶縁性の樹脂により覆い露出さ
せな・い様にし、半田レジスト機能をもたせる。 1
()この様にすると、半田伺の際に半田(fi(4着部
品が減υ、半田ブリッジによるショート不良が軽。The thick film circuit board shown in Fig. 6 is made by printing and firing a conductor paste v on an alumina substrate to form a conductor consisting of a wiring conductor 2, and then printing and firing a resistor paste to form a resistor 3. Then, the resistance value of the resistor 3 is precisely trimmed as required, and then a thermosetting resin paste is printed and heated to harden to complete the process. In Fig. 3, among the component connection pads 7 and the element measurement pads 8, the element measurement pads 8 are not only unnecessary after the above-mentioned trimming process, but also have the risk of shorting during the half-fitting process. It has the following. Therefore, as shown in FIG. 6, the element measurement pad 8 is covered with an insulating resin so as not to be exposed, thereby providing a solder resist function. 1
() By doing this, when soldering, the number of solder (fi) parts will be reduced, and short-circuit defects caused by solder bridges will be reduced.
減される。reduced.
本発明を適用することにより、高密度実装の混成集積回
路の半田付時における半田ブリッヂ等によるショート不
良を軽減することができ、。By applying the present invention, it is possible to reduce short-circuit defects caused by solder bridges and the like during soldering of high-density mounted hybrid integrated circuits.
半田付の作業性乞著しく向上するという効果を奏する。This has the effect of significantly improving soldering workability.
第1図は従来の厚膜回路基板の要部図面、第2図は従来
の厚膜回路基板に電気部品を塔載した場合の図面、第6
図は本発明による厚膜回路基板の要部平面部、第4図は
本発明による厚膜回路基板に電気部品を塔載した図面で
ある。
4・・・絶縁性樹脂コート
7・・・福、気部品接続用パッド
8・・・素子測定用パッド
9・・・電気部品接続用パッドの〕・ンダ伺部10・・
・ハンダブリッヂ部
代理人弁理士 薄 1)利 幸 =u
4 ・
オ 2 圀
(α) 5
.5 ・7び ・
ぢ 2≦ a−g□□7′
/////
/// ≦7 、////
B // / /′/
BL :
ビ 7,7 0 a 1/////////
////
/// / /
!
才 2 図
汁ろ菌
vFigure 1 is a diagram of the main parts of a conventional thick film circuit board, Figure 2 is a diagram of a conventional thick film circuit board with electrical components mounted on it, and Figure 6 is a diagram of the main parts of a conventional thick film circuit board.
The figure is a plan view of the main part of the thick film circuit board according to the present invention, and FIG. 4 is a drawing showing electrical components mounted on the thick film circuit board according to the present invention. 4... Insulating resin coat 7... Pad for electrical component connection 8... Pad for element measurement 9... Pad for electrical component connection]/Inner contact portion 10...
- Susuki, Patent Attorney, Handa Bridge Department 1) Toshiyuki = u 4 ・ O 2 Kuni (α) 5. 5 ・7bi ・ ぢ 2≦ a−g□□7′ //////// ≦7 、//// B // / /′/
BL:
Bi 7,7 0 a 1/////////
/////////! Sai 2 illustration soup filtration bacterium v
Claims (1)
焼成して形成した後、抵抗のトリミングを行ない、絶縁
性樹脂コートを硬化形成した゛厚膜基板上に電気部品を
半田付してなる混成集積回路において、前記電気部品の
回路接続のための接続用パッドと抵抗値等、測定のため
の素子測定用バッドを複数個有し、前記抵()抗体のト
リミング終了後、前記絶縁性樹脂コ。 −トで該素子測定用パッドを覆うことを特徴とする混成
厚膜集積回路。[Claims] 1. Conductor wiring and resistors are printed and fired on a ceramic substrate, the resistors are trimmed, and an insulating resin coat is hardened and formed.Electrical components are formed on a thick film substrate. In the hybrid integrated circuit formed by soldering, there are a plurality of connection pads for circuit connection of the electrical components and a plurality of element measurement pads for measuring resistance values, etc., and the trimming of the resistor is completed. After that, the insulating resin. - A hybrid thick film integrated circuit characterized in that the element measuring pad is covered with a pad.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56183812A JPS5885557A (en) | 1981-11-18 | 1981-11-18 | Hybrid thick film integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56183812A JPS5885557A (en) | 1981-11-18 | 1981-11-18 | Hybrid thick film integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5885557A true JPS5885557A (en) | 1983-05-21 |
Family
ID=16142298
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56183812A Pending JPS5885557A (en) | 1981-11-18 | 1981-11-18 | Hybrid thick film integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5885557A (en) |
-
1981
- 1981-11-18 JP JP56183812A patent/JPS5885557A/en active Pending
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