JPS5882560A - Ｃｍｏｓ集積回路 - Google Patents
Ｃｍｏｓ集積回路Info
- Publication number
- JPS5882560A JPS5882560A JP56179653A JP17965381A JPS5882560A JP S5882560 A JPS5882560 A JP S5882560A JP 56179653 A JP56179653 A JP 56179653A JP 17965381 A JP17965381 A JP 17965381A JP S5882560 A JPS5882560 A JP S5882560A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- potential level
- internal circuit
- control element
- power source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
- H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56179653A JPS5882560A (ja) | 1981-11-11 | 1981-11-11 | Ｃｍｏｓ集積回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56179653A JPS5882560A (ja) | 1981-11-11 | 1981-11-11 | Ｃｍｏｓ集積回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5882560A true JPS5882560A (ja) | 1983-05-18 |
| JPH0118587B2 JPH0118587B2 (enrdf_load_stackoverflow) | 1989-04-06 |
Family
ID=16069531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56179653A Granted JPS5882560A (ja) | 1981-11-11 | 1981-11-11 | Ｃｍｏｓ集積回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5882560A (enrdf_load_stackoverflow) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4571505A (en) * | 1983-11-16 | 1986-02-18 | Inmos Corporation | Method and apparatus of reducing latch-up susceptibility in CMOS integrated circuits |
| US4837460A (en) * | 1983-02-21 | 1989-06-06 | Kabushiki Kaisha Toshiba | Complementary MOS circuit having decreased parasitic capacitance |
| JPH01220470A (ja) * | 1988-02-29 | 1989-09-04 | Fujitsu Ltd | 相補型半導体集積回路装置 |
| JP2014027279A (ja) * | 2012-07-27 | 2014-02-06 | Freescale Semiconductor Inc | 半導体デバイスのためのシングルイベントラッチアップ防止技法 |
-
1981
- 1981-11-11 JP JP56179653A patent/JPS5882560A/ja active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4837460A (en) * | 1983-02-21 | 1989-06-06 | Kabushiki Kaisha Toshiba | Complementary MOS circuit having decreased parasitic capacitance |
| US4571505A (en) * | 1983-11-16 | 1986-02-18 | Inmos Corporation | Method and apparatus of reducing latch-up susceptibility in CMOS integrated circuits |
| JPH01220470A (ja) * | 1988-02-29 | 1989-09-04 | Fujitsu Ltd | 相補型半導体集積回路装置 |
| JP2014027279A (ja) * | 2012-07-27 | 2014-02-06 | Freescale Semiconductor Inc | 半導体デバイスのためのシングルイベントラッチアップ防止技法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0118587B2 (enrdf_load_stackoverflow) | 1989-04-06 |
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