JPS5866769U - Muting circuit - Google Patents

Muting circuit

Info

Publication number
JPS5866769U
JPS5866769U JP1981159894U JP15989481U JPS5866769U JP S5866769 U JPS5866769 U JP S5866769U JP 1981159894 U JP1981159894 U JP 1981159894U JP 15989481 U JP15989481 U JP 15989481U JP S5866769 U JPS5866769 U JP S5866769U
Authority
JP
Japan
Prior art keywords
signal
circuit
muting
muting circuit
horizontal synchronizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1981159894U
Other languages
Japanese (ja)
Other versions
JPH0212770Y2 (en
Inventor
隆 角田
Original Assignee
日本ビクター株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本ビクター株式会社 filed Critical 日本ビクター株式会社
Priority to JP1981159894U priority Critical patent/JPS5866769U/en
Publication of JPS5866769U publication Critical patent/JPS5866769U/en
Application granted granted Critical
Publication of JPH0212770Y2 publication Critical patent/JPH0212770Y2/ja
Granted legal-status Critical Current

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  • Amplifiers (AREA)
  • Noise Elimination (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のミューティング回路の１例を示すブロッ
ク系統図、第２図は本考案になるミューティング回路の
１実施例の回路図、第３図Ａ、　Ｂは第２図示の回路の
各部の信号波形図である。 １０・・・入力端子、１１・・・電源端子、１２・・・
出力端子、Ｃ工〜Ｃ５・・・コンデンサ、Ｄｌ・・・ダ
イオード、Ｑ□ｗ　Ｑ２・・・トランジスタ、Ｒ１−Ｒ
７・・・抵抗。Fig. 1 is a block diagram showing an example of a conventional muting circuit, Fig. 2 is a circuit diagram of an embodiment of the muting circuit according to the present invention, and Figs. 3A and B are diagrams of the circuit shown in Fig. 2. It is a signal waveform diagram of each part. 10...Input terminal, 11...Power terminal, 12...
Output terminal, C~C5...Capacitor, Dl...Diode, Q□w Q2...Transistor, R1-R
7...Resistance.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] その共振周波数が水平同期信号周波数とほぼ等しくされ
、供給された入力信号より水平同期信号に同期した信号
を取り出すための共振回路と、該共振回路より取り出さ
れた信号のレベルに応じてミューティング信号を出力す
る回路とよりなるミューティング回路。A resonant circuit whose resonant frequency is made almost equal to the horizontal synchronizing signal frequency and extracts a signal synchronized with the horizontal synchronizing signal from a supplied input signal, and a muting signal according to the level of the signal extracted from the resonant circuit. A muting circuit consisting of a circuit that outputs .
JP1981159894U 1981-10-27 1981-10-27 Muting circuit Granted JPS5866769U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981159894U JPS5866769U (en) 1981-10-27 1981-10-27 Muting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981159894U JPS5866769U (en) 1981-10-27 1981-10-27 Muting circuit

Publications (2)

Publication Number Publication Date
JPS5866769U true JPS5866769U (en) 1983-05-06
JPH0212770Y2 JPH0212770Y2 (en) 1990-04-10

Family

ID=29952328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981159894U Granted JPS5866769U (en) 1981-10-27 1981-10-27 Muting circuit

Country Status (1)

Country Link
JP (1) JPS5866769U (en)

Also Published As

Publication number Publication date
JPH0212770Y2 (en) 1990-04-10

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