JPS5864038A - Bonding plate - Google Patents
Bonding plateInfo
- Publication number
- JPS5864038A JPS5864038A JP56163010A JP16301081A JPS5864038A JP S5864038 A JPS5864038 A JP S5864038A JP 56163010 A JP56163010 A JP 56163010A JP 16301081 A JP16301081 A JP 16301081A JP S5864038 A JPS5864038 A JP S5864038A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- vacuum
- semiconductor element
- plate
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置の製造に用いるボンディングプレ
ートに係り、特にフィルムキャリヤ方式による同時ボン
ディング工程′に於て、ボンディング時に半導体素子を
保持しているボンディングプレートに関するものである
０ １
通常、半導体素子を接続するフィルムキャリヤは、例え
ば３５謳幅で数ピツチのパーフォレージ１ン毎に半導体
搭載用の穴をあけた帯状の可焼性絶縁フィルムに鋼箔を
接着し、写真蝕刻法により箔状のリードフレームが形成
されている。このフィルムキャリヤに接続される半導体
素子はボンデインクの際、半導体素子をクエハ状態での
配列を崩さずに供給する為、９エバを貼付基板にフック
ス等で貼付ケーＩｔ、、ｔｔダイシングしこの状態でボ
ンディングステージに供給される。−
第１図は、こＶノフィルムキャリャと半導体素子のボン
ディング方法を説明する為の概略図である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bonding plate used in the manufacture of semiconductor devices, and particularly to a bonding plate that holds a semiconductor element during bonding in a simultaneous bonding process using a film carrier method. 0 1 Normally, film carriers for connecting semiconductor devices are made by bonding steel foil to a strip of combustible insulating film with holes for mounting semiconductors at intervals of several perforations, for example, 35 cm wide, and then photo-etching the film. A foil-shaped lead frame is formed using a method. In order to supply the semiconductor elements to be connected to this film carrier without disrupting the arrangement of the semiconductor elements in a wafer state during bonding ink, 9 wafers are pasted onto the pasting substrate with hooks, etc., and then diced in this state. supplied to the bonding stage. - FIG. 1 is a schematic diagram for explaining a method of bonding a V-no film carrier and a semiconductor element.
図に於て、ｌは半導体素子、２は半導体素子１の貼付基
板、３は半導体素子１を固着保持しているワックス、４
は半導体素子１の電極パッドに形成された突起電極（バ
ンプ）、５はフィルムキャリヤ、６はフィルムキャリヤ
に形成されたリードフレーム（インナーリード）、７は
ボンディングリールである。以上６様な′配置に於て、
フイルムキ藏
ャリャ方式のボンディングは、先ず、インナーリードボ
ンダーのボンディングステージ（図示せず）にダイシン
グした半導体素子ｌが保持されている貼付基板２を方向
を合せて載せる。リールに巻いたフィルムキャリヤ５を
ボンダーにかけ、ボンディングステージ部に引き出し、
フィルムキャリヤ５のインナーリード６と半導体索子１
のバンブ４とを位置合せしたのち、ボンディングツール
７にパルス電流を流して加熱及び加圧し、熱圧涜または
Ａｕ−８ｎ等の共晶接合によってボンディングが行なわ
れる。この時ボンディングの熱でワックス３が融はボン
ディングツール７が上昇する時牛導体素子ｌは、インナ
ーリード６に引き上げられて、貼付基板２から分離され
る。これには、貼付基板２の熱伝導度、ワックスの融点
とボンディング条件（温度）とが調和していなければな
らない。In the figure, l is the semiconductor element, 2 is the substrate to which the semiconductor element 1 is attached, 3 is the wax that firmly holds the semiconductor element 1, and 4 is the wax that holds the semiconductor element 1 firmly.
Reference numeral 1 indicates a protruding electrode (bump) formed on an electrode pad of the semiconductor element 1, 5 a film carrier, 6 a lead frame (inner lead) formed on the film carrier, and 7 a bonding reel. In the above six arrangements,
In the film-type bonding, first, the bonding substrate 2 holding the diced semiconductor element 1 is placed on a bonding stage (not shown) of an inner lead bonder with the direction aligned. The film carrier 5 wound on a reel is placed on a bonder and pulled out to the bonding stage section.
Inner lead 6 of film carrier 5 and semiconductor cable 1
After aligning the bumps 4 with the bonding tool 7, a pulse current is applied to the bonding tool 7 to heat and pressurize it, and bonding is performed by heat pressure or eutectic bonding of Au-8n or the like. At this time, the wax 3 is melted by the heat of bonding, and when the bonding tool 7 rises, the conductive element 1 is pulled up by the inner lead 6 and separated from the bonded substrate 2. For this purpose, the thermal conductivity of the bonding substrate 2, the melting point of the wax, and the bonding conditions (temperature) must be in harmony.
熱伝導度が低く、ワックスの融点が低いと近接する半導
体素子の下のワックス（で融け、配列が崩れてしまい、
逆の場合は干セリックスが融けず、ボンディング後半導
体素子が貼付基板から離れにくい。またダイシングのダ
イヤモンドホイールの寿命の為には貼付基板は比較的軟
かく、ホイールに対し抵抗を与えない材料が望ましい。If the thermal conductivity is low and the melting point of the wax is low, the wax under the adjacent semiconductor elements will melt and the arrangement will collapse.
In the opposite case, the dried SELIX will not melt and the semiconductor element will be difficult to separate from the bonded substrate after bonding. In addition, in order to extend the life of the diamond wheel for dicing, it is desirable that the material to be attached is relatively soft and does not provide resistance to the wheel.
更に同時ボンディングである為、貼付基板に高い平行度
が！！＊されるので良い加工性イ、加工後の安定性−必
要になる。現在、この様な制約の中から最適の材料を見
出すことは、祷しく、フィルムキャリヤ方式によるボン
ディングに於る大きな問題点となっている。−即ちこの
貼付基板方式によるボンディングはウェハ形態のままで
ボンディング作業を行なうという位置合わせ時間の短縮
化を目的にするにもかかわらず現状はその材′ｊ！ｉ寺
によって位置合わせ時間の短縮化をさｔ九げるものであ
る。更に貼付基板にウェハを貼付けた状態で半導体索子
に分割する為完全切断する心安があり、ダイシングに於
てカッティングスピードが上げられない、又ダイヤモン
ドホイールの寿命が短かい等の間４もある。史にワック
スによる保持に於る牛導体パ子の組立工程は常にワック
ス除去の為の有機洗浄工程等が付随するという工程上の
問題４を吃含んでいる。Furthermore, because it is bonded simultaneously, the bonding board has a high degree of parallelism! ! *Good processability and stability after processing are required. Currently, it is difficult to find the most suitable material within such constraints, and it is a major problem in bonding using a film carrier method. -In other words, although the purpose of bonding using this bonding substrate method is to shorten the alignment time by performing the bonding operation while the wafer is still in the form, the current situation is that the material 'j' is not suitable for bonding. The i-temperature reduces the time required for alignment. Furthermore, since the wafer is divided into semiconductor strips with the wafer attached to the attached substrate, there is no need to worry about complete cutting, and there are other problems such as the cutting speed cannot be increased during dicing, and the life of the diamond wheel is short. Historically, the process of assembling cow conductor pads that has been retained with wax has always had the problem of process problems such as an accompanying organic cleaning process to remove wax.
本発明の目的および特徴は、ボンディングステージに於
て半導体索子を保持するボンディングプレートを従来の
貼付基板から半導体索子を真空吸着保持する為の孔を設
けることにより、これまでの問題点を解決する最適なボ
ンディングプレート全提供することにある。The purpose and feature of the present invention is to solve the problems of the past by providing a bonding plate that holds a semiconductor strand on a bonding stage with a hole for holding the semiconductor strand by vacuum suction from a conventional bonding substrate. We are here to provide you with the perfect bonding plate for you.
次に図面を用いて本発明の一実施例について詳述する。Next, one embodiment of the present invention will be described in detail using the drawings.
第２図は本発明の実施例のボンディングプレートによる
フィルムキャリヤ方式のボンディングを説明する為の説
明図である。第２図に於て８は、真空吸着孔９を持つ九
本発明のボンディングプレートである。本発明のボンデ
ィングプレートによるインナーリードボンディングは、
先ずボンダーのボンディングステージにボンディングプ
レート８の真空吸着孔９′を真空源の孔１０に合わせて
載せる。フィルムキャリヤ５は順次ボンディング位置に
送り込まれる０更に半導体索子１はワーク供給部（図示
せず）より、ボンディングプレート８の真空吸着乱丁な
わちボンディング位置に正確に供給される。このワーク
供給は、例えば平面上に引き延ばされた弾性シートに接
着された半導体素子を弾性体シートを介して突き上げ棒
を用いて半導体素子を突き上げ、移送アーム先端に取付
けられた吸着コレットにより吸着されアームの回転動作
等により正確にボンディング位置に置かれる。この時供
給された半導体索子１はボンディングプレート８に設け
られ九真空吸着孔より真空吸着保持される。その後フィ
ルムキャリヤ５のインナーリード６と半導体索子１のバ
ンプ４の位置合わせ完了に於てボンディングツール７に
よりインナーリードボンディングが行なわれる。FIG. 2 is an explanatory diagram for explaining film carrier type bonding using a bonding plate according to an embodiment of the present invention. In FIG. 2, 8 is a bonding plate of the present invention having vacuum suction holes 9. Inner lead bonding using the bonding plate of the present invention is as follows:
First, the bonding plate 8 is placed on the bonding stage of the bonder with the vacuum suction hole 9' of the bonding plate 8 aligned with the hole 10 of the vacuum source. The film carrier 5 is sequentially fed to the bonding position. Further, the semiconductor cable 1 is accurately fed to the bonding plate 8 by vacuum suction, that is, to the bonding position from a work supply section (not shown). This workpiece supply is carried out by, for example, pushing up a semiconductor element bonded to an elastic sheet stretched on a flat surface using a push-up rod through the elastic sheet, and adsorbing it with a suction collet attached to the tip of a transfer arm. The bonding position is accurately placed by rotating the arm. The semiconductor cable 1 supplied at this time is provided in the bonding plate 8 and held by vacuum suction through nine vacuum suction holes. Thereafter, when the alignment of the inner leads 6 of the film carrier 5 and the bumps 4 of the semiconductor cable 1 is completed, inner lead bonding is performed by the bonding tool 7.
即ち本発明のボンディングプレート８によるフィルムキ
ャリヤ方式のボンディングによると、ボンディング位置
による半導体素子の保持は真空成層による保持であるこ
とがら、従来方法の様な貼付基板の熱伝導度及びワック
スの融点挺にボンディング条件（温度）等の影響による
半導体素子の位置ずれが無くなり最適なボンディングを
提供するものである。更に、本発明によるとワックスを
使用しない為従来の組立工程に常に付随するワックス除
去の有機洗浄工程等が省略できるという工根上大きな効
果を生むことは云うまでもない。更に又本発明によると
、半導体ウェハから半導体素子に分割する各種一連の工
程、いわゆるベレッタイズエ楊及び次工程へのハンドリ
ング方式等がそのまま取り入れられること、位置ずれに
於てもワックスによる影響等不確定要素が黒いこと尋に
よジ自動化等が更に容易に実施できる効果も優られる０That is, according to the film carrier type bonding using the bonding plate 8 of the present invention, since the semiconductor element is held at the bonding position by vacuum lamination, the thermal conductivity of the bonded substrate and the melting point of the wax are not affected as in the conventional method. This eliminates misalignment of the semiconductor element due to the effects of bonding conditions (temperature), etc., and provides optimal bonding. Furthermore, since the present invention does not use wax, it goes without saying that the process of organic cleaning for removing wax, etc., which is always associated with the conventional assembly process, can be omitted, which is a great advantage in terms of engineering. Furthermore, according to the present invention, a series of processes for dividing a semiconductor wafer into semiconductor elements, such as so-called pelletizing and handling methods for the next process, can be directly incorporated, and uncertain factors such as the influence of wax on positional deviation can be eliminated. However, the effect of automation, etc., being easier to implement is also excellent.
第１図は、従来のフィルムキャリヤと牛棉体累子のボン
ディング方法を説明する概略図、第２図は本発明のボン
ディングプレートによるボンディングを説明する概略図
である。
図に於て、１・・・・・・半導体素子、２・・・・・・
貼付蒸機、３・・・・・・ワックス、４・・・・・・バ
ンプ、５・・・・・・フィルムキャリヤ、６・・・・・
・リードフレーム（インナーリード）、７・・・・・・
ポンディグツール、８・・・・・・真空ａ層孔？持った
ボンディングプレート、９・・・・・・真空吸着孔、１
０・・・・・・真空源の孔である。FIG. 1 is a schematic diagram illustrating a conventional bonding method between a film carrier and a Ushidanshi yoko, and FIG. 2 is a schematic diagram illustrating bonding using a bonding plate of the present invention. In the figure, 1...semiconductor element, 2...
Pasting steamer, 3... Wax, 4... Bump, 5... Film carrier, 6...
・Lead frame (inner lead), 7...
Ponding tool, 8... Vacuum A-layer hole? Bonding plate held, 9... Vacuum suction hole, 1
0...This is the hole of the vacuum source.
Claims (1)
する半導体装置の製造に用いるボンディングプレートに
於て、半導体基板を分離して各々の前記半導体素子をボ
ンディング位置に於て、真空吸着保持した状態で前記接
続を行なわせる為の真空吸着孔を持−）九ことを特徴と
するボンディングプレート。[Claims] A plurality of inner leads of a lead frame. In a bonding plate used for manufacturing a semiconductor device that simultaneously and continuously connects multiple electrodes of a semiconductor element, a semiconductor substrate is separated and each semiconductor element is held at a bonding position by vacuum suction. 9. A bonding plate characterized in that it has vacuum suction holes for making the connection in the above-mentioned state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56163010A JPS5864038A (en) | 1981-10-13 | 1981-10-13 | Bonding plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56163010A JPS5864038A (en) | 1981-10-13 | 1981-10-13 | Bonding plate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5864038A true JPS5864038A (en) | 1983-04-16 |
| JPS6250057B2 JPS6250057B2 (en) | 1987-10-22 |
Family
ID=15765474
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56163010A Granted JPS5864038A (en) | 1981-10-13 | 1981-10-13 | Bonding plate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5864038A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0316237A (en) * | 1989-06-14 | 1991-01-24 | Toshiba Seiki Kk | Inner lead bonder |
| CN106068555A (en) * | 2014-03-19 | 2016-11-02 | 信越半导体株式会社 | Work-supporting means |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02117879U (en) * | 1989-03-06 | 1990-09-20 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5776850A (en) * | 1980-10-30 | 1982-05-14 | Nec Corp | Manufacture device for semiconductor device |
| JPS5832426A (en) * | 1981-08-20 | 1983-02-25 | Seiko Epson Corp | Integrated circuit chip receiving base of inner lead bonder |
-
1981
- 1981-10-13 JP JP56163010A patent/JPS5864038A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5776850A (en) * | 1980-10-30 | 1982-05-14 | Nec Corp | Manufacture device for semiconductor device |
| JPS5832426A (en) * | 1981-08-20 | 1983-02-25 | Seiko Epson Corp | Integrated circuit chip receiving base of inner lead bonder |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0316237A (en) * | 1989-06-14 | 1991-01-24 | Toshiba Seiki Kk | Inner lead bonder |
| CN106068555A (en) * | 2014-03-19 | 2016-11-02 | 信越半导体株式会社 | Work-supporting means |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6250057B2 (en) | 1987-10-22 |
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