JPS6250057B2 - - Google Patents
Info
- Publication number
- JPS6250057B2 JPS6250057B2 JP56163010A JP16301081A JPS6250057B2 JP S6250057 B2 JPS6250057 B2 JP S6250057B2 JP 56163010 A JP56163010 A JP 56163010A JP 16301081 A JP16301081 A JP 16301081A JP S6250057 B2 JPS6250057 B2 JP S6250057B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- semiconductor element
- wax
- vacuum suction
- film carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 35
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 description 15
- 239000000758 substrate Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910015363 Au—Sn Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000005453 pelletization Methods 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Description
【発明の詳細な説明】
本発明は、半導体装置の製造に用いるボンデイ
ングプレートに係り、特にフイルムキヤリヤ方式
による同時ボンデイング工程に於て、ボンデイン
グ時に半導体素子を保持しているボンデイングプ
レートに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bonding plate used in the manufacture of semiconductor devices, and particularly to a bonding plate that holds a semiconductor element during bonding in a simultaneous bonding process using a film carrier method. .
通常、半導体素子を接続するフイルムキヤリヤ
は、例えば35mm幅で数ピツチのパーフオレーシヨ
ン毎に半導体搭載用の穴をあけた帯状の可撓性絶
縁フイルムに銅箔を接着し、写真蝕刻法により箔
状のリードフレームが形成されている。このフイ
ルムキヤリヤに接続される半導体素子はボンデイ
ングの際、半導体素子をウエハ状態での配列を崩
さずに供給する為、ウエハを貼付基板にワツクス
等で貼付けたままダイシングしこの状態でボンデ
イングステージに供給される。 Normally, film carriers for connecting semiconductor devices are made by bonding copper foil to a strip-shaped flexible insulating film that is 35 mm wide and has holes for mounting semiconductors at every few pitches of perforation. A foil-like lead frame is formed. During bonding, the semiconductor elements connected to this film carrier are supplied without disrupting the arrangement of the semiconductor elements in the wafer state, so the wafer is diced with the wafer attached to the wafer with wax or the like and transferred to the bonding stage in this state. Supplied.
第１図は、このフイルムキヤリヤと半導体素子
のボンデイング方法を説明する為の概略図であ
る。図に於て、１は半導体素子、２は半導体素子
１の貼付基板、３は半導体素子１を固着保持して
いるワツクス、４は半導体素子１の電極パツドに
形成された突起電極（バンプ）、５はフイルムキ
ヤリヤ、６はフイルムキヤリヤに形成されたリー
ドフレーム（インナーリード）、７はボンデイン
グリールである。以上の様な配置に於て、フイル
ムキヤリヤ方式のボンデイングは、先ず、インナ
ーリードボンダーのボンデイングステージ（図示
せず）にダイシングした半導体素子１が保持され
ている貼付基板２を方向を合せて載せる。リール
に巻いたフイルムキヤリヤ５をボンダーにかけ、
ボンデイングステージ部に引き出し、フイルムキ
ヤリヤ５のインナーリード６と半導体素子１のバ
ンプ４とを位置合せしたのち、ボンデイングツー
ル７にパルス電流を流して加熱及び加圧し、熱圧
着またはAu−Sn等の共晶接合によつてボンデイ
ングが行なわれる。この時ボンデイングの熱でワ
ツクス３が融けボンデイングツール７が上昇する
時半導体素子１は、インナーリード６に引き上げ
られて、貼付基板２から分離される。これには、
貼付基板２の熱伝導度、ワツクスの融点とボンデ
イング条件（温度）とが調和していなければなら
ない。熱伝導度が低く、ワツクスの融点が低いと
近接する半導体素子の下のワツクスまで融け、配
列が崩れてしまい、逆の場合は十分ワツクスが融
けず、ボンデイング後半導体素子が貼付基板から
離れにくい。またダイシングのダイヤモンドホイ
ールの寿命の為には貼付基板は比較的軟かく、ホ
イールに対し抵抗を与えない材料が望ましい。更
に同時ボンデイングである為、貼付基板に高い平
行度が要求されるので良い加工性、加工後の安定
性も必要になる。現在、この様な制約の中から最
適の材料を見出すことは、難しく、フイルムキヤ
リヤ方式によるボンデイングに於る大きな問題点
となつている。即ちこの貼付基板方式によるボン
デイングはウエハ形態のままでボンデイング作業
を行なうという位置合わせ時間の短縮化を目的に
するにもかかわらず現状はその材質等によつて位
置合わせ時間の短縮化をさまたげるものである。
更に貼付基板にウエハを貼付けた状態で半導体素
子に分割する為完全切断する必要があり、ダイシ
ングに於てカツテイングスピードが上げられな
い、又ダイヤモンドホイールの寿命が短かい等の
問題もある。更にワツクスによる保持に於る半導
体素子の組立工程は常にワツクス除去の為の有機
洗浄工程等が付随するという工程上の問題点をも
含んでいる。 FIG. 1 is a schematic diagram for explaining the bonding method of this film carrier and a semiconductor element. In the figure, 1 is a semiconductor element, 2 is a substrate to which the semiconductor element 1 is attached, 3 is wax that firmly holds the semiconductor element 1, 4 is a protruding electrode (bump) formed on the electrode pad of the semiconductor element 1, 5 is a film carrier, 6 is a lead frame (inner lead) formed on the film carrier, and 7 is a bonding reel. In the above-described arrangement, in film carrier bonding, first, the bonding substrate 2 holding the diced semiconductor element 1 is placed on the bonding stage (not shown) of the inner lead bonder with the direction aligned. . Put the film carrier 5 wound on the reel on the bonder,
After pulling it out to the bonding stage section and aligning the inner leads 6 of the film carrier 5 and the bumps 4 of the semiconductor element 1, a pulse current is applied to the bonding tool 7 to heat and pressurize it, and bond it by thermocompression or Au-Sn etc. Bonding is performed by eutectic bonding. At this time, when the wax 3 melts due to the heat of bonding and the bonding tool 7 rises, the semiconductor element 1 is pulled up by the inner leads 6 and separated from the bonded substrate 2. This includes:
The thermal conductivity of the bonding substrate 2, the melting point of the wax, and the bonding conditions (temperature) must be in harmony. If the thermal conductivity is low and the melting point of the wax is low, the wax under the adjacent semiconductor elements will melt and the arrangement will be disrupted.In the opposite case, the wax will not melt sufficiently and the semiconductor elements will be difficult to separate from the bonded substrate after bonding. In addition, in order to extend the life of the diamond wheel for dicing, it is desirable that the material to be attached is relatively soft and does not provide resistance to the wheel. Furthermore, since it is simultaneous bonding, a high degree of parallelism is required for the bonded substrate, so good workability and stability after processing are also required. Currently, it is difficult to find the most suitable material within such constraints, and this has become a major problem in bonding using the film carrier method. In other words, although bonding using this bonding substrate method aims to shorten the alignment time by performing the bonding operation while the wafer is in the form of a wafer, the current situation is that shortening of the alignment time is hindered by the material etc. be.
Furthermore, it is necessary to completely cut the wafer attached to the wafer to separate it into semiconductor elements, which poses problems such as the cutting speed cannot be increased during dicing and the life of the diamond wheel is short. Furthermore, the process of assembling semiconductor devices using wax always involves a process problem such as an organic cleaning process for removing the wax.
本発明の目的および特徴は、ボンデイングステ
ージに於て半導体素子を保持するボンデイングプ
レートを従来の貼付基板から半導体素子を真空吸
着保持する為の孔を設けることにより、これまで
の問題点を解決する最適なボンデイングプレート
を提供することにある。ここでボンデイングプレ
ートの孔はボンデイングステージの孔よりも小さ
くするから、ボンデイングプレートはボンデイン
グステージに真空吸着できる。又、ボンデイング
ステージの孔よりも小さい半導体素子も本発明の
ボンデイングプレートを介在させることにより確
実に真空吸着をすることができる。 The purpose and characteristics of the present invention are to provide an optimal solution to the problems of the past by providing a bonding plate that holds a semiconductor element on a bonding stage with holes for vacuum suction and holding of a semiconductor element from a conventional bonding substrate. Our objective is to provide a bonding plate that is suitable for Here, since the holes in the bonding plate are made smaller than the holes in the bonding stage, the bonding plate can be vacuum-adsorbed to the bonding stage. Furthermore, by interposing the bonding plate of the present invention, semiconductor elements smaller than the holes of the bonding stage can be reliably vacuum-adsorbed.
次に図面を用いて本発明の一実施例について詳
述する。第２図は本発明の実施例のボンデイング
プレートによるフイルムキヤリヤ方式のボンデイ
ングを説明する為の説明図である。第２図に於て
８は、真空吸着孔９を持つた本発明のボンデイン
グプレートである。本発明のボンデイングプレー
トによるインナーリードボンデイングは、先ずボ
ンダーのボンデイングステージにボンデイングプ
レート８の真空吸着孔９を真空源の孔１０に合わ
せて載せる。フイルムキヤリヤ５は順次ボンデイ
ング位置に送り込まれる。更に半導体素子１はワ
ーク供給部（図示せず）より、ボンデイングプレ
ート８の真空吸着孔すなわちボンデイング位置に
正確に供給される。このワーク供給は、例えば平
面上に引き延ばされた弾性シートに接着された半
導体素子を弾性体シートを介して突き上げ棒を用
いて半導体素子を突き上げ、移送アーム先端に取
付けられた吸着コレツトにより吸着されアームの
回転動作等により正確にボンデイング位置に置か
れる。この時供給された半導体素子１はボンデイ
ングプレート８に設けられた真空吸着孔より真空
吸着保持される。その後フイルムキヤリヤ５のイ
ンナーリード６と半導体素子１のバンプ４の位置
合わせ完了に於てボンデイングツール７によりイ
ンナーリードボンデイングが行なわれる。 Next, one embodiment of the present invention will be described in detail using the drawings. FIG. 2 is an explanatory diagram for explaining film carrier type bonding using a bonding plate according to an embodiment of the present invention. In FIG. 2, numeral 8 denotes a bonding plate of the present invention having vacuum suction holes 9. Inner lead bonding using the bonding plate of the present invention, first, the bonding plate 8 is placed on the bonding stage of the bonder with the vacuum suction holes 9 of the bonding plate 8 aligned with the holes 10 of the vacuum source. The film carriers 5 are successively fed into the bonding position. Furthermore, the semiconductor element 1 is accurately supplied to the vacuum suction hole of the bonding plate 8, that is, to the bonding position, from a workpiece supply section (not shown). This workpiece supply is carried out, for example, by pushing up a semiconductor element bonded to an elastic sheet stretched on a flat surface using a push-up rod through the elastic sheet, and then sucking it up with a suction collet attached to the tip of a transfer arm. The bonding position is precisely placed by rotating the arm. The semiconductor element 1 supplied at this time is held by vacuum suction through a vacuum suction hole provided in the bonding plate 8. Thereafter, when the alignment of the inner leads 6 of the film carrier 5 and the bumps 4 of the semiconductor element 1 is completed, inner lead bonding is performed by the bonding tool 7.
即ち本発明のボンデイングプレート８によるフ
イルムキヤリヤ方式のボンデイングによると、ボ
ンデイング位置による半導体素子の保持は真空吸
着による保持であることから、従来方法の様な貼
付基板の熱伝導度及びワツクスの融点更にボンデ
イング条件（温度）等の影響による半導体素子の
位置ずれが無くなり最適なボンデイングを提供す
るものである。更に、本発明によるとワツクスを
使用しない為従来の組立工程に常に付随するワツ
クス除去の有機洗浄工程等が省略できるという工
程上大きな効果を生むことは云うまでもない。更
に又本発明によると、半導体ウエハから半導体素
子に分割する各種一連の工程、いわゆるペレツタ
イズ工程及び次工程へのハンドリング方式等がそ
のまま取り入れられること、位置ずれに於てもワ
ツクスによる影響等不確定要素が無いこと等によ
り自動化等が更に容易に実施できる効果も得られ
る。 That is, according to the film carrier type bonding using the bonding plate 8 of the present invention, since the semiconductor element is held by vacuum suction at the bonding position, the thermal conductivity of the bonded substrate and the melting point of the wax are different from those in the conventional method. This eliminates misalignment of the semiconductor element due to the effects of bonding conditions (temperature), etc., and provides optimal bonding. Furthermore, since the present invention does not use wax, it goes without saying that the organic cleaning process for removing wax, etc., which is always associated with the conventional assembly process, can be omitted, which is a great advantage in terms of the process. Furthermore, according to the present invention, a series of processes for dividing a semiconductor wafer into semiconductor elements, such as a so-called pelletizing process and a handling method for the next process, can be directly incorporated, and uncertain factors such as the influence of wax on positional deviation can be eliminated. There is also the effect that automation can be implemented more easily due to the absence of such functions.
第１図は、従来のフイルムキヤリヤと半導体素
子のボンデイング方法を説明する概略図、第２図
は本発明のボンデイングプレートによるボンデイ
ングを説明する概略図である。
図に於て、１……半導体素子、２……貼付基
板、３……ワツクス、４……バンプ、５……フイ
ルムキヤリヤ、６……リードフレーム（インナー
リード）、７……ボンデイグツール、８……真空
吸着孔を持つたボンデイングプレート、９……真
空吸着孔、１０……真空源の孔である。
FIG. 1 is a schematic diagram illustrating a conventional method of bonding a film carrier and a semiconductor element, and FIG. 2 is a schematic diagram illustrating bonding using a bonding plate of the present invention. In the figure, 1... Semiconductor element, 2... Bonding substrate, 3... Wax, 4... Bump, 5... Film carrier, 6... Lead frame (inner lead), 7... Bonding tool. , 8...A bonding plate having vacuum suction holes, 9...Vacuum suction holes, 10...Vacuum source holes.
Claims (1)
半導体素子の複数個の電極とを同時にかつ連続的
に接続する半導体装置の製造に用いるボンデイン
グプレートであつて、第１の真空吸着孔を有する
ボンデイングステージ上に載置され、前記半導体
素子を真空吸着しかつ該第１の真空吸着孔より小
さい第２の真空吸着孔を有することを特徴とする
ボンデイングプレート。1. A bonding plate used for manufacturing a semiconductor device that simultaneously and continuously connects a plurality of inner leads of a lead frame and a plurality of electrodes of a semiconductor element, which is mounted on a bonding stage having a first vacuum suction hole. What is claimed is: 1. A bonding plate having a second vacuum suction hole which is placed on the semiconductor element and which vacuum suctions the semiconductor element and is smaller than the first vacuum suction hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56163010A JPS5864038A (en) | 1981-10-13 | 1981-10-13 | Bonding plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56163010A JPS5864038A (en) | 1981-10-13 | 1981-10-13 | Bonding plate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5864038A JPS5864038A (en) | 1983-04-16 |
| JPS6250057B2 true JPS6250057B2 (en) | 1987-10-22 |
Family
ID=15765474
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56163010A Granted JPS5864038A (en) | 1981-10-13 | 1981-10-13 | Bonding plate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5864038A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02117879U (en) * | 1989-03-06 | 1990-09-20 |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2754043B2 (en) * | 1989-06-14 | 1998-05-20 | 東芝メカトロニクス株式会社 | Inner lead bonder |
| JP6032234B2 (en) * | 2014-03-19 | 2016-11-24 | 信越半導体株式会社 | Work holding device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5776850A (en) * | 1980-10-30 | 1982-05-14 | Nec Corp | Manufacture device for semiconductor device |
| JPS5832426A (en) * | 1981-08-20 | 1983-02-25 | Seiko Epson Corp | Integrated circuit chip receiving base of inner lead bonder |
-
1981
- 1981-10-13 JP JP56163010A patent/JPS5864038A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5776850A (en) * | 1980-10-30 | 1982-05-14 | Nec Corp | Manufacture device for semiconductor device |
| JPS5832426A (en) * | 1981-08-20 | 1983-02-25 | Seiko Epson Corp | Integrated circuit chip receiving base of inner lead bonder |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02117879U (en) * | 1989-03-06 | 1990-09-20 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5864038A (en) | 1983-04-16 |
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