JPS586322B2 - Integrated circuit with thermal feedback in mind - Google Patents

Integrated circuit with thermal feedback in mind

Info

Publication number
JPS586322B2
JPS586322B2 JP50019735A JP1973575A JPS586322B2 JP S586322 B2 JPS586322 B2 JP S586322B2 JP 50019735 A JP50019735 A JP 50019735A JP 1973575 A JP1973575 A JP 1973575A JP S586322 B2 JPS586322 B2 JP S586322B2
Authority
JP
Japan
Prior art keywords
transistor
differential
transistors
integrated circuit
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50019735A
Other languages
Japanese (ja)
Other versions
JPS5194745A (en
Inventor
要 太田
不二男 町田
邦夫 関
徹 三瓶
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP50019735A priority Critical patent/JPS586322B2/en
Publication of JPS5194745A publication Critical patent/JPS5194745A/ja
Publication of JPS586322B2 publication Critical patent/JPS586322B2/en
Expired legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明は差動入力段と、交番熱源例えばB級プッシュプ
ル構成の出力段とを同一チップ内に有する集積回路に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit having a differential input stage and an output stage with an alternating heat source, e.g. class B push-pull configuration, on the same chip.

この種集積回路において熱帰還の問題があり、その対策
として差動入力段の差動素子を熱源に対し熱的平衡位置
に配置する方法と、入力段と熱源との距離を充分に取る
方法がある。
There is a problem of thermal feedback in this type of integrated circuit, and as a countermeasure, there are methods to place the differential elements of the differential input stage in a thermally balanced position with respect to the heat source, and methods to maintain a sufficient distance between the input stage and the heat source. be.

しかし前者の方法は複数の熱源がある場合において、そ
れらの熱帰還効果を積算した最小点に配置することであ
り、これだけでは満足な性能は得られない場合が多い。
However, in the former method, when there are multiple heat sources, they are placed at the minimum point that integrates their heat feedback effects, and this alone often does not provide satisfactory performance.

従って一般には前者と後者を併用して熱帰還効果を或る
値以下に押し込めているが、一般に後者の方法で必要な
距離はかなり大きくなり半導体ペレットのサイズを大な
らしめるという欠点があった。
Therefore, the former and the latter are generally used in combination to suppress the thermal feedback effect below a certain value, but the latter method generally has the drawback that the required distance is considerably large, increasing the size of the semiconductor pellet.

そこで本出願人は先に第1図,第2図に示す回路および
配置を提案した。
Therefore, the present applicant previously proposed the circuit and arrangement shown in FIGS. 1 and 2.

即ち差動トランジスタ111,112のエミツタにダイ
オード113,114を設け、そしてこれらを出力トラ
ンジスタ121,122から発生する熱の影響が差動入
力の双方で同一同相成分となるように配置したものであ
る。
That is, diodes 113 and 114 are provided at the emitters of differential transistors 111 and 112, and these are arranged so that the influence of heat generated from output transistors 121 and 122 becomes the same common-mode component on both differential inputs. .

これによれば、差動入力段と出力段との距離言換ればペ
レットのサイズを大きくすることなく熱帰還を軽減でき
る効果がある。
According to this, there is an effect that heat feedback can be reduced without increasing the size of the pellet, in other words, the distance between the differential input stage and the output stage.

しかしこの回路は差動トランジスタ111,112,の
エミツタにダイオード113,114を接続しているの
で、そのダイオードの立上り電圧だけ入力端子間の電圧
が大きくなり減電圧的に不利である。
However, since this circuit has diodes 113 and 114 connected to the emitters of differential transistors 111 and 112, the voltage between the input terminals increases by the rising voltage of the diodes, which is disadvantageous in terms of voltage reduction.

本発明の目的は上記従来技術の欠点をなくし、半導体ペ
レットのサイズを拡大することなしにだ帰還の効果を低
減することができかつ減電圧特伯の優れた方法を提供す
ることにある。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide an excellent method for reducing voltage, which can reduce the feedback effect without increasing the size of the semiconductor pellet.

以下本発明の実施例を図面に基づいて説明する第3図は
本発明の実施例を示す概略回路図、第4図はその回路部
品の配置図である。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is a schematic circuit diagram showing an embodiment of the present invention, and FIG. 4 is a layout diagram of the circuit components.

これらの図■において100は差動構成の入力段110
と熱湧である出力段120を有した集積回路、111,
111′および112,112’は入力段110の初段
差動増幅トランジスタであって、トランジスタ111と
111′及び112と112′は夫々差列に接続され、
トランジスタ111,111’と112,112’は差
動的に構成されている。
In these figures, 100 is an input stage 110 with a differential configuration.
and an integrated circuit having an output stage 120, 111,
111', 112, and 112' are first-stage differential amplification transistors of the input stage 110, and the transistors 111 and 111' and 112 and 112' are connected in a differential series, respectively.
Transistors 111, 111' and 112, 112' are configured differentially.

121,122は出力段120のB級プッシュプル構成
の出力トランジスタである。
121 and 122 are output transistors of the output stage 120 having a class B push-pull configuration.

そしてこれら対の差動トランジスタ111,111’、
および112,112’と出力トランジスタ121,1
22は第4図或は第5図に示す如く配置してある。
And these pairs of differential transistors 111, 111',
and 112, 112' and output transistor 121, 1
22 are arranged as shown in FIG. 4 or 5.

即ち入力差動トランジスタ回路110と、出力トランジ
スタ回路120はある距離L例えば1000μm程度の
距離をおいて夫々対向して配置し、かつ差動トランジス
タ回路110の4個の差動トランジスタ111,111
’,112,112′は、トランジスタ111,111
’,112,112’の熱源120から受ける影響がト
ランジスタ111+トランジスタ111’=トランジス
タ112+トランジスタ112′となる如くそれらを夫
々対称に配置する。
That is, the input differential transistor circuit 110 and the output transistor circuit 120 are arranged facing each other with a certain distance L, for example, about 1000 μm, and the four differential transistors 111, 111 of the differential transistor circuit 110
', 112, 112' are transistors 111, 111
', 112, 112' are arranged symmetrically so that the influence from the heat source 120 is as follows: transistor 111+transistor 111'=transistor 112+transistor 112'.

このように配置すると、出力トランジスタ121から見
た差動トランジスタ111,111’までの距離a,d
の和a+dと差動トランジスタ112,112’までの
距離c,bの和とが等しくなる。
With this arrangement, the distances a and d from the output transistor 121 to the differential transistors 111 and 111' are
The sum a+d is equal to the sum of the distances c and b to the differential transistors 112 and 112'.

このことは出力トランジスタ122から見た場合も同様
である。
This also applies when viewed from the output transistor 122.

従ってこの場合には出力トランジスタ121または12
2が差動トランジスタ111,111’および差動トラ
ンジスタ112,112’とで構成される差動対入力に
与える熱的効果は等しくなり、同相同一入力となって出
力端には現われない・つまり第3図に示す回路構成にお
いて差動トランジスタ111,111’,112,11
2’のコレクタ電流Icを Ic=A(expBVbe−1)・・・・・(1)(但
しA,B定数)とし、そのベース・エミッタ間電圧Vb
eの非常に少さな変化△Vbeによりコレクタ電流Ic
に与える影響を△■cとすれば、(1)式を微分して(
2)式となる。
Therefore, in this case, the output transistor 121 or 12
2 has the same thermal effect on the differential pair input composed of the differential transistors 111, 111' and the differential transistors 112, 112', and the inputs are the same in phase and do not appear at the output terminal. In the circuit configuration shown in FIG. 3, differential transistors 111, 111', 112, 11
2' collector current Ic is Ic=A(expBVbe-1) (1) (where A and B are constants), and its base-emitter voltage Vb
Due to a very small change in e, △Vbe, the collector current Ic
If the influence on is △■c, then by differentiating equation (1), we get (
2) Equation becomes.

△Ic=ABIc・△vbe……(2) ここで△Vbeは熱帰還によるVbeの変化であり、△
Iはこれに起因するIcの変化である。
△Ic=ABIc・△vbe...(2) Here, △Vbe is the change in Vbe due to thermal feedback, and △
I is the change in Ic caused by this.

従って第3図の差動トランジスタ111,111’,1
12,112’が受ける熱帰還の量を夫々△Vbc4v
△Vbe2,△Vbe3,△Vbe4とし、△Iclg
△1c2,△Ic3,△Ic4をその結果の)Icの変
化とすれば、4個の差動トランジスタ111,111’
,112,112’を△vbe1(トランジスタ111
)+△Vbe3(トランジスタ111’)=△Vbe2
(トランジスタ112)+△Vbe4(トランジスタ1
12’)となるように配置することにより△Ic1(ト
ランジスタ111)+△Ic3(トランジスタ111’
)=△Ic2(トランジスタ112)+△■c4(トラ
ンジスタ112’)となり差動出力を零にすることがで
きる。
Therefore, the differential transistors 111, 111', 1 in FIG.
The amount of heat feedback received by 12 and 112' is △Vbc4v, respectively.
△Vbe2, △Vbe3, △Vbe4, △Iclg
If △1c2, △Ic3, △Ic4 are the resulting changes in Ic, the four differential transistors 111, 111'
, 112, 112' as △vbe1 (transistor 111
) + △Vbe3 (transistor 111') = △Vbe2
(Transistor 112) + △Vbe4 (Transistor 1
12'), △Ic1 (transistor 111) + △Ic3 (transistor 111')
)=ΔIc2 (transistor 112)+Δ■c4 (transistor 112'), and the differential output can be made zero.

第4図は横軸に周波数Hzをとり、縦軸に入出力信号の
比dBをとって熱による帰還量を示した特性図であり、
Aは本発明の回路構成および部品配置に基づく特性曲線
、Bは従来の回路構成および部品配置に基づく特性曲線
である。
FIG. 4 is a characteristic diagram showing the amount of feedback due to heat, with the horizontal axis representing the frequency Hz and the vertical axis representing the input/output signal ratio dB.
A is a characteristic curve based on the circuit configuration and component placement of the present invention, and B is a characteristic curve based on the conventional circuit configuration and component placement.

この特性図から本発明は従来に比べ帰還量が小さくその
影響が小さいことが分る。
From this characteristic diagram, it can be seen that the amount of feedback in the present invention is smaller than that in the prior art, and its influence is small.

以上述べた本発明によれば、従来の如く熱帰還を防止す
るのに入力段と出力段の距離を大きく取ることなしに同
等以上の効果を上げることができ、ペレット面積を従来
よりも小さくできる。
According to the present invention as described above, it is possible to achieve the same or better effect without increasing the distance between the input stage and the output stage to prevent heat feedback as in the past, and the pellet area can be made smaller than before. .

また本発明によれば、入力段トランジスタのエミツタに
ダイオードを接続していないから減電圧的に有利である
Further, according to the present invention, since no diode is connected to the emitter of the input stage transistor, it is advantageous in terms of voltage reduction.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来入力部と出力部の回路の一部を抜き書きし
た概略回路図、第2図はその部品の配置図、第3図は本
発明の高利得増幅器の入力部と出力部の回路の一部を抜
き書きした概略回路図、第4図はその部品の配置図、第
5図は本発明の入力部部品の配置図、第6図は本発明の
説明に供する特性曲線図である。 110・・・入力段、120・・・出力段、111,1
11’,112,112’,121,122・・・トラ
ンジスタ。
Fig. 1 is a schematic circuit diagram in which a part of the conventional input section and output section circuit is extracted, Fig. 2 is a layout diagram of the components, and Fig. 3 is a schematic diagram of the input section and output section of the high gain amplifier of the present invention. FIG. 4 is a schematic circuit diagram in which a part of the circuit is extracted, FIG. 4 is a layout diagram of its components, FIG. 5 is a layout diagram of input part components of the present invention, and FIG. 6 is a characteristic curve diagram for explaining the present invention. be. 110...Input stage, 120...Output stage, 111,1
11', 112, 112', 121, 122...transistor.

Claims (1)

【特許請求の範囲】[Claims] 1 差動入力段および少なくとも2つ以上の熱源を同一
チップ内に有する集積回路において、差動入力段を少な
くとも2つ以上の並列トランジスタペアA,C,…およ
びB,D,…で構成しこれら各トランジスタA,C,…
およびB,D…と、これらゐ各トランジスタの第1の熱
源との距離をそれぞれa,c…およびb,dとし、第2
の熱源との距離をそれぞれa′,c′…およびb/ ,
d/としたときa+c+…=b+d+…,並びにa’
+d’+…の関係を満足する如く上記トランジスタA,
B,C,D,…および上記第1,第2の熱源を配置構成
し、以下同様にして複数の熱源のそれぞれからの熱帰還
量が差動入力段の正,負入力間で等しくなるように配置
したことを特徴とする熱帰還を考慮した集積回路。
1 In an integrated circuit having a differential input stage and at least two or more heat sources in the same chip, the differential input stage is composed of at least two or more parallel transistor pairs A, C, ... and B, D, ... Each transistor A, C,...
and B, D... and the first heat source of each of these transistors are respectively a, c... and b, d, and the second
The distances from the heat source to the heat source are respectively a', c'... and b/,
When d/, a+c+...=b+d+..., and a'
The above transistors A, so as to satisfy the relationship +d'+...
B, C, D, ... and the above-mentioned first and second heat sources are arranged and configured in the same manner so that the amount of heat feedback from each of the plurality of heat sources is equal between the positive and negative inputs of the differential input stage. An integrated circuit that takes thermal feedback into consideration, characterized in that it is arranged in a.
JP50019735A 1975-02-19 1975-02-19 Integrated circuit with thermal feedback in mind Expired JPS586322B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50019735A JPS586322B2 (en) 1975-02-19 1975-02-19 Integrated circuit with thermal feedback in mind

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50019735A JPS586322B2 (en) 1975-02-19 1975-02-19 Integrated circuit with thermal feedback in mind

Publications (2)

Publication Number Publication Date
JPS5194745A JPS5194745A (en) 1976-08-19
JPS586322B2 true JPS586322B2 (en) 1983-02-04

Family

ID=12007570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50019735A Expired JPS586322B2 (en) 1975-02-19 1975-02-19 Integrated circuit with thermal feedback in mind

Country Status (1)

Country Link
JP (1) JPS586322B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH037867Y2 (en) * 1983-07-22 1991-02-27

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5337353A (en) * 1976-09-17 1978-04-06 Matsushita Electric Ind Co Ltd Amplifier
JPS5573114A (en) * 1978-11-28 1980-06-02 Nippon Gakki Seizo Kk Output offset control circuit for full step direct-coupled amplifier
JPS61142763A (en) * 1984-12-14 1986-06-30 Mitsubishi Electric Corp Bipolar semiconductor integrated circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4895194A (en) * 1972-03-16 1973-12-06
JPS49104586A (en) * 1973-02-07 1974-10-03

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4895194A (en) * 1972-03-16 1973-12-06
JPS49104586A (en) * 1973-02-07 1974-10-03

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH037867Y2 (en) * 1983-07-22 1991-02-27

Also Published As

Publication number Publication date
JPS5194745A (en) 1976-08-19

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