JPS5861660A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To fill elements with insulating layers and leave the insulating film on elements, by applying an even exposure from the substrate back surface and a pattern exposure from the surface on the resist layer coating insular elements on a transparent insulating substrate. CONSTITUTION:Insular Si n layer 2 and npn element part 8 are formed on the sapphire substrate 1, the insulating layer 3 approx. the same in thickness as the Si layer is deposited, and the resist 9 is applied. When evenly exposing 10 from the side of the substrate 1, the part 9 becomes sensitive. Subsequently, the part 9' is made sensitive by the mask 11 from the surface. It is developed, the insulator layer is corrosion-removed by the resist mask, the interval between layers 2 and 8 is filled flat with the insulator layer 3', and accordingly the thick insulator layer 3 is left on the layer 2. Next, when a gate oxide film 13, poly Si 6, 6', an insulating film 14 and metallic wirings 4, 5 are formed, an SOS type device is completed. Thus, in a process of burying the insulating layer, by leaving the part thereof on an insular layer, a thick and high withstand voltage insulating film can be formed resulting in the great simplification of the process of the manufacture of a device.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an island-shaped semiconductor device provided on a transparent insulating substrate, for example, a semiconductor device using a silicon-on-sapphire substrate.

Semiconductor devices using semiconductor films on insulating substrates, such as silicon-on-sapphire (SOS) substrates, have perfect isolation between elements, no parasitic elements, and little parasitic capacitance, so they can achieve excellent characteristics. In particular, this is being applied to large-scale integrated circuits. These applications are, of course, circuits that require a low voltage power supply, that is, 5 to IOV, and do not require a high voltage insulating film exceeding, for example, 100V. By the way, silicon-on-sapphire type semiconductor devices are known to be excellent as integrated circuit elements for high-voltage operation for the reasons mentioned above, and integrated circuit semiconductor devices that operate at 150 to 500 V have been developed. . Such a semiconductor device naturally requires an insulating film with high breakdown voltage for elements and wiring.

In order to obtain an insulating film with high withstand voltage, it is sufficient to increase the thickness of the insulating film. When a so-called bulk silicon substrate is used, a thick and high-quality insulating oxide film can be easily obtained by oxidizing the substrate silicon for a long time, but in the case of an SOS substrate, a wholesaler is required. Figure 1 shows, as an example, a cross-sectional view of a high voltage capacitance element in which a thick oxide film is provided by directly oxidizing an SO8 substrate. is silicon oxide film, 4 and 5 are entire %h
It is. Silicon film 2 and gold IIJ4 are connected via insulating film 3.
A capacitance is formed between the SIL pole 4 and the SIL pole 4 . This - combination,
(1) The silicon layer on the SO8 substrate is generally 0.5 to 1μ
Since the silicon layer is about This results in disadvantages such as 7 in the figure, which causes deterioration of withstand voltage. Therefore, in order to obtain a thick insulating film in a 5osz semiconductor device, as shown in FIG.
It is common practice to provide the number n, 19. However, this requires a dedicated oxide film vapor phase growth process and a resist process in addition to the conventional process. In addition, LOCO & (mo method al Oxid-at
ion in 5ilicon) structure
In a semiconductor device, as shown in FIG. 4, a high voltage capacitance element has a three-layer electrode structure in which a polysilicon layer 6 is sandwiched between a silicon layer 2 and a total of five titan layers 5 via thick silicon oxide films 3 and 14. When attempting to obtain the same, there is a problem in that it is difficult to control the etching of the oxide film. In other words, when a thick oxide film 3 is deposited by a method such as vapor phase growth on an 808 substrate that already has a LOCO8 structure, and only the necessary parts are to be left, the oxide film 3 is etched on the LOCO8@formed oxide film. need to be terminated. However, it is difficult to accurately stop the layering of the fermentation film midway through.
This often resulted in overetching of the LOCO8 structure oxide film.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the problems in manufacturing the conventional SO8 type high voltage semiconductor device.

According to the present invention, it is possible to obtain an SOS@semiconductor device with #I structure including physical insulation, and at the same time, to obtain a thick insulating layer at a desired portion on a silicon layer with fewer manufacturing steps.

Of course, the present invention is applicable to the conventionally commonly used SO8
Traditional SO because it is completely compatible with technology
It can be easily applied to an 8-type semiconductor device. That is, according to the present invention, in manufacturing a semiconductor device having an insulating physical embedding layer between island-shaped elements on a transparent insulating substrate, a resist layer coated on a embedding insulating layer covering the island-shaped elements. A method for manufacturing a semiconductor device, characterized in that uniform exposure is carried out from the back side of the substrate and pattern exposure is carried out from the front side of the substrate to obtain the insulating physical layer and at the same time obtain an insulating film having a desired shape on the island-shaped element. is obtained.

The present invention will be explained in detail below using the drawings. Fifth
wJ(a), (b), , and (c) are diagrams for explaining the manufacturing process of the semiconductor device of the present invention, showing device cross sections in each main process using a high voltage capacitance device as an example. be. That is, in FIG. 5(a), 1.2
are the sapphire substrate and the silicon layer (assumed to be n+ doped), respectively, and 8 is the other transistor element 25. In the present invention, first, the island-shaped S
A buried insulator layer 3 having approximately the same thickness as the silicon layer is deposited over the entire surface of the O8 substrate by vapor deposition. Next, a resist □ mark 9 is applied over it. Next, uniform exposure 1o is applied to the entire substrate from the back side of the sapphire substrate.

In this case, the resist layer above the island-shaped silicon layers 2 and 8 is not exposed to light because the silicon layer blocks exposure. It is exposed to light that passes through it. Next, the photo master 11 selects the part from the substrate surface where a thick insulating film is to be left, and the resist is 9" thick.
Expose the part.

By developing this resist layer and etching the insulating layer using the resist as a mask, a cross-sectional shape as shown in FIG. 5 can be obtained. That is, the space between the island-like silicon layers 2, 8, etc. is filled flat with an insulating layer 3', and a thick insulating layer 3 is formed on the silicon layer 2 for providing a high voltage capacitance element. is left behind. Here, the resist may be exposed to light either uniformly from the back side or selectively from the front side. A gate oxide film 13 is formed on the substrate in the state shown in FIG. 5(b). Polysilicon layers 6, 6' are formed, and a thick insulating film 14. Once the metal wirings 4 and 5 are formed, an SO8 type semiconductor device having a cross-sectional structure as shown in FIG. 115(c) is completed. Here, the polysilicon layer 6 connected to the gold wiring 4 is covered with upper and lower thick insulating films 14.
and 3, it is sandwiched between gold gx electrode 5 and silicon layer 3 connected thereto, and a high breakdown voltage capacitance element is formed between the two. Such a capacitive element having a three-layer structure is particularly advantageous in the case of a high-voltage capacitive element that can obtain a small capacitance per unit area because a thick insulating film must be used. If a very large capacitance is not required, a high breakdown voltage capacitance element as shown in FIG. 3 can be obtained by subjecting the substrate shown in FIG. 5 to a gate oxidation process and a metal wiring process. In this case, the device electrode has two layers: a metal electrode 4 and a silicon layer 2. As described above, in the present SO8 type semiconductor device manufacturing method, a desired high voltage insulating film can be obtained, and at the same time, the entire island-like silicon layer on the 7-layer substrate is smoothed by the buried insulating layer 3'. They will be embedded so that they are on the same plane.

This structure has been conventionally referred to as a backfill method, and is known as a preferable structure useful for preventing wire breakage and side W1 leakage current peculiar to 808) transistors. That is, according to the manufacturing method of the present invention, during the step of providing an insulating physical embedding layer, a resist for the same step is also used, and a part of the embedding insulator layer is left as it is in the island-like silicon layer.
Since it is possible to obtain an insulating film that is thicker and therefore has a higher breakdown voltage, it can greatly contribute to the simplification of the manufacturing process. Needless to say, the high-voltage insulating film can be used not only for the capacitance element described in the embodiments but also for masking over high-voltage wiring using a polysilicon layer.

[Brief explanation of drawings]

FIG. 2 is a schematic cross-sectional view showing the structure of a high voltage capacitance element manufactured by a conventional manufacturing method, and FIG. Figure t44 is a schematic cross-sectional view showing the structure of a high voltage capacitance element obtained by the manufacturing method of the present invention, Figure 5(a),
(b) and (c) are device cross-sectional views at each main step for explaining the manufacturing method of the present invention, and in each figure, 1 is a transparent insulator substrate, 2 is a semiconductor layer, 3 is an insulator layer, 4 and 5 are metal electrode layers, 6 and 6' are other electrode layers, 7 is a constriction, 8 is a transistor element, 9 is a photoresist layer, 9' and 9'' are resist exposed areas, and 10 is a back side uniformly exposed ,
11 is a photomask, 12 is pattern exposure from the surface,
Reference numeral 13 indicates a gate oxide film, and reference numeral 14 indicates another insulating layer.

Claims (1)

[Claims] In manufacturing semiconductor devices that have an insulating physical embedding layer between island-shaped elements on a transparent insulating substrate, the resist layer coated on the embedding insulating layer covering the &-shaped elements is uniformly exposed from the back side of the substrate. A method for manufacturing a semiconductor device, comprising performing pattern exposure from the surface of the substrate to obtain the insulating physical layer and at the same time obtaining an insulating layer having a desired shape on the island-shaped element.