JPS5858777A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPS5858777A JPS5858777A JP56158548A JP15854881A JPS5858777A JP S5858777 A JPS5858777 A JP S5858777A JP 56158548 A JP56158548 A JP 56158548A JP 15854881 A JP15854881 A JP 15854881A JP S5858777 A JPS5858777 A JP S5858777A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- temperature
- film
- ohmic contact
- amorphous film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 229910052738 indium Inorganic materials 0.000 claims abstract description 6
- 229910052763 palladium Inorganic materials 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 claims description 6
- 229910001120 nichrome Inorganic materials 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 abstract description 5
- 229910052737 gold Inorganic materials 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract 2
- 238000006731 degradation reaction Methods 0.000 abstract 2
- 239000004615 ingredient Substances 0.000 abstract 2
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 239000012528 membrane Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000001000 micrograph Methods 0.000 description 2
- 206010037660 Pyrexia Diseases 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000008685 targeting Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 230000002087 whitening effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photovoltaic Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はケイ素を主成分とする非晶質膜を備え、この非
晶質膜にオーミックコンタクト部を形成している半導体
素子の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device including an amorphous film containing silicon as a main component, and in which an ohmic contact portion is formed in the amorphous film.
半導体素子の多くは半導体膜と金属とのオーミックコン
タクト部を有している。本発明は主成分がケイ素である
非晶質膜を用いた半導体素子におけるオーミックコンタ
クト部の改良に関し、オーミックコンタクトの特性を大
きく改善するとともにその劣化を防ぐ半導体素子の製造
方法を提供することを目的とする。Many semiconductor devices have an ohmic contact portion between a semiconductor film and a metal. The present invention relates to improvement of an ohmic contact portion in a semiconductor device using an amorphous film whose main component is silicon, and an object of the present invention is to provide a method for manufacturing a semiconductor device that greatly improves the characteristics of the ohmic contact and prevents its deterioration. shall be.
従来、非晶質ケイ素（以下ａ−３ｉ と略記する）膜
を備えた半導体素子において、前記非晶質ケイ素にオー
ミックコンタクトを有するＡｎ 電極を形成するにはＡ
２ を室温で真空蒸着することにより行なっていた。Conventionally, in a semiconductor device equipped with an amorphous silicon (hereinafter abbreviated as a-3i) film, the method of forming an electrode having an ohmic contact on the amorphous silicon is A.
2 was vacuum-deposited at room temperature.
しかし、電極形成後の素子保護の処理、製品組立工程に
おいてしばしば前記ＡＱ 電極のオーミックコンタクト
が劣化することがあった。例えばノ゛ンダ付けによって
他の回しまたは素ｆと接続する組立時に熱によってＡＱ
主電極白河する等の現象である。ＡＱ 電極が白河する
とａ−５ｉ 膜によつて形成された例えばダイオード等
の特性が劣化し、逆方向電流が増加したり、拡散ポテン
シャルが小さくなったり、直列抵抗が増加する等の現象
が生じる。However, the ohmic contact of the AQ electrode often deteriorates during element protection processing and product assembly processes after electrode formation. For example, when assembling to connect with other turns or elements by soldering, the AQ is caused by heat.
This is a phenomenon such as the main electrode whitening. When the AQ electrode becomes white, the characteristics of, for example, a diode formed by the a-5i film deteriorate, and phenomena such as an increase in reverse current, a decrease in diffusion potential, and an increase in series resistance occur.
第１図（ａ） 、 （ｂｌ） 、 （ｃ）の一連の顕微
鏡写真（倍率６００倍）はａ−３ｔ 膜上に室温で蒸着
したＡｆｆ電極を真空熱処理し、その後ＡＲ電極をとり
除いた部分のａ −Ｓｉ 表面の状態を示している。A series of micrographs (600x magnification) in Figures 1 (a), (bl), and (c) show the area where the Aff electrode was deposited on the a-3T film at room temperature and subjected to vacuum heat treatment, and then the AR electrode was removed. The state of the a-Si surface is shown.
これらの図より、熱処理温度が１７・０℃（第１図（ａ
））付近になると、コンタクト部の劣化を示すピット（
穴）が発生し、この温度付許でａ−３ｔとＡＱ 電極と
が相互作用を始めることがわかる。From these figures, the heat treatment temperature is 17.0°C (Fig. 1 (a)
)), pits (
It can be seen that a-3t and the AQ electrode begin to interact with each other at this temperature.
さらに、熱処理温度が１８６℃（第１図（ｂｌ）。Furthermore, the heat treatment temperature was 186°C (Fig. 1 (bl)).
２００℃（第１図（Ｃ））になるとピットが急激に増加
しコンタクト部の劣化が激しくなっていることがわかる
。It can be seen that when the temperature reached 200° C. (FIG. 1(C)), the number of pits increased rapidly and the contact portion deteriorated more severely.
ピットの発生により、コンタクト部の抵抗が増大し、オ
ーミック性が失なわれる。Due to the occurrence of pits, the resistance of the contact portion increases and ohmic properties are lost.
本発明は前述したように、ケイ素を主成分とする非晶質
膜とＡＱ醒極等によって形成するオーミックコンタクト
部における特性劣化を防ぐとともに、積極的にへρ等に
よる電極のオーミックコンタクト特性を改善させる半導
体素子の製造方法を提供するものである。As described above, the present invention prevents characteristic deterioration in the ohmic contact portion formed by an amorphous film mainly composed of silicon and AQ electrode, and actively improves the ohmic contact characteristic of the electrode due to ρ etc. The present invention provides a method for manufacturing a semiconductor device.
以下に本発明の半導体素子の製造方法の実施例について
説明する。Examples of the method for manufacturing a semiconductor device of the present invention will be described below.
（実施例１）
本実施例では主として熱処理を行なうことでａ−９ｉ
膜のシート抵抗にどのような変化が生じ、このａ−３ｉ
膜に形成した電極のオーミック特性にどのような影響
を及ぼすかを示す。(Example 1) In this example, a-9i was obtained by mainly performing heat treatment.
What changes occur in the sheet resistance of the film and this a-3i
This shows how the ohmic characteristics of the electrode formed on the film are affected.
表面を熱的に酸化させた単結晶Ｓｉ 基板上にｎ型ａ−
３ｉ 膜を以下の条件で堆積させた。容量結合型高周波
グロー放電装置で基板温度２ｏ○℃。N-type a-
3i films were deposited under the following conditions. The substrate temperature is 2°C using a capacitively coupled high frequency glow discharge device.
真空度Ｉ Ｔｏｒｒで５ＩＨ４を単結晶Ｓｉ基板上に分
解堆積させた。ａ−３ｉ のｎ型不純物としてＰＨ３
を用イ、Ｓ １Ｈ４Ｋ ７ｔ Ｌ Ｏ−４〜１ 、０
Ｖｏ ｌ ％ （体積百分率）混合させた。ａ−３ｉ
膜の膜厚は約１０００人である。これを化学的に選択エ
ツチング１．て島状のａ−８ｔ膜領域を作り、基板温度
２００℃で、プラズマＣＶＤ法によりシリコンチフ化膜
（ＳｉＮ膜）を堆積させ、コンタクトホールをあける。5IH4 was decomposed and deposited on a single crystal Si substrate under a vacuum degree of I Torr. PH3 as n-type impurity of a-3i
Using A, S 1H4K 7t L O-4~1, 0
Vol % (volume percentage) was mixed. a-3i
The thickness of the membrane is approximately 1000 people. Chemically selectively etching this 1. Then, an island-shaped A-8T film region is formed, a silicon nitride film (SiN film) is deposited by plasma CVD at a substrate temperature of 200° C., and a contact hole is formed.
その上に電極として用いる金属、例えばＡＮ、ＮｉＣｒ
、Ｐｔ 、Ｐｄ、Ｍｏ、Ｗ、Ｉｎ、Ａｕを蒸着させ、コ
ンタクト用のパターン出しをする。これを真空装置の付
いた電気炉に入れ、３０分間熱処理をした後、ＴＬＭ法
を用いてｎ型ａ−３ｉ 膜のシート抵抗を測定した。On top of that, a metal used as an electrode, such as AN, NiCr.
, Pt, Pd, Mo, W, In, and Au are vapor-deposited, and a contact pattern is formed. This was placed in an electric furnace equipped with a vacuum device and heat treated for 30 minutes, after which the sheet resistance of the n-type a-3i film was measured using the TLM method.
第２図は、ＴＬＭ法によってシート抵抗を測定する原理
および方法を示す図である。ａ−８ｌ膜１上に電極２ａ
、２ｂ、２ｃを蒸着する。電極２ａと２ｂとの距離Ｄ１
と、電極２ｂと２０との距離Ｄ２ とは一般に異な
らせている。可変電源４を変化させ、ある一定の電流Ｉ
が電％２ｂから電％２ａに流れる時の電圧をＶａｂ 、
同様に電極２ｂから電極２Ｃに流した時の電圧をＶｂｃ
とする。電流の流れる方向の切換は、電源３の切換スイ
ッチ４によって行なう。島状ａ−８ｉ 膜１の幅をＷと
するとａ′か＄１膜１のシート抵抗値Ｒ６は
で計算される。FIG. 2 is a diagram showing the principle and method of measuring sheet resistance by the TLM method. Electrode 2a on a-8l membrane 1
, 2b and 2c are deposited. Distance D1 between electrodes 2a and 2b
and the distance D2 between the electrodes 2b and 20 are generally different. By changing the variable power supply 4, a certain current I
The voltage when it flows from electric %2b to electric %2a is Vab,
Similarly, the voltage when flowing from electrode 2b to electrode 2C is Vbc
shall be. The direction of current flow is switched by a changeover switch 4 of the power supply 3. Letting the width of the island-like a-8i film 1 be W, the sheet resistance value R6 of the a' or $1 film 1 is calculated as follows.
第３図は、上記方法によって得られた測定結果を示すも
ので、熱処理温度（℃）を横軸にとり、ノート抵抗値（
Ω／口）を縦軸に取ってあり、熱処理温度の変化による
シート抵抗の変化を示す。同図において、代表例は電極
材料としてＮｉＣｒとＡＱを用いた場合を示す。１１は
ＮｉＣｒ ４極の場合を示し、１２ばＡｆｌ 電極の場
合の特性曲線を示している。ＡＲ主電極特性曲線１２の
場合、１７０℃付近で、ＡＲ主電極下ピットが発生する
ため、この付近でノート抵抗は増大しはじめるが、１７
０’Ｃ以下で熱処理をした場合にｊｄ熱処理をしない場
合よりシート抵抗（ｄ減少し、同時にコノタクト部のオ
ーミック性も良くなった７、なお、ａ−８ｉ 膜の堆
積温度が２ｏ○℃を越えると／−１・抵抗は増大した。Figure 3 shows the measurement results obtained by the above method, with the heat treatment temperature (°C) plotted on the horizontal axis and the note resistance value (
The vertical axis represents the change in sheet resistance due to change in heat treatment temperature. In the figure, a typical example shows a case where NiCr and AQ are used as electrode materials. 11 shows the characteristic curve for the NiCr 4-electrode, and 12 shows the characteristic curve for the Afl electrode. In the case of AR main electrode characteristic curve 12, a pit under the AR main electrode occurs at around 170°C, so the note resistance starts to increase around this area.
When heat treated at 0'C or lower, the sheet resistance (d) decreased compared to the case without heat treatment, and at the same time, the ohmic properties of the contact area also improved7. Note that the deposition temperature of the a-8i film exceeds 2o○C and/-1・Resistance increased.
以上の結果よりＡＱ を電極として用いた場合、１７０
℃までの熱処理を行なうことによりノート抵抗は下がり
続け、約半分に１で下降してシート抵抗特性が改善され
た。１７０℃以上の熱を加えるとピットがａ−３ｔ
膜とＡｆｆｉ 電極との間に発生し、しかもａ−８ｔ
膜のシート抵抗が増大することがわかった。Ａｆｌ以外
の電極材料で、ａ−８ｉと熱的に相互作用が起こりやす
い金属、例えばＰｔ、Ｐｄ、Ｉｎ、Ａｕ も多少の温
度差はあるもののピットが発生する温度より低い温度の
熱処理によってシート抵抗は減少することが確かめられ
た。From the above results, when AQ is used as an electrode, 170
By performing the heat treatment up to .degree. C., the note resistance continued to decrease, decreasing by about half by 1, and the sheet resistance characteristics were improved. When heat is applied above 170℃, the pit becomes a-3t.
occurs between the membrane and Affi electrode, and a-8t
It was found that the sheet resistance of the membrane increases. Electrode materials other than Afl, such as metals that tend to thermally interact with a-8i, such as Pt, Pd, In, and Au, can also have sheet resistance by heat treatment at a temperature lower than the temperature at which pits occur, although there is a slight temperature difference. was confirmed to decrease.
すなわち、Ａｎ、Ｐｔ、Ｐｄ、Ｉｎ、Ａｕ のいずれか
よりなる電極を蒸着により非晶質膜上に形成した場合に
は、１７０℃以下の温度で熱処理することにより、オー
ミックコンタクト部の特性を良好にでき、しかも劣化を
防止できることになる。なお、熱処理温度は、あまり低
くても効果が少なく、１００℃以上にすることが望まし
い。In other words, when an electrode made of An, Pt, Pd, In, or Au is formed on an amorphous film by vapor deposition, the characteristics of the ohmic contact part can be improved by heat treatment at a temperature of 170°C or less. This means that deterioration can be prevented. Note that even if the heat treatment temperature is too low, the effect will be small, so it is desirable to set the heat treatment temperature to 100° C. or higher.
以上はＡＭ、Ｐｔ 、Ｐｄ、 Ｉｎ、Ａｕ の各電極
に対する熱処理の効果であるがＮｉＣｒ 、Ｗ、Ｍｏ
、Ｎｉ 、Ｃｒ ｆ：ａ −８ｉ膜の電極とした場合に
は、異なる現象が観測された。The above is the effect of heat treatment on AM, Pt, Pd, In, and Au electrodes, but NiCr, W, and Mo
, Ni, Cr f:a-8i film electrodes, a different phenomenon was observed.
すなわち、例えばＮｉＣｒを電極として用いた場合には
、第３図の特性曲＠１１に示すように、２００℃１でシ
ート抵抗が減少し続けた。熱処理温度が２０ｏ℃以上を
越えると、シート抵抗値がきわめて不規則に変化し、測
定がふらつき正常な測定が困難になった（第３図で特性
曲線１１に関して２００℃以上のＲｓ の正確な測定は
困難となり記入していない。）。That is, when NiCr was used as the electrode, for example, the sheet resistance continued to decrease at 200° C.1, as shown in characteristic curve @11 in FIG. When the heat treatment temperature exceeded 20oC, the sheet resistance value changed extremely irregularly, causing the measurement to fluctuate, making it difficult to make normal measurements. (I did not write it down because it was difficult.)
この原因は、必ずしも明らかでないが、２ｏ。The cause of this is not necessarily clear, but 2o.
℃という温、度がａ−８ｉ 膜を基板上に堆積するとき
の堆積ｄ（一致し、この温度以上になるとａ−３ｉ膜の
組成が変化し始めることによると思われる。It is thought that this is because the temperature of 0.degree. C. corresponds to the deposition rate d when an a-8i film is deposited on a substrate, and above this temperature the composition of the a-3i film begins to change.
とにかく、Ｎｉ Ｃｒ 、 Ｗ 、 Ｍｏ 、Ｎｉ 、
Ｃｒをａ−３ｔ膜の電極とする場合には、コンタクト部
の抵抗は、ａ−３ｔ 膜の堆積時の基板温度になるまで
低下し続け、オーミック性が向上した。
・１（実施例２）
次に太陽電池を対象とした実施例について述べる。この
太陽電池の構造はガラス板に透明電極を蒸着した上に順
にｐ、ｉ、ｎ型のａ−８ｉ 膜を堆積し、さらにとのａ
−Ｓｔに金属電極を形成したものである。Anyway, Ni Cr, W, Mo, Ni,
When Cr was used as the electrode of the a-3t film, the resistance of the contact portion continued to decrease until the substrate temperature reached the temperature at which the a-3t film was deposited, and the ohmic properties improved.
-1 (Example 2) Next, an example targeting a solar cell will be described. The structure of this solar cell is that a transparent electrode is deposited on a glass plate, p-, i-, and n-type a-8i films are deposited in this order, and then a
-St with a metal electrode formed thereon.
本実施例では、前記ｎ型のａ−８ｉ 膜と金属電極（こ
こではＡｆｉ電極）とのコンタクト部が太陽電池の特性
に与えるえいきょうを調べるため、次のようなサンプル
Ａ、Ｂ、Ｃを用意した。In this example, the following samples A, B, and C were used to investigate the effect that the contact portion between the n-type a-8i film and the metal electrode (here, the Afi electrode) has on the characteristics of the solar cell. Prepared.
すなわち、サンプルＡは前記ＡＮ 電極を有する太陽電
池を熱処理しないもの、サンプルＢは２００℃付近まで
過度の熱処理した太陽電池、サンプルＣは、本発明に係
るもので真空中で１３０℃の適温で熱処理した太陽電池
である。That is, sample A is a solar cell having the AN electrode that is not heat-treated, sample B is a solar cell that has been excessively heat-treated to around 200°C, and sample C is a solar cell according to the present invention that has been heat-treated at an appropriate temperature of 130°C in vacuum. This is a solar cell.
これらのサンプルＡ、Ｂ、Ｃのソーラシミュレ−シｇ
７ Ａ Ｍ １ （１００ｍＷ／ＣＪ） 照射下テノそ
レソれの特性を次表に示す。Solar simulation of these samples A, B, and C
The characteristics of the tenosoreso under 7 A M 1 (100 mW/CJ) irradiation are shown in the following table.
表：各サンプルの熱処理の違いによる素子特性の比較表
に示したとおり短絡電流ＪｓｃはすべてのサンプルＡ−
Ｃにわたってほぼ同じであるが、開放電圧ｖＯＣおよび
曲線因子Ｆ、Ｆ、 はサンプルＢの場合は大幅に減少
し、効率は３近くにまで減少した。もっとも特性の良い
太陽電池は、本発明に係るサンプルＣであった。Table: Comparison of device characteristics due to differences in heat treatment of each sample As shown in the table, the short circuit current Jsc of all samples A-
Although nearly the same across C, the open circuit voltage vOC and fill factor F, F, were significantly reduced for sample B, and the efficiency was reduced to close to 3. The solar cell with the best characteristics was Sample C according to the present invention.
以上説明したように本発明の半導体素子の製造方法はオ
ーミックコンタクトの劣化を未然に防ぐことができると
ともに、さらにシート抵抗を減少でき、そのためオーミ
ックコンタクトが改善され、ａ−６ｉ太陽電池に適用し
た場合には効率を改善することができる等の利点を有し
、工業的に極めて有意義である。As explained above, the method for manufacturing a semiconductor device of the present invention can prevent deterioration of ohmic contacts and further reduce sheet resistance, thereby improving ohmic contacts, and when applied to A-6I solar cells. It has advantages such as improved efficiency and is extremely meaningful industrially.
第１図（ａ１〜＜ＣＩは各温度の熱処理による非晶質ケ
イ素とＡＮとの相互拡散の様子を示す顕微鏡写真（倍率
５００倍）、第２図は非晶質ケイ素のシート抵抗を測定
する方法を示した図、第３図は本発明の半導体装置の製
造方法によって得られた素子の熱処理温度によるシート
抵抗の変化を示す特性図である。
１・・・―・・非晶質シリコン膜、２ａ、２ｂ、２ｃ・
・・・・・電極、３・・・・・・電源、４・・・・・・
切換スイッチ。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名巷閂
昭５＋ニー５８’／ン“バ４）
第２図
３図
軌ｇ理ｚ２蔓度（・Ｃ）Figure 1 (a1~<CI is a micrograph (500x magnification) showing the state of interdiffusion between amorphous silicon and AN due to heat treatment at various temperatures; Figure 2 is a measurement of the sheet resistance of amorphous silicon. FIG. 3, which is a diagram showing the method, is a characteristic diagram showing changes in sheet resistance depending on heat treatment temperature of an element obtained by the method for manufacturing a semiconductor device of the present invention. 1...Amorphous silicon film , 2a, 2b, 2c・
...Electrode, 3...Power supply, 4...
Changeover switch. Name of agent Patent attorney Toshio Nakao and 1 other person Akira 5+Knee 58'/N'ba 4)
Claims (3)
ｔ。 Ｐｄ、Ｉｎ、Ａｕのいずれかよりなる金属層を形成した
後、１７０℃以下の温度で熱処理することを特徴とする
半導体素子の製造方法。(1) AQ, P on an amorphous film mainly composed of silicon.
t. 1. A method for manufacturing a semiconductor device, which comprises forming a metal layer made of Pd, In, or Au, and then heat-treating the layer at a temperature of 170° C. or lower.
ことを特徴とする特許請求の範囲第１項記載の半導体素
子の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the temperature of the heat treatment is 100°C or more and 170°C or less.
イ素を主成分とする非晶質膜を形成し、前記非晶質膜上
にＷ 、 Ｍｏ 、Ｎｉ 、Ｃｒ 、ＮｉＣｒのいずれ
かよりなる金属層を形成し、前記金属層が形成これた非
晶質膜を前記基板上への前記非晶質膜の形成時の温度以
下で熱処理することを特徴とする半導体素子の製造方法
。(3) An amorphous film containing silicon as a main component is formed on the substrate while the substrate is heated to a predetermined temperature, and a film made of W, Mo, Ni, Cr, or NiCr is formed on the amorphous film. 1. A method of manufacturing a semiconductor device, comprising: forming a metal layer, and heat-treating the amorphous film on which the metal layer has been formed at a temperature lower than the temperature at which the amorphous film is formed on the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56158548A JPS5858777A (en) | 1981-10-05 | 1981-10-05 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56158548A JPS5858777A (en) | 1981-10-05 | 1981-10-05 | Manufacture of semiconductor element |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62003546A Division JPS62169372A (en) | 1987-01-09 | 1987-01-09 | Manufacture of semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5858777A true JPS5858777A (en) | 1983-04-07 |
| JPS6249753B2 JPS6249753B2 (en) | 1987-10-21 |
Family
ID=15674109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56158548A Granted JPS5858777A (en) | 1981-10-05 | 1981-10-05 | Manufacture of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5858777A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59224182A (en) * | 1983-06-03 | 1984-12-17 | Hitachi Ltd | Thin film semiconductor device |
| JPS60211879A (en) * | 1984-04-05 | 1985-10-24 | Semiconductor Energy Lab Co Ltd | Manufacture of semiconductor device |
| JPS60211817A (en) * | 1984-04-05 | 1985-10-24 | Semiconductor Energy Lab Co Ltd | Apparatus for photoelectric conversion |
| JPS60211880A (en) * | 1984-04-05 | 1985-10-24 | Semiconductor Energy Lab Co Ltd | Manufacture of photoelectric conversion device |
| JPS6126268A (en) * | 1984-07-16 | 1986-02-05 | Kanegafuchi Chem Ind Co Ltd | Heat-resistant amorphous silicon solar cell and manufacture thereof |
| JPS6191973A (en) * | 1984-10-11 | 1986-05-10 | Kanegafuchi Chem Ind Co Ltd | Heat resisting thin film photoelectric conversion element and manufacture thereof |
| JPS61144885A (en) * | 1984-12-18 | 1986-07-02 | Kanegafuchi Chem Ind Co Ltd | Heatproof, thin film optoelectric transducer and production thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55123178A (en) * | 1979-03-16 | 1980-09-22 | Sanyo Electric Co Ltd | Solar cell |
| JPS5669874A (en) * | 1979-11-13 | 1981-06-11 | Fuji Electric Co Ltd | Amorphous semiconductor solar cell |
| JPS6246076A (en) * | 1985-08-21 | 1987-02-27 | 日本鋼管株式会社 | Method of reducing friction resistance of buried removing pipe |
-
1981
- 1981-10-05 JP JP56158548A patent/JPS5858777A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55123178A (en) * | 1979-03-16 | 1980-09-22 | Sanyo Electric Co Ltd | Solar cell |
| JPS5669874A (en) * | 1979-11-13 | 1981-06-11 | Fuji Electric Co Ltd | Amorphous semiconductor solar cell |
| JPS6246076A (en) * | 1985-08-21 | 1987-02-27 | 日本鋼管株式会社 | Method of reducing friction resistance of buried removing pipe |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59224182A (en) * | 1983-06-03 | 1984-12-17 | Hitachi Ltd | Thin film semiconductor device |
| JPS60211879A (en) * | 1984-04-05 | 1985-10-24 | Semiconductor Energy Lab Co Ltd | Manufacture of semiconductor device |
| JPS60211817A (en) * | 1984-04-05 | 1985-10-24 | Semiconductor Energy Lab Co Ltd | Apparatus for photoelectric conversion |
| JPS60211880A (en) * | 1984-04-05 | 1985-10-24 | Semiconductor Energy Lab Co Ltd | Manufacture of photoelectric conversion device |
| JPS6126268A (en) * | 1984-07-16 | 1986-02-05 | Kanegafuchi Chem Ind Co Ltd | Heat-resistant amorphous silicon solar cell and manufacture thereof |
| JPS6191973A (en) * | 1984-10-11 | 1986-05-10 | Kanegafuchi Chem Ind Co Ltd | Heat resisting thin film photoelectric conversion element and manufacture thereof |
| JPS61144885A (en) * | 1984-12-18 | 1986-07-02 | Kanegafuchi Chem Ind Co Ltd | Heatproof, thin film optoelectric transducer and production thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6249753B2 (en) | 1987-10-21 |
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