JPS59224182A - Thin film semiconductor device - Google Patents
Thin film semiconductor deviceInfo
- Publication number
- JPS59224182A JPS59224182A JP58097784A JP9778483A JPS59224182A JP S59224182 A JPS59224182 A JP S59224182A JP 58097784 A JP58097784 A JP 58097784A JP 9778483 A JP9778483 A JP 9778483A JP S59224182 A JPS59224182 A JP S59224182A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- thin film
- semiconductor device
- amorphous silicon
- film semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000010409 thin film Substances 0.000 title claims 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000004020 conductor Substances 0.000 claims description 6
- 150000003376 silicon Chemical class 0.000 abstract description 17
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 8
- 239000011521 glass Substances 0.000 abstract description 3
- 230000002542 deteriorative effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 58
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 238000010438 heat treatment Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 229910052789 astatine Inorganic materials 0.000 description 5
- 239000007789 gas Substances 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 3
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910001120 nichrome Inorganic materials 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- -1 Cr-AL Substances 0.000 description 1
- 229910019590 Cr-N Inorganic materials 0.000 description 1
- 229910019588 Cr—N Inorganic materials 0.000 description 1
- 235000004311 Dacryodes edulis Nutrition 0.000 description 1
- 244000022759 Dacryodes edulis Species 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001017 electron-beam sputter deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type
- H01L31/1055—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type the devices comprising amorphous materials of Group IV of the Periodic System
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は非晶質シリコンを用いたダイオードに関するも
のである。特にその耐熱性を向上させるものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a diode using amorphous silicon. In particular, it improves its heat resistance.
従来、水素化非晶質シリコンを用いたｐｉｎダイオード
は第１図に示すような構造をしている。Conventionally, a pin diode using hydrogenated amorphous silicon has a structure as shown in FIG.
１は基板、２は下部電極、３はｐを添加したｎ形水素化
非晶質シリコン層（ｎ層）、４は不純物をドーグしない
水素化非晶質シリコン層（ｉ層）、５はＢｆ：添加した
ｐ形水素化非晶質シリコン層（ｐ層）、６は上部′電極
である。ｎ層、ｉ層、ｐ層の順序はこれと反対の場合も
ある。２，６の電極金属としてはｎ形あるいはｐ膨水素
化非晶質シリコンと良好なオーム性接触を示す事が要求
される。また、このダイオードを一次元あるいは二次元
に配列して形成するためには電極が結晶シリコ７ＩＣ，
ＬＳＩと同様にホトエツチング工程で容易にパターン化
できる事も要求される。これらの要求を満たす金属とし
てＡｔ、 Ｃｒ 、 Ｎ ｉ 。1 is a substrate, 2 is a lower electrode, 3 is an n-type hydrogenated amorphous silicon layer doped with p (n layer), 4 is a hydrogenated amorphous silicon layer (i layer) that does not contain impurities, and 5 is Bf : Added p-type hydrogenated amorphous silicon layer (p layer), 6 is the upper electrode. The order of the n-layer, i-layer, and p-layer may be reversed. The electrode metals 2 and 6 are required to exhibit good ohmic contact with n-type or p-swelled hydrogenated amorphous silicon. In addition, in order to form these diodes in a one-dimensional or two-dimensional array, the electrodes must be made of crystalline silicon 7IC,
Similar to LSI, it is also required that it can be easily patterned by a photoetching process. At, Cr, and Ni are metals that meet these requirements.
ＮｉＣｒ、Ｍｏ、Ｔａなどが良く知られている。このな
かでは下記の性徴を持つＡ７が広く用いられてきた。（
１）水素化非晶質シリコン層に及ぼす応力が小さいので
厚く堆積可能である。（２）そのため抵抗が小さくでき
る。（３）抵抗加熱蒸着法・電子ビーム蒸着法、スパッ
タリングなど種々の方法で容易に堆積可能である。（４
）ＳｉＩＣプロセスで用いられており、加工が容易であ
る。しか、Ｌ、ｌ５ｂｉｈａｒａらがＪ、Ａｐｐｌ、
Ｐｈｙｓ、、 ｖｏｌ、 ５３．Ａ ５ ｐｐ。NiCr, Mo, Ta, etc. are well known. Among these, A7, which has the following sexual characteristics, has been widely used. (
1) Since the stress exerted on the hydrogenated amorphous silicon layer is small, it can be deposited thickly. (2) Therefore, resistance can be reduced. (3) It can be easily deposited by various methods such as resistance heating evaporation, electron beam evaporation, and sputtering. (4
) It is used in the SiIC process and is easy to process. However, L,l5bihara et al. J,Appl.
Phys., vol. 53. A 5pp.
３９０９〜３９１１． Ｍａｙ’ ８２．において、示
したようにＡＡは非晶質シリコン層と２００Ｃ程度の低
温で容易に反応し、ＡｔとＳｉ原子が相互拡散をおこす
。これはｐｉｎダイオードにおいては接合を破壊する原
因となる。よって電極金属にＡｔを用いた場合には電極
形成後は２００Ｃ程度以上の温度にする事ができず、素
子の耐熱性が悪い。3909-3911. May' 82. As shown in , AA easily reacts with the amorphous silicon layer at a low temperature of about 200 C, and At and Si atoms interdifuse. This causes breakdown of the junction in the pin diode. Therefore, when At is used as the electrode metal, the temperature cannot be raised to about 200 C or higher after the electrode is formed, and the heat resistance of the element is poor.
と同時に、−次元ないし二次元センサなどにこのｐｉｎ
ダイオードを用いる場合、これ以後の堆積、加工プロセ
スに制限が加わる事になる。At the same time, connect this pin to a -dimensional or two-dimensional sensor, etc.
If a diode is used, restrictions will be placed on subsequent deposition and processing processes.
本発明の目的は従来のＡｔ電極を有する非晶質シリコン
・ダイオードが有していたこの欠点をな−くし、耐熱性
が良好でかつ電極抵抗の小さなダイオードを提供するも
のである。The object of the present invention is to eliminate this drawback of conventional amorphous silicon diodes having At electrodes, and to provide a diode with good heat resistance and low electrode resistance.
本発明は非晶質シリコン層とその上部に設けた導電体層
と接触を取る場合、非晶質シリコン層に接してはＣｒ層
を用いることを特徴とするものである。半導体層上に金
属層を設ける場合、応力の半導体層におよぼす影響が問
題となるが、この点は当該金属層を多層膜として問題の
解決をはかるものである。以下、詳細に本発明を説明す
る。The present invention is characterized in that a Cr layer is used in contact with the amorphous silicon layer when contact is made between the amorphous silicon layer and the conductor layer provided on the amorphous silicon layer. When a metal layer is provided on a semiconductor layer, the influence of stress on the semiconductor layer becomes a problem, but this problem is solved by forming the metal layer into a multilayer film. The present invention will be explained in detail below.
Ａ４とＳｉの相互拡散については結晶シリコンＩＣの分
野ではよく知られている。しかし、非晶質水素化シリコ
ンとＡ４の場合にはその様子が異なっている。最も大き
な違いは結晶ＳｉとＡｔの反応が４００Ｃ以上の高温で
おきるのに対し、非晶質水素化シリコンとＡＡの場合に
は２００Ｃ程度の低温でおきる点である。第１図のよう
な構造のｐｉｎダイオードにおいては約２０００以上の
温度でＡｔ電極６とｐ形弁晶質水素化シリコン層５が反
応・相互拡散し、ついにはＡ４がｐ層をつきぬけ、１層
４内部にまで達する。第２図はＩＭＡによる深さ方向の
分析結果の一例である。Ａ７の膜厚は約１μｍ１非晶質
水素化シリコン層の厚みは９層０．０２３μｍ、 ｉ層
０．５５μｍ、ｎ層０．０３μｍで２００Ｃで１４時間
アニールした素子の表面のｋｔを除いた試料について示
す。このようにＡ４はポロンが添加されたｐ層（曲線９
の範囲）をつきぬけ、０．０５μｍ程度ｉ層内部にまで
はいシこんでいる。７，８．９はＳｒ、ＡＬ、Ｂの信号
強度である。各信号の大きさの関係は任意となっている
。Interdiffusion of A4 and Si is well known in the field of crystalline silicon ICs. However, the situation is different between amorphous hydrogenated silicon and A4. The biggest difference is that the reaction between crystalline Si and At occurs at a high temperature of 400C or higher, whereas the reaction between amorphous silicon hydride and AA occurs at a low temperature of about 200C. In the pin diode with the structure shown in Fig. 1, the At electrode 6 and the p-type crystalline hydrogenated silicon layer 5 react and interdiffuse at a temperature of about 2000°C or higher, and eventually A4 penetrates the p layer, forming a single layer. 4 Reaches inside. FIG. 2 is an example of the results of analysis in the depth direction by IMA. The film thickness of A7 is approximately 1 μm1 The thickness of the amorphous hydrogenated silicon layer is 9 layers 0.023 μm, the i layer 0.55 μm, the n layer 0.03 μm, and the kt on the surface of the device was removed at 200 C for 14 hours. Show about. In this way, A4 has a p-layer doped with poron (curve 9
) and penetrates into the i-layer by about 0.05 μm. 7, 8.9 are the signal intensities of Sr, AL, and B. The relationship between the magnitudes of each signal is arbitrary.
第３図はｐｉｎダイオードの２００Ｃ熱処理による逆方
向電流の増加の様子を示した図である。FIG. 3 is a diagram showing how the reverse current increases due to the 200C heat treatment of the pin diode.
１ｏ、１１，１２はＡ４膜厚１．８ 、１．０ 、０．
４μｍの場合を示す。Ａ７膜厚が厚いほど劣化の速鷹は
太きい。これはＡＡとＳｉの相互拡散がＡｔの量、即ち
膜厚によって律速されているためである。1o, 11, 12 are A4 film thickness 1.8, 1.0, 0.
The case of 4 μm is shown. The thicker the A7 film, the faster the rate of deterioration. This is because the mutual diffusion of AA and Si is rate-limited by the amount of At, ie, the film thickness.
このような現象はｐ層とＡｔばかりでなく、０層゛とＡ
Ａの場合にも見られる。ｐ層の方が化学的に安定である
ため、ｎ層とＡ４の場合の方が速く劣化する。第４図は
第３図のｐｉｎダイオードと逆に基板側からｐ層−１層
−ｎ層の順に形成し、ｎ層の厚みを第３図のダイオード
のｐ層と等しくした場合について示したものである。ｎ
層とＡｔの反応の方がすみやかに進行する事が判る。This phenomenon occurs not only in the p layer and At, but also in the 0 layer and A.
This can also be seen in the case of A. Since the p-layer is chemically more stable, the n-layer and A4 deteriorate faster. Figure 4 shows a case in which, contrary to the pin diode in Figure 3, the p layer, layer 1, and layer n are formed in this order from the substrate side, and the thickness of the n layer is made equal to the p layer of the diode in Figure 3. It is. n
It can be seen that the reaction between the layer and At proceeds more quickly.
以上のようにＡｔを上部電極とした素子では２００Ｃ程
度の熱処理によって容易に劣化してしまう。これに対し
、Ｃｒと非晶質水素化シリコンとは様子が異なる事を発
見した。Ｃｒも非晶質水素化シリコンと反応はする。非
晶質水素化シリコンの上に基板温度１００Ｃ以上に加熱
してＣｒあるいはＣｒ−Ａｔ、Ｃｒ−Ｎｉ、 Ｃｒ−Ｎ
ｉＣｒ−Ａ ｕ 、 Ｃｒ Ｎ ｆ Ａ ｕなど（
Ｃｒ−Ａｔ等の表示ＩｄＣｒ層とＡｔ層の二層の重ね層
をあられしている。以下同様の表示は同様の意味をあら
れしている。）を蒸着法あるいはスパッタリング法で堆
積するか、または基板加熱温度がこれ以下でも金属を堆
積後に１００Ｃ以上で加熱処理した後、この金属を除去
すると非晶質水素化シリコン表面にＣｒとの反応物が残
る。この反応物は非晶質水素化シリコン層より低抵抗で
１０に０７口以下である。しかもＡＡと非晶質水素化シ
リコンの場合には場所的に不均一に反応するが、Ｃｒと
非晶質水素化シリコンの場合には膜全面で均一に反応す
る。この反応のためｐｉｎダイオードの逆方向電流は熱
処理によって若干増加するが、２００ｔ：’程度では破
壊するには至らないものと考えられる。As described above, an element using At as an upper electrode is easily deteriorated by heat treatment at about 200C. On the other hand, it was discovered that Cr and amorphous hydrogenated silicon behave differently. Cr also reacts with amorphous hydrogenated silicon. Cr, Cr-At, Cr-Ni, Cr-N is deposited on amorphous hydrogenated silicon by heating the substrate to a temperature of 100C or higher.
iCr-Au, CrNfAu, etc. (
Two overlapping layers of a display IdCr layer and an At layer such as Cr-At are used. Below, similar expressions have the same meanings. ) is deposited by evaporation or sputtering, or even if the substrate heating temperature is lower than this, if the metal is deposited and then heated at 100C or higher and then this metal is removed, a reaction product with Cr will be formed on the surface of the amorphous silicon hydride. remains. This reactant has a lower resistance than the amorphous hydrogenated silicon layer, less than 10 times lower. Moreover, in the case of AA and amorphous hydrogenated silicon, the reaction occurs unevenly locally, but in the case of Cr and amorphous hydrogenated silicon, the reaction occurs uniformly over the entire surface of the film. Due to this reaction, the reverse current of the PIN diode increases slightly due to the heat treatment, but it is considered that this does not lead to destruction at about 200 t:'.
しかしながら、Ｃｒ膜は非晶質水素化シリコン層に及ぼ
す応力が大きく、厚く堆積すると加工時に非晶質水素化
シリコンを剥離させてしまう。このため、ダイオードの
直列抵抗を低減するためには電極を多層構造とする必要
があシ、この例としてはＣｒ−Ａｊａ、Ｃｒ−Ｎｉ−Ａ
ｕ、Ｃｒ−ＮｉＣｒ −Ａｕなどが考えられる。Ｃｒ
膜の膜厚は５００人〜２０００人程以上用いている。Ｃ
ｒ膜上に積層する金属膜の膜厚は非晶質シリコン層への
応力を考慮して設定される。However, the Cr film exerts a large stress on the amorphous hydrogenated silicon layer, and if it is deposited thickly, the amorphous hydrogenated silicon layer will be peeled off during processing. Therefore, in order to reduce the series resistance of the diode, it is necessary to make the electrode a multilayer structure. Examples of this are Cr-Aja, Cr-Ni-A
Possible examples include u, Cr-NiCr-Au, and the like. Cr
The thickness of the membrane used is approximately 500 to 2000 or more. C
The thickness of the metal film laminated on the r film is set in consideration of stress on the amorphous silicon layer.
下部電極についても同様な現象が起こるが、下部電極を
多層構造とする場合には基板との接着性が問題となって
くる。基板をガラスにする場合にはＣｒ−ＡＬ、 Ｃｒ
−Ｎｉ−Ａｕ、 Ｃｒ−ＮｉＣｒ−Ａ ｕ等Ａ４やＡｕ
が基板面と接触する構造は接着性が十分でなく、Ｃｒ、
ＮｉＣｒ、Ｍｏ、Ｔａあるいはこれらの組み合わせた多
層構造などがより現実的である。A similar phenomenon occurs with the lower electrode, but when the lower electrode has a multilayer structure, adhesion to the substrate becomes a problem. When the substrate is made of glass, Cr-AL, Cr
-Ni-Au, Cr-NiCr-A u etc. A4 and Au
The structure in which Cr,
A multilayer structure of NiCr, Mo, Ta, or a combination of these is more realistic.
し発明の実施例〕
実施例１
第５図のようにガラス基板１の上にＣｒ電極２を膜厚０
．３μｍ形成する。その上、にプラズマＣＶＤ（Ｃｈｅ
ｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ
）法で基板温度２３０ＣでＰＨ，ガスとＳｉＨ４ガス
とを混合したガスを用いて（混合比ＰＨ８／８ｉＨ４≧
０．５体積％）Ｐを含んだ非晶質水素化シリコン層（ｎ
層）３を、次にＳｉＨ４ガスのみで非晶質水素ＳｔＨ，
と全混合したガスを用いて（混合比Ｂ２）１゜へ
／ＳｉＨ，≧０．５体積％）Ｂを含んだ非晶質水素化シ
リコン層（ｐ層）５を順次形成する。各層の膜厚は例え
ば０層３００人、１層５５００人、９層２３０人である
。次にこの上にＣｒ１３を０．１μｍ１その上にＡｔ１
４を１μｍ蒸着で形成する。Embodiments of the invention] Example 1 As shown in FIG.
．． Form 3 μm. Moreover, plasma CVD (Che
Mical Vapor Deposition
) method at a substrate temperature of 230C using a mixture of PH gas and SiH4 gas (mixture ratio PH8/8iH4≧
An amorphous hydrogenated silicon layer containing P (0.5% by volume) (n
layer) 3, then amorphous hydrogen StH using only SiH4 gas,
An amorphous silicon hydride layer (p layer) 5 containing B (mixture ratio B2) to 1°/SiH, 0.5% by volume) is sequentially formed using a gas completely mixed with (mixing ratio B2). The film thickness of each layer is, for example, 300 people for the 0th layer, 5500 people for the 1st layer, and 230 people for the 9th layer. Next, apply Cr13 to 0.1 μm1 on top of this and At1 on top of this.
4 is formed by vapor deposition to a thickness of 1 μm.
この時の電流電圧特性はＡｔ１μｍのみの場合とほとん
ど差がなく、電極抵抗が低い事を示している。このダイ
オードを２００Ｃ空気中で熱処理すると第６図に示すよ
うに逆方向電流は時間の経過と共に若干増加するが、約
１０時間程度で飽和する。これはＣｒと非晶質水素化シ
リコン層の拡散がある程度で進行しなくなるためと考え
られる。The current-voltage characteristics at this time have almost no difference from the case of At 1 μm only, indicating that the electrode resistance is low. When this diode is heat treated in air at 200C, the reverse current increases slightly over time, as shown in FIG. 6, but saturates in about 10 hours. This is considered to be because the diffusion of Cr and the amorphous hydrogenated silicon layer stops progressing to a certain extent.
また、Ｃｒの膜厚に関しては２０００人程度以上では応
力が太きく、作製した時点で破壊するものが多いが、こ
れよシ薄い膜厚では大きな差は認められない。Ｃｒ膜は
均一な膜の形成が可能な４００人〜５００人程以上れば
効果を奏し得る。Regarding the film thickness of Cr, the stress is large when there are more than 2,000 people, and many of them break at the time of fabrication, but no big difference is observed when the film thickness is thinner than this. The Cr film can be effective if about 400 to 500 people or more can form a uniform film.
実施例２
実施例１のＣｒ−Ａｔの積層のかわりにＣｒ０．１μ”
Ｉ Ｎ Ｉ Ｏ−１１’ ｍｒ Ａ ｕＯ−２１’
ｍを電子ビーム蒸着で堆積する。他の状態は実施例１と
同様である。電流電圧特性、耐熱性共にＣｒ−ＡＡの積
層の場合とほぼ等しい。Example 2 Cr0.1μ" instead of the Cr-At lamination of Example 1
I N I O-11' mr A uO-21'
m is deposited by electron beam evaporation. Other conditions are the same as in the first embodiment. Both current-voltage characteristics and heat resistance are almost the same as in the case of a Cr-AA lamination.
実施例３ 実施例１のＣｒ−ＡＡのかわシにＣｒ０．１μｍ。Example 3 Cr0.1 μm was added to the Cr-AA liner of Example 1.
ＮｉＣｒ０．３μｍ、ＡｕＯ，２μｍをスパッタリング
で堆積する。他の状態は実施例１と同様である。0.3 μm of NiCr and 2 μm of AuO are deposited by sputtering. Other conditions are the same as in the first embodiment.
電流電圧特性、耐熱性共にＣｒ−Ａｔの積層の場合とほ
ぼ等しい。Both current-voltage characteristics and heat resistance are almost the same as in the case of a Cr-At stack.
以上の実施例に示したように、本発明によれば非晶質水
素化シリコンルミｎダイオードの耐熱性の向上を電気的
特性の劣化なく実現できるので非晶質水素化シリコンを
用いた一次元・二次元の受光素子の信頼性を向上させる
事ができる。As shown in the above embodiments, according to the present invention, it is possible to improve the heat resistance of an amorphous hydrogenated silicon-luminium diode without deteriorating its electrical characteristics.・The reliability of two-dimensional light receiving elements can be improved.
第１図は従来の非晶質水素化シリコンルミｎダイオード
の断面図、第２図は非晶質シリコン層の金属と接触する
面側のＨＭＡ分析結果を示す図、第３図、第４図は熱処
理によるダイオードの劣化を示す図、第５図は本発明の
一実施例を示す断面図、第６図は実施例における劣化の
様子を示す図である。
１・・・ガラス基板、２・・・下部金属電極、３，４．
５・・・非晶質水素化シリコンｎ層、ｉ層、ｐ層、６・
・・Ａ４上部電極、７，８．９・・・Ｓｉ、Ａｔ、Ｂの
ＩＭＡ信号強度、１３・・・Ｃｒ電極、１４・・・Ａ７
電極。
代理人 弁理士 高橋明夫
不 １ 図
藁 ２ 図
ル
θ
に面クラ／７岬さ
不 ３ 図
１、−３
「
θ ｆθ ２ρ ３θ ４θ
５ρ夕へ（Ｔ１時間 （Ｒ今間ン
■ ４ 図
ｆｉｌｌ’
す４幻７理−吟開 （Ｐ１閏）
第 ５ 図
菖 乙 図
７１１、ム理吟間（時開ｐ
国分寺市東恋ケ窪１丁目２８Ｃ
地株式会社日立製作所中央伺
所内
の発 明 者 太田日佐雄
横須賀車載１丁目２３５６番地日
電信電話公社横須賀電気適化
究所内
■出 願 人 日本電信電話公社Figure 1 is a cross-sectional view of a conventional amorphous hydrogenated silicon-luminium diode, Figure 2 is a diagram showing the HMA analysis results of the side of the amorphous silicon layer that comes into contact with metal, Figures 3 and 4. FIG. 5 is a cross-sectional view showing an embodiment of the present invention, and FIG. 6 is a diagram showing the state of deterioration in the embodiment. 1... Glass substrate, 2... Lower metal electrode, 3, 4.
5...Amorphous hydrogenated silicon n layer, i layer, p layer, 6...
...A4 upper electrode, 7,8.9...IMA signal intensity of Si, At, B, 13...Cr electrode, 14...A7
electrode. Agent Patent Attorney Akio Takahashi 1 Figure 2 Figure θ ni Menkura / 7 Misaki Safu 3 Figure 1, -3 " θ fθ 2ρ 3θ 4θ
5ρ To evening (T1 hour (R Imama n ■ 4 Figure fill' Su4 Gen 7 Ri-Ginkai (P1 leap) 5th Iris Otsu Figure 711, Muriginma (time opening p Kokubunji City Higashi Koigakubo 1-28C) Inventor: Hitachi, Ltd., Chuo Research Office Inventor: Hisao Ota, Yokosuka Automobile 1-2356, Yokosuka Electrical Optimization Research Institute, Nippon Telegraph and Telephone Public Corporation Applicant: Nippon Telegraph and Telephone Public Corporation
Claims (1)
この非晶質シリコン層に接して第１の導電体層を有する
薄膜半導体装置であって、前記第１の導電体層は前記非
晶質シリコン層に接する側がＣｒ層よシ成る多層構造の
導電体層なることを特徴とする薄膜半導体装置。 ２、前記非晶質シリコン層がｎ型導電層、ｎ型導電層お
よびｐ型溝電層が順次液した積層構造を有することを特
徴とする特許請求の範囲第１項記載の薄膜半導体装置。 ３、前記非晶質シリコン層のｎ型導電層が前記基板側に
あることを特徴とする特許請求の範囲第２項記載の薄膜
半導体装置。 ４、前記非晶質シリコン層。ｐ型溝電層が前記基板側に
あることを特徴とする特許請求の範囲第２項記載の薄膜
半導体装置。 ５、前記第１の導電体層の多層構造の導電体層はＣｒ層
上にＡｔ層が積層されてなることを特徴とする特許請求
の範囲第１項〜第４項のいずれかに記載の薄膜半導体装
置。 ６、前記ｎ型導電層が省略されてなること全特徴とする
特許請求の範囲第２項〜第４項のいずれかに記載の薄膜
半導体装置。 ７、特許請求の範囲第１項〜第６項のいずれかに記載の
薄膜半導体装置において、前記基板上には第２の導電体
層を有し、この上部に非晶質シリコン層が積層されて成
ることを特徴とする薄膜半導体装置。[Claims] 1. Having an amorphous silicon layer on at least a predetermined substrate,
A thin film semiconductor device having a first conductive layer in contact with the amorphous silicon layer, wherein the first conductive layer has a multilayer conductive structure in which a side in contact with the amorphous silicon layer is a Cr layer. A thin film semiconductor device characterized by a body layer. 2. The thin film semiconductor device according to claim 1, wherein the amorphous silicon layer has a laminated structure in which an n-type conductive layer, an n-type conductive layer, and a p-type trench conductive layer are sequentially formed. 3. The thin film semiconductor device according to claim 2, wherein the n-type conductive layer of the amorphous silicon layer is on the substrate side. 4. The amorphous silicon layer. 3. The thin film semiconductor device according to claim 2, wherein the p-type trench conductor layer is on the substrate side. 5. The conductor layer of the multilayer structure of the first conductor layer is characterized in that an At layer is laminated on a Cr layer. Thin film semiconductor device. 6. The thin film semiconductor device according to any one of claims 2 to 4, characterized in that the n-type conductive layer is omitted. 7. The thin film semiconductor device according to any one of claims 1 to 6, wherein a second conductor layer is provided on the substrate, and an amorphous silicon layer is laminated on top of the second conductor layer. A thin film semiconductor device characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58097784A JPS59224182A (en) | 1983-06-03 | 1983-06-03 | Thin film semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58097784A JPS59224182A (en) | 1983-06-03 | 1983-06-03 | Thin film semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59224182A true JPS59224182A (en) | 1984-12-17 |
Family
ID=14201438
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58097784A Pending JPS59224182A (en) | 1983-06-03 | 1983-06-03 | Thin film semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59224182A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0423364A (en) * | 1990-05-15 | 1992-01-27 | Showa Shell Sekiyu Kk | Photoelectromotive force device usable as mirror |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5858777A (en) * | 1981-10-05 | 1983-04-07 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor element |
-
1983
- 1983-06-03 JP JP58097784A patent/JPS59224182A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5858777A (en) * | 1981-10-05 | 1983-04-07 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor element |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0423364A (en) * | 1990-05-15 | 1992-01-27 | Showa Shell Sekiyu Kk | Photoelectromotive force device usable as mirror |
| US5298087A (en) * | 1990-05-15 | 1994-03-29 | Showa Shell Sekiyu K.K. | Photovoltaic device useful as a mirror |
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