JPH084095B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH084095B2 JPH084095B2 JP60061308A JP6130885A JPH084095B2 JP H084095 B2 JPH084095 B2 JP H084095B2 JP 60061308 A JP60061308 A JP 60061308A JP 6130885 A JP6130885 A JP 6130885A JP H084095 B2 JPH084095 B2 JP H084095B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon substrate
- forming
- semiconductor device
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01051—Antimony [Sb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法、特にオーミック接続
工程に関するものである。TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an ohmic connection process.
従来の半導体装置のオーミック接続に関しては、半導
体素子形成基板の表面はアルミニウム（Al）との接触に
より行い、反対面は半田付にて容器にオーミック接続す
る方法が一般的であった、半田付される裏面は半田との
なじみの良い金属及びシリコンとの密着性の良い金属と
の組み合せでおおわれており、シリコン基板裏面側には
リン等の不純物を用いてN+層を設けていた。Regarding the conventional ohmic connection of a semiconductor device, the surface of the semiconductor element formation substrate was contacted with aluminum (Al), and the opposite surface was soldered to the container by ohmic connection. The backside of the silicon substrate is covered with a combination of a metal having a good affinity with solder and a metal having a good adhesion with silicon, and an N + layer was provided on the backside of the silicon substrate by using impurities such as phosphorus.
すなわち、第２図に示すように、表面にエピタキシャ
ル層を有するシリコン基板１の裏面を研磨して薄くした
後、表面エピタキシャル層にベース領域３およびエミッ
タ領域２を設け、裏面にAuSi共晶層9,Ti層6,Ni層５およ
び銀層４を積層し、その後熱処理をして、裏面に半田付
の可能なオーミック接続を設けていた。That is, as shown in FIG. 2, after the back surface of the silicon substrate 1 having an epitaxial layer on the front surface is polished to be thin, the base region 3 and the emitter region 2 are provided on the front surface epitaxial layer, and the AuSi eutectic layer 9 is provided on the back surface. Then, the Ti layer 6, the Ni layer 5 and the silver layer 4 were laminated and then heat-treated to provide a solderable ohmic connection on the back surface.
しかしながら、これらの複数金属層からなる電極系に
おいては、シリコンと直接接続される金属をどの様に選
んでもシリコン基板の不純物濃度が８×1018atom/cc以
上でないと良好なオーミック性接触が得られない事が経
験的に知られている。しかし、シリコン単結晶引き上げ
法で作られる基板そのものの不純物濃度を８×1018atom
/cc以上の不純物濃度とすることは製法技術上は非常に
困難であり、エピタキシャル基板としての不純物濃度に
は限界があった。又、不純物濃度が低いシリコン基板で
オーミック接触を得るためには、高温（500℃以上）で
の熱処理が必要であり、トランジスタの電流増幅率（h
FE）のリニアリティーが劣化してしまう。そこで、従来
は、シリコン単結晶引き上げ法で作られた基板の裏面に
高不純物濃度の拡散層を形成し、その後に裏面電極を形
成していた。半導体装置の熱抵抗を低く抑える為には、
製造後のシリコン基板全体の厚さを薄くする必要がある
が、高不純物濃度の拡散層を不純物拡散工程で形成する
ために、不純物拡散工程への投入前に研磨により薄くす
る必要があり、このため不純物拡散工程においてウェハ
ー割れ不良の増加等の問題が生じていた。However, in the electrode system composed of these multiple metal layers, no matter how the metal directly connected to silicon is selected, good ohmic contact can be obtained unless the impurity concentration of the silicon substrate is 8 × 10 18 atom / cc or more. It is empirically known that it is not possible. However, if the impurity concentration of the substrate itself made by the silicon single crystal pulling method is 8 × 10 18 atom
It was very difficult to make the impurity concentration above / cc in terms of manufacturing technology, and there was a limit to the impurity concentration as an epitaxial substrate. In order to obtain ohmic contact on a silicon substrate with a low impurity concentration, heat treatment at high temperature (500 ° C or higher) is necessary, and the current amplification factor (h
FE ) linearity will deteriorate. Therefore, conventionally, a diffusion layer having a high impurity concentration is formed on the back surface of a substrate made by the silicon single crystal pulling method, and then the back surface electrode is formed. In order to keep the thermal resistance of semiconductor devices low,
Although it is necessary to reduce the total thickness of the silicon substrate after manufacturing, in order to form a diffusion layer having a high impurity concentration in the impurity diffusion process, it is necessary to reduce the thickness by polishing before the impurity diffusion process. Therefore, problems such as an increase in wafer cracking defects have occurred in the impurity diffusion process.
本発明によれば、不純物濃度が８×1018atom/cc以下
であるシリコン基板の一主面上にベース層及びエミッタ
層を形成する工程と、ベース層及びエミッタ層形成後に
シリコン基板の他の主面上を研磨する工程と、シリコン
基板の他の主面上にTi層を形成する工程と、Ti層上にAu
Sb層を形成する工程と、AuSb層上にTi,Mo,W,Taの内の１
つ又は２つ以上の組み合わされた第１の金属層を形成す
る工程と、第１の金属層上にNi,Cu,Ag,Auの内の１つ又
は２つ以上の組み合わされた第２の金属層を形成する工
程と、シリコン基板を350℃〜500℃の範囲で熱処理する
工程とを含む半導体装置の製造方法が得られる。According to the present invention, a step of forming a base layer and an emitter layer on one main surface of a silicon substrate having an impurity concentration of 8 × 10 18 atom / cc or less, and another step of forming the base layer and the emitter layer on the other side of the silicon substrate. The step of polishing the main surface, the step of forming a Ti layer on the other main surface of the silicon substrate, and the step of Au on the Ti layer.
Step of forming Sb layer and 1 of Ti, Mo, W, Ta on AuSb layer
Forming one or more combined first metal layers, and one or more combined second of Ni, Cu, Ag, Au on the first metal layer. A semiconductor device manufacturing method including a step of forming a metal layer and a step of heat-treating a silicon substrate in the range of 350 ° C. to 500 ° C. can be obtained.
ウェハーを研磨することなく厚い基板のまま拡散工程
を施し、拡散の最終工程においてウェハーを所定の厚さ
に研磨を行い、しかる後Sbの入ったAuを蒸着又はスパッ
ターで付着させ、次にSbのストッパーとしてのTi又はM
o,W,Taの内の１つ又は２つ以上の組み合わされた金属膜
を設け、さらにこの上にNi,Cu,Ag,Auの内の１つ又は２
つ以上組み合わされた金属膜を設け、この系を350℃以
上500℃以下で熱処理を行って、オーミック接続をとっ
ている。The wafer is subjected to a diffusion process without polishing the thick substrate, and the wafer is polished to a predetermined thickness in the final step of diffusion, and then Au containing Sb is deposited by vapor deposition or sputtering, and then Sb Ti or M as a stopper
One or two or more combined metal films of o, W, Ta are provided, and one or two of Ni, Cu, Ag, Au are further provided on the metal film.
A metal film composed of three or more is provided, and this system is subjected to heat treatment at 350 ° C. or higher and 500 ° C. or lower to obtain ohmic connection.
次に、本発明を図面を参照してより詳細に説明する。 Next, the present invention will be described in more detail with reference to the drawings.
本発明の一実施例によれば、第１図に示すように、直
径４″φ，厚さ450μm,不純物濃度１×1018atom/ccのエ
ピタキシャル基板１を用い、所定の拡散工程を施し、ベ
ース層３及びエミック層２を形成する。さらに基板１を
厚さ230μｍとなる様に研磨し、蒸着を行う面に対しサ
ンドブラストを行う。又多層蒸着の可能な蒸着材を用い
てTi層8,AuSb層7,Ti層6,Ni層5,Ag層４をそれぞれ、200
Å,1000Å,2000Å,4000Å,4000Åの厚さで蒸着し、基板
１を400℃,30分間熱処理を行った。以上の製法では拡散
工程ではウェハー厚が450μｍと厚い為にウェハー割れ
不良はほとんどなく、熱処理中に第１層のTi層８を突き
破ってAuSb層７が基板のシリコン中に拡散して、良好な
オーミック接続層が形成され、２番目のTi層６はNi層５
に対するSb,Siのストッパー層として働くので、結果と
してシリーズ抵抗は拡散でN+層を形成した場合と同様に
良好な値とすることが可能である。According to one embodiment of the present invention, as shown in FIG. 1, an epitaxial substrate 1 having a diameter of 4 ″ φ, a thickness of 450 μm and an impurity concentration of 1 × 10 18 atom / cc is used, and a predetermined diffusion process is performed. A base layer 3 and an emic layer 2 are formed, and further, the substrate 1 is polished to a thickness of 230 μm, and the surface to be vapor-deposited is sandblasted. AuSb layer 7, Ti layer 6, Ni layer 5, Ag layer 4 are each 200
The substrate 1 was heat-treated at 400 ° C. for 30 minutes by vapor deposition with a thickness of Å, 1000 Å, 2000 Å, 4000 Å, 4000 Å. In the above-mentioned manufacturing method, since the wafer thickness is as thick as 450 μm in the diffusion step, there is almost no wafer cracking defect. Ohmic contact layer is formed, second Ti layer 6 is Ni layer 5
Since it acts as a stopper layer for Sb and Si with respect to, as a result, the series resistance can be set to a good value as in the case where the N + layer is formed by diffusion.
以上のように本発明による製造方法によれば、単結晶
シリコン基板に高濃度のN+層を形成することなく、拡散
工程を施しているので、シリコン基板を研磨することな
く厚い基板のまま拡散工程を施すことが可能となり、ウ
ェハー割れ不良を低減して、歩留りを向上させ、シリコ
ンウェハーの大型化にも対応できる、という効果を得ら
れる。As described above, according to the manufacturing method of the present invention, since the diffusion step is performed without forming the high-concentration N + layer on the single crystal silicon substrate, the silicon substrate is diffused as a thick substrate without polishing. It is possible to carry out the steps, and it is possible to obtain the effects of reducing defects in wafer cracking, improving the yield, and being able to cope with an increase in the size of silicon wafers.
更に、N+層を形成する必要がないので、製造工程を短
縮させ、通常使用される不純物濃度のシリコン基板にた
いして350℃〜500℃程度の低温の熱処理で良好なオーミ
ック接続を得ることができるという効果を得られるFurthermore, since it is not necessary to form an N + layer, it is possible to shorten the manufacturing process and obtain a good ohmic contact by heat treatment at a low temperature of about 350 ° C. to 500 ° C. for a silicon substrate with an impurity concentration that is normally used. Get the effect
第１図は本発明一実施例による熱処理前の半導体装置の
断面図、第２図は従来例による熱処理前の半導体装置の
断面図である。 １……シリコン基板、２……エミッタ、３……ベース
層、４……Ag層、５……Ni層、６……第2Ti層、７……A
uSb層、８……第1Ti層、９……AuSi共晶層。FIG. 1 is a sectional view of a semiconductor device before heat treatment according to an embodiment of the present invention, and FIG. 2 is a sectional view of a semiconductor device before heat treatment according to a conventional example. 1 ... Silicon substrate, 2 ... Emitter, 3 ... Base layer, 4 ... Ag layer, 5 ... Ni layer, 6 ... Second Ti layer, 7 ... A
uSb layer, 8 ... 1st Ti layer, 9 ... AuSi eutectic layer.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭57−63837（ＪＰ，Ａ) 特開 昭60−14445（ＪＰ，Ａ) 実開 昭56−119650（ＪＰ，Ｕ) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-57-63837 (JP, A) JP-A-60-14445 (JP, A) Actually developed JP-A-56-119650 (JP, U)
Claims (1)
Ｎ型シリコン基板にオーミック接続を形成する半導体装
置の製造方法において、前記シリコン基板の表面に所定
の拡散工程を施し素子領域域を形成する工程と、前記素
子領域の形成された前記シリコン基板の裏面を研磨する
工程と、前記研磨された前記シリコン基板の裏面にTi層
を加熱処理によって突き破られる厚さに形成する工程
と、前記Ti層上にAuSb層を形成する工程と、前記AuSb層
上にTi,Mo,W,Taの内の１つ又は２つ以上の組み合わされ
た第１の金属層を加熱処理によって突き破られることな
くバリア層として機能する厚さに形成する工程と、前記
第１の金属層上にNi,Cu,Ag,Auの内の１つ又は２つ以上
組み合わされた第２の金属層を形成した後、この系を35
0℃〜500℃の範囲で加熱処理する工程とを含むことを特
徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device in which an ohmic contact is formed on an N-type silicon substrate having an impurity concentration of 8 × 10 18 atom / cc or less, wherein a predetermined diffusion process is performed on the surface of the silicon substrate to form an element region region. A step of forming, a step of polishing the back surface of the silicon substrate on which the element region is formed, and a step of forming a Ti layer on the back surface of the polished silicon substrate to a thickness that can be pierced by heat treatment, , A step of forming an AuSb layer on the Ti layer, and piercing the AuSb layer by heat treatment on one or more combined first metal layers of Ti, Mo, W and Ta. And a second metal layer in which one or more of Ni, Cu, Ag, and Au are combined on the first metal layer is formed on the first metal layer. After doing this system 35
And a step of performing heat treatment in the range of 0 ° C to 500 ° C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60061308A JPH084095B2 (en) | 1985-03-26 | 1985-03-26 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60061308A JPH084095B2 (en) | 1985-03-26 | 1985-03-26 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61220344A JPS61220344A (en) | 1986-09-30 |
| JPH084095B2 true JPH084095B2 (en) | 1996-01-17 |
Family
ID=13167412
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60061308A Expired - Lifetime JPH084095B2 (en) | 1985-03-26 | 1985-03-26 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH084095B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0523701B1 (en) * | 1991-07-17 | 1998-01-07 | Denso Corporation | Method of forming electrodes of semiconductor device |
| US6211550B1 (en) * | 1999-06-24 | 2001-04-03 | Intersil Corporation | Backmetal drain terminal with low stress and thermal resistance |
| JP3951300B2 (en) * | 2003-07-23 | 2007-08-01 | 信越半導体株式会社 | Light emitting device and method for manufacturing light emitting device |
| JP4978877B2 (en) * | 2004-06-10 | 2012-07-18 | 信越半導体株式会社 | Light emitting device manufacturing method and light emitting device |
| JP5355586B2 (en) * | 2009-04-30 | 2013-11-27 | パナソニック株式会社 | Joining structure joining method |
| JP7271166B2 (en) * | 2018-12-21 | 2023-05-11 | ルネサスエレクトロニクス株式会社 | Semiconductor device and its manufacturing method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5690450A (en) * | 1979-12-24 | 1981-07-22 | Matsushita Electric Ind Co Ltd | Recording and reproducing device |
| JPS56119650U (en) * | 1980-02-15 | 1981-09-11 | ||
| JPS57154844A (en) * | 1981-03-20 | 1982-09-24 | Hitachi Ltd | Semiconductor element |
-
1985
- 1985-03-26 JP JP60061308A patent/JPH084095B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61220344A (en) | 1986-09-30 |
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| EXPY | Cancellation because of completion of term |