JP2919583B2 - Method for manufacturing thin film transistor - Google Patents

Description

The present invention relates to a method for manufacturing a thin film transistor using a polycrystalline silicon film as an active layer.

(B) Conventional technology In recent years, as a semiconductor material for a thin film transistor, a device using polycrystalline silicon as a constituent material has been rapidly developed.

In particular, a polycrystalline silicon thin film transistor has a feature that a transparent insulating substrate can be used as a supporting substrate thereof, and is therefore used for a pixel switching element such as a liquid crystal display.

However, in the case of a thin film transistor made of polycrystalline silicon, most of the process technology is diverted to that of single crystal silicon, so that the advantages of polycrystalline silicon not as a bulk but as a thin film cannot be fully utilized.

(C) Problems to be Solved by the Invention When polycrystalline silicon is used as an active layer of a thin film transistor, it is necessary to go through several doping steps during the step. Conventionally, as such a doping method, for example, an ion implantation method or the like has been used, but in any case, annealing at 1000 ° C. or more is required to activate the doping impurity.

As a result, a quartz substrate excellent in heat resistance has to be used as a light-transmitting insulating substrate for forming polycrystalline silicon, which raises manufacturing costs. Furthermore, in the conventional ion implantation method, since acceleration is necessary for implanting doping ions, it is difficult to increase the area of the processing substrate.

Regarding such technology, IEEE.ELECTRON DEVICE LETTER
S, VOL. 9 NO. 6 p.290-292 described in detail in JUNE1988.

An object of the present invention is to provide a manufacturing method for forming a semiconductor device made of polycrystalline silicon which requires a doping method at a lower temperature and a simpler method than before.

(D) Means for Solving the Problems A feature of the method of manufacturing a thin film transistor according to the present invention is that a polycrystalline silicon film in which the conductivity types of the ohmic contact portion and the channel formation portion are opposite to each other is used. In the method for manufacturing a thin film transistor provided, each of the above-described portions includes annealing in a state where a conductive amorphous silicon layer and an i-type or substantially i-type amorphous silicon layer are formed in an overlapping manner. The conductive amorphous silicon layer has a conductivity type of each of the portions.

(E) Function The conductive polycrystalline silicon film in the manufacturing method of the present invention is obtained by superposing and stacking a conductive amorphous silicon layer and an i-type or substantially i-type amorphous silicon layer on an insulating substrate. The semiconductor thin film thus formed is formed by annealing.

When the semiconductor thin film is annealed, the conductive amorphous silicon layer functions as nucleation for polycrystallization,
The intrinsic amorphous silicon layer can be polycrystallized at a low temperature of 600 ° C. or less.

Further, the polycrystalline silicon film has a structure in which the conductivity-type determining element in the conductive amorphous silicon layer diffuses into the i-type or substantially i-type amorphous silicon layer during the progress of the annealing. Will have.

Therefore, the conductive amorphous silicon layer is formed as a desired pattern for each conductivity type, and the intrinsic amorphous silicon is superimposed and laminated thereon and annealed to form a polycrystalline silicon film of each conductivity type. It can be formed corresponding to the pattern.

Note that the i-type amorphous silicon used in the present invention is:
For example, in the case of formation by plasma CVD, impurities formed for determining the conductivity type are not mixed, and only a reaction gas such as a silane compound is used.In the case of formation by sputter deposition, a silicon substrate is used as a target and sputtering is performed. A gas formed using an inert gas or the like without mixing impurities for determining conductivity type as a gas is used.

Such i-type amorphous silicon generally shows a slight n-type conductivity as it is.

The amorphous silicon that can be used in the present invention is not limited to the i-type amorphous silicon described above.
It may be substantially i-type amorphous silicon by doping the mold.

Hereinafter, i-type or substantially i-type amorphous silicon is abbreviated as intrinsic amorphous silicon.

(F) Example FIGS. 1 to 6 are sectional views for explaining steps of manufacturing a polycrystalline silicon thin film transistor of the present invention.

In a first step shown in FIG. 1, an intrinsic amorphous silicon layer (2) and a p-type amorphous silicon layer (3) are formed on a supporting substrate (1) by a conventionally known plasma CVD method or sputtering method. Then, the p-type amorphous silicon layer is patterned. In the plasma CVD method, a silicon compound such as silane is subjected to gas decomposition by plasma energy generated by glow discharge. When a p-type amorphous silicon layer is formed, for example, a diborane gas is added to the silicon compound as a doping gas.

In the example, the boron doping concentration of the p-type amorphous silicon layer was 10 ¹⁷ cm ⁻³ , and the thickness was 1000 °.
The thickness of the intrinsic amorphous silicon was 5000 °.

Next, in a second step shown in FIG. 2, an n-type amorphous silicon layer (4) is formed and patterned by a method similar to the plasma CVD method. In this case, a phosphine gas or the like is used as the doping gas. The phosphorus doping concentration of the n-type amorphous silicon layer (4) was 10 ²⁰ cm ^-3, and its thickness was 1000 °.

In the third step shown in FIG. 3, annealing is performed at 500 ° C. for 10 hours.

As a result, the p-type polycrystalline silicon layer (3a) and the n-type polycrystalline silicon layer (4a) form a pattern of the p-type amorphous silicon layer (3) and the n-type amorphous silicon layer (4). Is formed corresponding to

That is, the pattern of each conductive type amorphous silicon layer formed in the first step and the second step is designed so as to have a desired pattern when it is transformed into a polycrystalline silicon film in the third step. Do it.

In a fourth step shown in FIG. 4, the surfaces of the p-type polycrystalline silicon layer (3a) and the n-type polycrystalline silicon layer (4a) are slightly etched so that patterning in a subsequent step becomes easy. And flatten.

In a fifth step shown in FIG. 5, the gate insulating film (5)
Is formed by a plasma CVD method, a normal pressure CVD method or the like, and an opening for a drain and a source contact portion is provided in a part of the gate insulating film (5). In the embodiment, a silicon oxide film having a thickness of 1000 ° is used as the gate insulating film (5).

Finally, in a sixth step shown in FIG. 6, a metal film is deposited and patterned to form a gate metal film (6), a drain electrode (7), and a source electrode (8).

According to the embodiment, in the p-type polycrystalline silicon layer obtained by the annealing, a polycrystalline film having a large grain size is obtained, and in the case of the n-type polycrystalline silicon layer, the n-type amorphous silicon layer (4) Although the particle size was reduced due to the increase in the doping amount of, a good ohmic contact was obtained.

In the thin film transistor of the example, about 190 cm ² / V · s was obtained as the electron mobility.

According to the manufacturing method of the present invention, the conductive amorphous silicon and the intrinsic amorphous silicon are formed by a plasma CVD method or a sputtering method capable of forming a large area. The device can be manufactured.

(G) Effects of the Invention According to the method for manufacturing a thin film transistor of the present invention, a polycrystalline silicon layer in which n-type and p-type conductivity types are mixed can be easily formed.

Further, since the conventional ion implantation method is not used, the polycrystalline silicon can be formed over a large area.

Further, according to the present manufacturing method, it is not necessary to use an expensive substrate having excellent heat resistance as the substrate.

[Brief description of the drawings]

1 to 6 are cross-sectional views of a thin film transistor for explaining a manufacturing method of the present invention, which are based on manufacturing steps.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Satoshi Ishida 2-18-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (58) Field surveyed (Int. Cl. ⁶ , DB name) H01L 29 / 786 H01L 21/336 H01L 21/20

Claims (1)

(57) [Claims] In a method of manufacturing a thin film transistor having a polycrystalline silicon film in which an ohmic contact portion and a channel forming portion each have a conductivity type opposite to each other, each of the portions is made of a conductive amorphous material. A silicon layer and an i-type or substantially i
A method for producing a thin film transistor, wherein annealing is performed in a state in which an amorphous silicon layer of a conductive type is superposed on the conductive amorphous silicon layer.