JPH0620944A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To realize a low contact resistance by providing an impurity region formed on a predetermined region of a semiconductor substrate, an interlayer insulating film having an opening on its upper part, and an epitaxial silicon layer doped with an impurity formed on a region in contact with the impurity region in the opening. CONSTITUTION:A P<+> type diffused layer 104 and an N<+> type diffused layer 205 are formed on a semiconductor substrate 201, and an interlayer insulating film 206 is formed. Further, a contact hole 207 is formed, a P<+> type a-Si layer 208 doped with boron is formed, annealed, epitaxially grown, and crystallized. Then, a contact hole 109 is opened, a barrier layer 210 is formed, and a metal layer 211 is formed. Then, the layer 211 is etched back, a contact plug 212 is formed, and meal wirings 213 are formed. Thus, a contact structure having low resistance and excellent ohmic properties can be formed for the P<+> type diffused layer and the N<+> type diffused layer for the hole having high aspect ratio.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a device structure and a manufacturing method for realizing a semiconductor device having fine contact with excellent contact characteristics by a simple process. .

[0002]

2. Description of the Related Art In a submicron fine contact, an increase in contact resistance with a diffusion layer (particularly a P + diffusion layer) has been a problem. As a countermeasure for this, after opening the contact hole, B (boron) is additionally injected only in the P + diffusion region to increase the surface concentration of boron to reduce the contact resistance.

FIG. 3 shows a conventional method of manufacturing a semiconductor device. In FIG. 3, (a) is an N-type semiconductor substrate 301.
After forming well 302 and P-well 303, P + diffusion layer
In this step, the 304 and N + diffusion layers 305 are formed, and the interlayer insulating film 306 is formed. FIG. 3B shows a step of forming a contact hole 307 in the interlayer insulating film 306, selecting only a P + diffusion region by a mask 308, and ion-implanting boron. FIG. 3C shows a lamp anneal (100) for activating the ion-implanted boron after removing the mask.
(0 ° C. or higher) to form a barrier layer 309 of Ti / TiN or the like by a sputtering method, and then form a metal wiring 310 of Al—Si or the like.

[0004]

However, the conventional technique requires a photo step of selecting the P + diffusion region after the contact opening, an ion implantation step, and a step of activating the implanted dopant, which is complicated. there were.
Furthermore, since high-temperature heat treatment is required for activation, redistribution of impurities, damage due to thermal stress, etc. occur, which is a serious problem in devices of submicron or even half micron or less.

Therefore, the present invention solves such a problem by a simpler process and at 600 ° C.
Provided is a contact structure and a manufacturing method thereof for realizing a low contact resistance at a low temperature of about 700 ° C. or lower.

[0006]

According to another aspect of the present invention, there is provided a semiconductor device including: (1) a semiconductor substrate, an impurity region formed in a predetermined region of the semiconductor substrate, and an interlayer insulating film having an opening above the impurity region. It has at least a film and an epitaxial silicon layer doped with impurities formed in at least a region in contact with the impurity region in the opening.

(2) The epitaxial silicon layer doped with the impurity is characterized by containing 0.5 to 2 atomic% of boron.

The method of manufacturing a semiconductor device according to the present invention comprises: (3) forming a diffusion layer on a semiconductor substrate, forming an interlayer insulating film covering the diffusion layer, and forming an interlayer insulating film on the diffusion layer. Forming a contact hole; depositing an impurity-doped amorphous silicon layer in the contact hole and on the interlayer insulating film; and crystallizing the amorphous silicon by a solid phase growth method. It is characterized by including at least a step of forming a metal wiring layer.

(4) The amorphous silicon is solid-phase grown using the diffusion layer as a seed.

[0010]

1 is an example of a sectional view of a semiconductor device according to an embodiment of the present invention.

In FIG. 1, 101 is an N-well, 102 is a P + diffusion layer, 103 is an interlayer insulating film, 104 is a contact portion, 10
5 is a P + Si layer doped with boron, 106 is a barrier layer, 10
7 is a contact plug and 108 is a metal wiring layer.

FIG. 2 shows an example of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

In FIG. 2, (a) shows a semiconductor substrate 201.
After forming N-well 202 and P-well 203 inside, P
The + diffusion layer 204 and the N + diffusion layer 205 are formed, and the interlayer insulating film 20 is formed.
It is a step of forming 6. 2B, a contact hole 207 is formed on the P + diffusion region in the interlayer insulating film 206,
This is a step of forming a P + a-Si layer 208 doped with boron. As an example of the method for forming the P + a-Si layer, C
A method of forming a film by mixing a doping gas such as B2H6 (diborane) with a silane-based gas such as SiH4 (monosilane) at 520 ° C. to 560 ° C. by a VD method, and a SiH4 (at a temperature of 150 ° C. to 400 ° C. by a plasma CVD method). There is a method of forming a film by mixing a silane-based gas such as monosilane) with a doping gas such as B2H6 (diborane). The mixing ratio of the doping gas such as B2H6 and the silane-based reaction gas is 0.00
About 25 to 0.01 is desirable. The a-Si is doped with 0.5 atomic% to 2 atomic% boron corresponding to the above gas ratio. Since increasing the impurity concentration in a-Si is effective in reducing the contact resistance, it is desirable to set the mixing ratio to a high value within the range that does not hinder the epi growth. Subsequently, annealing is performed at 550 ° C. to 700 ° C. for about 1 hour to 10 hours, and the P + a-Si layer is epitaxially grown using the single crystal silicon of the diffusion layer as a seed to be crystallized. At this time, the portion in contact with the diffusion layer is monocrystallized, and the contact side wall portion and the like are polycrystallized. Figure 2
(C) shows a contact hole 209 formed on the N + diffusion region in the interlayer insulating film 206, and is made of TiN, TiW or Ti.
/ TiN barrier layer 210 is sputtered or CVD
This is a step of forming a metal layer 211 of W or the like over the entire surface by blanket CVD or the like after the formation by the method or the like. In order to reduce the contact resistance of the barrier layer, a structure in which a barrier metal such as TiN is provided on a contact metal such as Ti is effective. Furthermore, after the contact metal and the barrier metal are formed, annealing is performed in an inert gas or hydrogen gas atmosphere at about 550 ° C. to 700 ° C. to further reduce the contact resistance. In this embodiment, the case where W or the like is formed on the entire surface by the blanket CVD method is taken as an example, but the present invention is not limited to this. Figure 2
(D) is a step of etching back the metal layer to form a contact plug 212 and then forming a metal wiring 213 with Al—Cu or the like.

The electrical characteristics of the semiconductor device according to the present invention will be described below. According to the present invention, the contact resistance of 40 μm or less is provided in the contact hole having the film thickness of the interlayer insulating film of 1.5 μm and the contact diameter of 0.5 μm and the aspect ratio of 3.
It was possible to realize 60Ω (P + diffusion layer), 20 to 30Ω (N + diffusion layer). Further, even if annealing was performed for 30 minutes at 525 ° C. after Al wiring, a contact structure that was thermally stable was realized without causing deterioration of characteristics such as junction leakage.

As described above, according to the semiconductor device and the method of manufacturing the same according to the present invention, a semiconductor device having excellent contact characteristics for both the P + diffusion layer and the N + diffusion layer can be formed by a simple process at a low temperature. You can

The present invention is not limited to the embodiments shown in FIGS. 1 and 2 and can be widely applied to the contact structure of semiconductor devices in general.

[0017]

As described above, according to the present invention, both the P + diffusion layer and the N + diffusion layer have low resistance and excellent ohmic properties for a contact hole having a contact diameter of submicron or less and a high aspect ratio. A contact structure can be formed. Further, according to the present invention, the ion implantation step and the high temperature annealing step for activating the impurities after the contact hole opening, which is required in the prior art, are not required, and the temperature can be reduced to about 600 ° C. to 700 ° C. in a simpler process. It has become possible to realize excellent contact characteristics in low temperature processes.
Furthermore, excellent characteristics can be realized with good reproducibility without causing redistribution of impurities and damage due to heat stress.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a semiconductor device according to an embodiment of the invention.

FIG. 3 is a manufacturing process diagram of a conventional semiconductor device.

[Explanation of symbols]

 101,202,302 ・ ・ ・ N-well 102,304 ・ ・ ・ P + diffusion layer 103,206,306 ・ ・ ・ Interlayer insulating film 104 ・ ・ ・ Contact part 105,208 ・ ・ ・ P + Si layer 107 ・ ・ ・ Contact plug 108,213,310 ・ ・ ・ Metal wiring 201,301 ・ ・ ・ Semiconductor Substrate 203,303 ・ ・ ・ P-well 205,305 ・ ・ ・ N + diffusion layer 207,209,307 ・ ・ ・ Contact hole 212 ・ ・ ・ Contact plug

Claims (4)

[Claims] 1. A semiconductor substrate, an impurity region formed in a predetermined region of the semiconductor substrate, an interlayer insulating film having an opening above the impurity region, and at least the impurity region in the opening. A semiconductor device having at least an impurity-doped epitaxial silicon layer formed in the formed region. 2. The semiconductor device according to claim 1, wherein the impurity-doped epitaxial silicon layer contains 0.5 to 2 atomic% of boron. 3. A step of forming a diffusion layer on a semiconductor substrate,
Forming an interlayer insulating film covering the diffusion layer; forming a contact hole in the interlayer insulating film on the diffusion layer; and an amorphous silicon layer doped with impurities in the contact hole and on the interlayer insulating film. And a step of crystallizing the amorphous silicon by a solid phase growth method and a step of forming a metal wiring layer. 4. The semiconductor device according to claim 3, wherein the amorphous silicon is solid-phase grown using the diffusion layer as a seed.