JPS5854650A - Manufacture of semiconductor device having insulating layer isolation structure - Google Patents
Manufacture of semiconductor device having insulating layer isolation structureInfo
- Publication number
- JPS5854650A JPS5854650A JP15200081A JP15200081A JPS5854650A JP S5854650 A JPS5854650 A JP S5854650A JP 15200081 A JP15200081 A JP 15200081A JP 15200081 A JP15200081 A JP 15200081A JP S5854650 A JPS5854650 A JP S5854650A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- nitride film
- film
- epitaxial layer
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000002955 isolation Methods 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 15
- 230000003647 oxidation Effects 0.000 claims abstract description 15
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 15
- 150000004767 nitrides Chemical class 0.000 claims abstract 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 32
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 30
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 14
- 239000000377 silicon dioxide Substances 0.000 abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- 239000010703 silicon Substances 0.000 abstract description 13
- 238000001259 photo etching Methods 0.000 abstract description 5
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 4
- 230000001546 nitrifying effect Effects 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 8
- 238000000926 separation method Methods 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003513 alkali Substances 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- -1 sodium ions (Na'') Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置よ〕詳しく述べるならけ絶縁層分離
構造を有する半導体装置の製造方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device. More specifically, the present invention relates to a method for manufacturing a semiconductor device having an insulating layer separation structure.
半導体集積回路では、同一基板内に多くの能動素子およ
び受動素子を作〕込んで回路機能を構成しておシ、これ
ら素子が相互に電気的な影響を受けないように分離（マ
イル−シ、ン）する必要がある。分離方法には各種方法
かあシ、本発明はそのうちで絶縁層分離に関するもので
ある。In semiconductor integrated circuits, many active and passive elements are fabricated on the same substrate to form circuit functions, and these elements are separated (miles apart) so that they are not electrically influenced by each other. ) need to be done. There are various separation methods, and the present invention relates to insulating layer separation.
例えば、第１−に示し大半導体装置の絶縁装置の絶縁層
分離構造では、Ｐ型シリコン半導体基板１ 上Ｅ）ＮＷ
ｉエピタキシャル層２内に基板１に達する絶縁層で塾る
二酸化シリコン（８五〇 ２ ）層３が設けられている
。この構造の半導体装置を製造する＆ｌ、まずＰｆＩＩ
ｉシリコン基板１上ＫＮｆｊｌｉシリコンエピタキシャ
ル層２を形成し、このエピタキシャル層２０表面を熱酸
化して８％０□膜を形成し、その上Ｋ ＣＶＤ （化学
的気相成長）法による耐酸化膜（８１３Ｎ４膜）を形成
する。次に、ホトエツチング法によってＳｔ、Ｎ４膜お
よび８１０．膜を選択的にエツチングして分離領域のエ
ピタキシャル層管表出する。表出したエピタキシャル層
部分を基板に達するまで熱酸化して絶縁層３を形成し、
８１ ＢＨ３膜をエツチング除去することによって第１
＃Ａの半導体装置が得られる。この場合Ｋ、絶縁層３の
８１０２がナトリウムイオン（Ｎａ”）などのアルカリ
イオンによって汚染されることがあシ、また、エピタキ
シャル層の熱酸化中にあるいはその後の熱処理中に基板
ｌ内のＰ型不純物（＆ロン）が１０２絶縁層３中へ吸収
されるように偏析し、逆に１工ピタキシヤル層のＮ型不
純物（リン）が基板中へ偏析することＫよって絶縁層３
下の基板表面に伝導屋反転のチャネルリークが発生し易
くなってしまう。For example, in the insulating layer separation structure of the insulating device of a large semiconductor device shown in No. 1-, the P-type silicon semiconductor substrate 1 is
In the epitaxial layer 2 there is provided a silicon dioxide (850 2 ) layer 3 which is surrounded by an insulating layer and reaches the substrate 1 . To manufacture a semiconductor device with this structure, first PfII
A KNfjli silicon epitaxial layer 2 is formed on a silicon substrate 1, the surface of this epitaxial layer 20 is thermally oxidized to form an 8% 0□ film, and an oxidation-resistant film ( 813N4 film). Next, the St, N4 film and 810. The membrane is selectively etched to expose the epitaxial layers of the separation region. The exposed epitaxial layer portion is thermally oxidized until it reaches the substrate, forming an insulating layer 3.
81 By etching away the BH3 film, the first
A semiconductor device #A is obtained. In this case, the K, 8102 of the insulating layer 3 may be contaminated by alkali ions such as sodium ions (Na''), and the P-type in the substrate 1 may be contaminated during thermal oxidation of the epitaxial layer or during subsequent heat treatment. Impurities (phosphorus) segregate to be absorbed into the insulating layer 3, and conversely, N-type impurities (phosphorus) in the first pitaxial layer segregate into the substrate.
Channel leakage due to conduction reversal is likely to occur on the surface of the underlying substrate.
本発明の目的は、絶縁層分離領域でのチャネルリークの
発生を防止し得る絶縁層離構造會得ることができる製造
方法を提供することである。An object of the present invention is to provide a manufacturing method capable of obtaining an insulating layer separation structure that can prevent channel leakage in an insulating layer isolation region.
本発明の別の目的は、基板中の不純物が絶縁層中へまた
エピタキシャル層中の不純物が基板中へ偏するのを防止
することができる製造方法上提供することである。Another object of the present invention is to provide a manufacturing method that can prevent impurities in the substrate from being localized into the insulating layer and impurities in the epitaxial layer from being localized into the substrate.
上述の目的が、半導体基板の分離領域に相当する部分の
赤面上に直接窒化シリコン膜管形成し、この半導体基板
お、よび直接窒化シリコン膜の上にエピタキシャル層を
形成し、次に、このエピタキシャル層の分離領域に相当
する部分を直接窒化シリコン膜まで酸化することによっ
て製造された絶縁層分離構造を有する半導体装置では達
成できる。The above purpose is to form a silicon nitride film tube directly on the surface of the part corresponding to the isolation region of the semiconductor substrate, to form an epitaxial layer directly on this semiconductor substrate and directly on the silicon nitride film, and then to form an epitaxial layer on the semiconductor substrate and directly on the silicon nitride film. This can be achieved in a semiconductor device having an insulating layer isolation structure manufactured by directly oxidizing a portion of a layer corresponding to an isolation region to a silicon nitride film.
直！１ｉ１化シリコン膜上のエピタキシャル層は多くの
場合に多結晶層となってしまうが、エピタキシャル成長
法で形成したという意味で多結晶層であっても本明細書
中ではエピタキシャル層とする。straight! Although the epitaxial layer on the 1i1 silicon film is often a polycrystalline layer, in this specification, even if it is a polycrystalline layer in the sense that it is formed by an epitaxial growth method, it is referred to as an epitaxial layer.
直接窒化シリコン膜上の分離領域のエピタキシャル層部
分を酸化する前に、この部分管その厚さの半分程工、チ
ング除去するならば、残シの半分全酸化したときに酸化
絶縁層の表面がエピタキシャル層表面と同橘度のレベル
となル表面平坦な半導体装置が得られる・
以下、株付図面に関連した本発明の実施態様によって本
発明を説明する。Before oxidizing the epitaxial layer portion of the isolation region directly on the silicon nitride film, if this portion is removed by a process of about half its thickness, the surface of the oxide insulating layer will be completely oxidized when the remaining half is completely oxidized. A semiconductor device having a flat surface on the same level as the surface of an epitaxial layer can be obtained.The present invention will be described below with reference to embodiments of the present invention in conjunction with the accompanying drawings.
Ｐ潴シリコン基板１１０表面を直熱窒化して窒化シリー
ン膜（Ｓ ｉ 、Ｎ４膜、例えば厚さ１００Ｘ）１２を
形成する。ホトエツチング法にて窒化シリコン膜１２の
分離領域形成領域に相当する部分上桟してそれ以外の部
分の窒化シリコン膜を除去する備２図）。シリコンのエ
ピタキシャル成長管性なって残っている窒化シリコン膜
１２を含めて基板１１全体ＫＮ型エピタキシャル層１３
（例えば厚さ１．５μｍ）！形成する（第３図）、窒化
シリコン膜１２上のエピタキシャル層部分はポリシリコ
ン層と々っていることが多い。エピタキシャル層１３を
熱酸化して二酸化シリコン（８１０２）膜１４管形成し
、その二酸化シリコン膜１４の上にＣＶＯ（化学的気相
成長）法による窒化シリコン（８１、Ｎ４）膜１５を形
成する（第３−）。The surface of the silicon substrate 110 is directly thermally nitrided to form a silicon nitride film (S i , N4 film, eg, 100× thick) 12 . Using a photo-etching method, a portion of the silicon nitride film 12 corresponding to the isolation region forming region is removed, and the rest of the silicon nitride film is removed (see Fig. 2). The entire substrate 11, including the silicon nitride film 12 remaining as a silicon epitaxial growth tube, is formed into a KN type epitaxial layer 13.
(For example, thickness 1.5 μm)! The epitaxial layer portion on the silicon nitride film 12 to be formed (FIG. 3) is often a polysilicon layer. The epitaxial layer 13 is thermally oxidized to form a silicon dioxide (8102) film 14, and a silicon nitride (81, N4) film 15 is formed on the silicon dioxide film 14 by a CVO (chemical vapor deposition) method ( 3rd-).
次に、ホトエツチング法によりて窒化シリコン膜１５お
よび二酸化シリコン膜１４ｔ−選択的にエツチングして
分離領域に相当する箇所に開孔（図示せず）管形成する
。そして熱酸化処理によりて開孔内に表示したエピタキ
シャル層１３會酸化して第４図に示すような絶縁酸化（
ＳｔＯ，）層１６形成する。このとき窒化シリコン膜１
５１ｉ耐酸化膜として働くので分離領域以外のエピタキ
シャル層１３は酸化されない。このようＫして形成した
絶縁層分離構造では直接窒化シリコン膜１２がＰ型基板
１１と絶縁酸化層１６との関に存在するので、基板中の
不純物（例えｄＭロン）が絶縁酸化層１６中へ偏析する
のｔ防止しかつＮ型エピタキシャル層１２中の不純物（
例えはリン）が基板中へ偏析するの會防止することがで
きる。したがって、チャネルリークの発生が回避できる
。Next, the silicon nitride film 15 and the silicon dioxide film 14t are selectively etched by photo-etching to form holes (not shown) in locations corresponding to isolation regions. Then, the epitaxial layer 13 shown in the opening is oxidized by thermal oxidation treatment to form an insulating oxidation (
A layer 16 of StO, ) is formed. At this time, silicon nitride film 1
Since the 51i acts as an oxidation-resistant film, the epitaxial layer 13 other than the isolation region is not oxidized. In the insulating layer isolation structure formed in this way, since the silicon nitride film 12 exists directly between the P-type substrate 11 and the insulating oxide layer 16, impurities in the substrate (for example, dMron) are present in the insulating oxide layer 16. This prevents the segregation of impurities in the N-type epitaxial layer 12 (
For example, phosphorus) can be prevented from segregating into the substrate. Therefore, occurrence of channel leakage can be avoided.
窒化シリコン膜１５１エツチング除去し、アイソレージ
、ンされたエピタキシャル層１２内に回路素子を公知方
法で形成して半導体装置を完成させる。The silicon nitride film 151 is etched and removed, and circuit elements are formed in the isolated epitaxial layer 12 by a known method to complete the semiconductor device.
ＩＣ、Ｌ８Ｉ 等の半導体装置では埋込層が形成されて
おシ、このような半導体装置を本発明の製造方法を応用
して製造する場合を説明する。A buried layer is formed in semiconductor devices such as ICs and L8Is, and the case where such semiconductor devices are manufactured by applying the manufacturing method of the present invention will be described.
Ｐ型シリコン基板２１１２）表面を熱酸化して二酸化シ
リコン膜２２を形成し、その上にＣＶＤ法による窒化シ
リコン膜２３を形成する。ホトエツチング法によりてこ
れら膜２２および２３の埋込層形成領域部分を除去して
分離領域部分を残す（第５図）。P-type silicon substrate 2112) The surface is thermally oxidized to form a silicon dioxide film 22, and a silicon nitride film 23 is formed thereon by CVD. By photo-etching, the buried layer forming regions of these films 22 and 23 are removed, leaving the isolation regions (FIG. 5).
シリコン基板２１の埋込層形成領域にイオン打込み又は
熱拡散によってＮｆＪｉ不純物（例えばアンチモン又は
リン）を注入し、熱酸化処理によって第６図のように埋
込層形成領域のシリコンを酸化して二酸化シリコン膜２
４を形成する。窒化シリコン膜２３は耐酸化膜として働
く。破線で示した領域２５が埋込拡散領域である。NfJi impurities (for example, antimony or phosphorus) are implanted into the buried layer formation region of the silicon substrate 21 by ion implantation or thermal diffusion, and the silicon in the buried layer formation region is oxidized by thermal oxidation treatment to oxidize the silicon dioxide as shown in FIG. Silicon film 2
form 4. The silicon nitride film 23 functions as an oxidation-resistant film. A region 25 indicated by a broken line is a buried diffusion region.
窒化シリコン膜２３をエツチング除去し、その下にある
二酸化シリコン膜２２もエツチング除去する。このとき
、埋込拡散領域２５上の二酸化シリコン膜２４も同時に
二酸化シリコン膜２２の厚さに相当する部分がエツチン
グ除去される。直接熱窒化処理して表出した基板２１の
表面に窒化シリコン膜（Ｓ ｉ 、Ｎ４膜）２６を形成
する（第７図）・次にに酸化シリコン膜２４′を全てエ
ツチング除去する。エピタキシャル成長法によって基板
２１および窒化シリコン膜２６の上にシリコンエピタキ
シャル層２７ｔ−形成する。このとき、埋込拡散領域２
５から不純物がエピタキシャル層２７内へ拡散し、埋込
層２５となる。エピタキシャル層２７の表面全熱酸化し
て二酸化シリコン膜２８を形成し、その上にＣＶＤ法に
よる窒化シリコン膜２９を形成する（第８図）。The silicon nitride film 23 is etched away, and the underlying silicon dioxide film 22 is also etched away. At this time, a portion of the silicon dioxide film 24 on the buried diffusion region 25 corresponding to the thickness of the silicon dioxide film 22 is etched away at the same time. A silicon nitride film (S i , N4 film) 26 is formed on the exposed surface of the substrate 21 by direct thermal nitriding (FIG. 7).Next, the silicon oxide film 24' is completely etched away. A silicon epitaxial layer 27t- is formed on the substrate 21 and the silicon nitride film 26 by an epitaxial growth method. At this time, the embedded diffusion region 2
Impurities from 5 diffuse into the epitaxial layer 27 and become the buried layer 25. A silicon dioxide film 28 is formed by thermally oxidizing the surface of the epitaxial layer 27, and a silicon nitride film 29 is formed thereon by the CVD method (FIG. 8).
ホトエツチング法で窒化シリコン膜２９および二酸化シ
リコン膜２８の分離領域相当部分をエツチング除去して
開孔を形成し、この開孔を通してエピタキシャル層２７
をその厚さの半分程工、チング除去する（第９図）。A portion of the silicon nitride film 29 and the silicon dioxide film 28 corresponding to the isolation region is etched away using a photoetching method to form an opening, and the epitaxial layer 27 is formed through the opening.
Remove the scratches by processing about half of its thickness (Figure 9).
そして、熱酸化処理によって開孔に表出したエピタキシ
ャル層２７を窒化シリコン膜２６に達するまで酸化して
絶縁酸化層３０を形成する（第１０埋込層含有する半導
体装置が得られる。Then, the epitaxial layer 27 exposed in the opening by the thermal oxidation process is oxidized until it reaches the silicon nitride film 26 to form an insulating oxide layer 30 (a semiconductor device containing a tenth buried layer is obtained).
かかるエピタキシャル層２７の酸化の際、横方向への酸
イヒを抑制すれば、絶縁酸化層３０の占有面積を低減す
ることができ当該半導体装置の集積度を高めることがで
きる。かかるエピタキシャル層２７の横方向への酸化を
抑制するためには、例えば前述の如くエツチングによっ
てはは半分の厚さとされたエピタキシャル層２７の露出
表面管直接窒化し、次いで生成され九窒化シリコン膜の
うち底部部分の窒化シリコン膜を除去する。かかる窒化
シリコン膜の選択的除去は方向性を有するドライエ、チ
ング法を適用することができる。しかる稜エピタキシャ
ル層の熱酸化処理を行なえば、当該エピタキシャル層開
口部の側面には前記直接窒化シリコン層が残存するため
に、かかる横方向への酸化は行なわれず、酸化は縦方向
へのみ進行する九め、占有面積の低減された絶縁域化層
を形成することができる。If oxidation of the epitaxial layer 27 is suppressed in the lateral direction, the area occupied by the insulating oxide layer 30 can be reduced and the degree of integration of the semiconductor device can be increased. In order to suppress such lateral oxidation of the epitaxial layer 27, the exposed surface of the epitaxial layer 27, which has been reduced to half its thickness by etching as described above, is directly nitrided, and then the formed silicon nitride film is nitrided. The bottom portion of the silicon nitride film is removed. For selective removal of such a silicon nitride film, a directional dry etching method can be applied. If the ridge epitaxial layer is thermally oxidized, the direct silicon nitride layer remains on the side surfaces of the opening in the epitaxial layer, so oxidation in the lateral direction does not occur, and oxidation progresses only in the vertical direction. Ninth, it is possible to form an insulating layer that occupies a reduced area.
第１図は従来の半導体装置の絶縁層分離構造部分の断面
図であシ、第２図ないし第４図は本発明による半導体装
置製造工程を説明する半導体装置の部分断面図であシ、
第５図ないし第１０図は本発明に係る製造方法を適用し
て半導体装置を製造する工程を説明する半導体装置の部
分断面図である。
１１・・・半導体基板、１２・・・窒化シリコン膜、１
３・・・エピタキシャル層、１４・・・二酸化シリコン
膜、１５・・・窒化シリコン膜、１６・・・絶縁酸化層
、２１・・・半導体基板、２４・・・二酸化シリコン膜
、２５・・・埋込層、２６・・・窒化シリコン膜、２７
・・・エピタキシャル層、３０・・・絶縁酸化層。
特許出願人
富士通株式会社
特許出願代理人
弁理士 青 木 朗
弁理士西舘和之
弁理士 内 １）幸 男
弁理士 山 口 昭 之
第２図
第３図
第６因
第７図FIG. 1 is a sectional view of an insulating layer separation structure portion of a conventional semiconductor device, and FIGS. 2 to 4 are partial sectional views of a semiconductor device illustrating a semiconductor device manufacturing process according to the present invention.
5 to 10 are partial cross-sectional views of a semiconductor device illustrating the steps of manufacturing the semiconductor device by applying the manufacturing method according to the present invention. 11... Semiconductor substrate, 12... Silicon nitride film, 1
3... Epitaxial layer, 14... Silicon dioxide film, 15... Silicon nitride film, 16... Insulating oxide layer, 21... Semiconductor substrate, 24... Silicon dioxide film, 25... Buried layer, 26... silicon nitride film, 27
...Epitaxial layer, 30...Insulating oxide layer. Patent applicant Fujitsu Limited Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney 1) Yukio Patent attorney Akiyuki Yamaguchi Figure 2 Figure 3 Figure 6 Cause Figure 7
Claims (1)
窒化膜を選択的に形成する工程、（へ）前記半導体基板
および直接窒化膜の上にエピタキシャル層を形成する工
程、および、（尊 前記エピタキシャル層の分離領域に
相当する部分を前記直接窒化膜まで選択的に酸化する工
程・ を含んでなる絶縁層分離構造を有する半導体装置の製造
方法。 ２、前記選択酸化工１１（ロ）の前に１前記工ピタキシ
ヤル層の分離領域に相当する部分をその厚さの半分機ま
で選択的に工、チング除去する工Ｓｔ會んでいる特許請
求の範Ｓ菖１項記載の製造方法。[Claims] 1. The following steps (7) to (fA: ■ A step of selectively forming a direct nitride film on the surface of a portion of the semiconductor substrate corresponding to the isolation region, (f) the semiconductor substrate and an insulating layer isolation structure comprising: forming an epitaxial layer directly on the nitride film; and selectively oxidizing a portion of the epitaxial layer corresponding to the isolation region up to the direct nitride film. Method for manufacturing a semiconductor device. 2. Before the selective oxidation process 11 (b), a process step for selectively etching and removing a portion corresponding to the isolation region of the 1-described epitaxial layer to half its thickness. A manufacturing method according to claim 1 of the patent claim S.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15200081A JPS5854650A (en) | 1981-09-28 | 1981-09-28 | Manufacture of semiconductor device having insulating layer isolation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15200081A JPS5854650A (en) | 1981-09-28 | 1981-09-28 | Manufacture of semiconductor device having insulating layer isolation structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5854650A true JPS5854650A (en) | 1983-03-31 |
Family
ID=15530871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15200081A Pending JPS5854650A (en) | 1981-09-28 | 1981-09-28 | Manufacture of semiconductor device having insulating layer isolation structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5854650A (en) |
-
1981
- 1981-09-28 JP JP15200081A patent/JPS5854650A/en active Pending
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