JPS5851574A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the electron mobility in a semiconductor device by inducing electron group in the vicinity of a hetero boundary between a buffer layer and an electron running layer and operating the electron group as a function of conductive medium. CONSTITUTION:An AlGaAs single crystal layer (buffer layer) 3 having no impurity is formed on a GaAs single crystal layer (electron running layer) 2 having less impurity content, an N type GaAs single crystal layer (control layer) 4 is further formed, and electrodes are formed on the layer 4. The material of the layer 4, the density of an impurity and the thickness of the layer are selected to the optimum conditions, thereby setting the surface potential between the layers 2 and 3 in the thermally balances state to OV, a positive voltage is applied to the gate, thereby inducing electron group (secondary electron gas) in the vicinity of the hetero boundary between the layers 3 and 4, and a high electron mobility transistor which operates as an enhancement type is formed with the electron group as conductive medium.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device. For more information, please refer to 2 types of Fi
In a semiconductor device having a combined layer structure consisting of three types of semiconductors with different energy gaps, a group of electrons (two-dimensional electron gas) is induced near the interface between the semiconductor layers with low impurity content. By using the property that the electron mobility of this group of electrons is not affected by impurity scattering, it is used as a conductive medium at a low temperature such as 77°K where the effect of impurity scattering prevents the increase in electron mobility. This invention relates to an enhancement type transistor based on a novel idea, which belongs to the category of high electron mobility transistors, which are characterized by realizing extremely high electron mobility.

The inventor of the present invention has discovered that two types of semiconductors with different electron affinities, such as full construction tool and GaAs
) and gallium arsenide (oaAs). An active semiconductor device which controls the impedance of a conductive path formed by the electron storage layer (two-dimensional electron gas) between a pair of input and output electrodes sandwiching a control electrode. Complete the invention and apply for a patent (
Patent Application No. 1982-82035) has been filed. but,
In the active semiconductor device of this patent application, the semiconductor with low electron affinity, that is, the semiconductor with a large energy gap (in the above example, Al-densium-GaAs/GaAs) is N-type. A large semiconductor, that is, a semiconductor with a small energy gap (in the above example, GaAs with arsenide)
The type impurity diffuses and forms an electron storage layer (two-dimensional electron gas).
There was naturally a limit to the improvement of electron mobility.

The first object of the present invention is to induce a group of electrons (two-dimensional electron gas) near the hetero interface formed by combining semiconductors of two types or three types of Fi with different energy gaps, and to convert this group of electrons into a conductive medium. In high electron mobility transistors, there is no need to apply impurities to the semiconductor layer directly adjacent to the semiconductor layer forming the conductive medium, and the transistor has a novel layer structure with improved electron mobility compared to conventional transistors. An object of the present invention is to provide a high electron mobility transistor.

A second object of the present invention is to provide a high electron mobility transistor having the above-mentioned structure, whose characteristic characteristic point-off voltage can be accurately controlled.

A third object of the present invention is to provide a high electron mobility transistor having the above structure, in which the contact resistance of the control electrode (source/drain electrode) is low and the transfer conductance is excellent. be.

A fourth object of the present invention is to provide a high electron mobility transistor having the above-mentioned structure, in which it is easy to realize excellent characteristics, and the structure is easy to manufacture. It's about doing.

The key to achieving the first objective is to use semiconductors with relatively small energy reserves, such as arsenide gallium
A semiconductor with a relatively large energy gap, such as aluminum (GaAs), is placed on a single crystal layer (electron transit layer) with a low impurity content.
A semiconductor formed of, for example, gallium arsenide (GaAs), which forms a single-crystal layer (9 tungsten layer) substantially free of impurities and has an energy gap equal to or lower than that of the semiconductor forming the electron transit layer. An N-type single crystal layer (control layer) is formed, and at least one control electrode (gate electrode) is provided on the control layer. By selecting the material of the control layer, the impurity concentration of the control layer, and the thickness of the control layer to the optimum conditions, the surface potential between the electron transport layer and the layer 7a is determined in a state of thermal equilibrium. 0 (zero)■
and 7. By applying a positive voltage to the control electrode (gate electrode), a group of electrons (two-dimensional electron gas) is induced in the vicinity of the hetero interface between the nototsufa layer in the electron transport layer. The purpose is to create a high electron mobility transistor that functions in an enhancement type manner as a conductive medium. In addition, the control room & (
The gate electrode) is preferably made of Shirotkipalya M1.
The output electrodes (source/drain electrodes) are made by vapor depositing gold/gold germanium (Au/AuGe), etc., and then alloying this.
It is desirable to ensure resistive contact with the above electron group (two-dimensional electron gas).

The key to achieving the second objective is to control the impurity concentration of the electron transit layer to a low concentration of ym or #iP type, rather than leaving it in the so-called unintensive doped state. The purpose is to accurately control the built-in voltage of the semiconductor stack that makes up the electron mobility transistor, so that the surface potential between the electron transit layer and the 79777 layer can be set to exactly 0 (zero) V. .

The key to achieving the third purpose above is input/output type 1
# (Source/drain electrodes) After introducing N-type impurities into the lower region of the planned formation area and performing heat treatment, input/output electrodes (source/drain electrodes) are vapor-deposited, and further heat treatment is performed. This is then alloyed to form input/output electrodes (source/drain electrodes), and the contact resistance between the input/output electrodes (source/drain electrodes) and the electron transit layer, especially the two-dimensional electron gas, is It lies in decreasing.

Note that this heat treatment temperature requires a temperature of 700 degrees Celsius, so a high melting point metal must be used for the control electrode (gate electrode). However, due to the use of ion implantation, there is an essential drawback in high electron mobility transistors! This has the great advantage of eliminating the difficulty of ensuring ohmic contact between certain input/output electrodes (source/drain electrodes) with the two-dimensional electron gas layer, and simplifying the manufacturing method.

The gist of achieving the fourth objective is to remove the control layer and the A7A layer below the input/output electrode (source/drain electrode) region, which are completely unnecessary from a functional point of view, to create a mesa-type structure. It is in. This is because it is easy to improve various characteristics including transfer conductance, and the manufacturing method is also easy.

The operating principle of the present invention will be explained below with reference to the drawings.

FIG. 1 is a conceptual cross-sectional view 1 of a high electron mobility transistor according to an embodiment of the present invention. In the figure, 1 is P-plated semi-insulating gallium arsenide (such as chromium (Or)).
2 is a single-crystal layer of gallium arsenide (GaAa) substantially free of impurities formed thereon, and constitutes an electron transit layer. 3 is aluminum containing substantially no impurities, gallium arsenide (Ar
This layer is made of a single crystal layer of EAAS), and is bonded to the electron transit layer 2 with a good heterointerface. 4 is an N-type gallium arsenide (GaAs) single crystal layer "r!", which is bonded to the layer 3 with a good hetero interface.The impurity concentration and thickness of this layer 4 are optimized. The desired high electron mobility transistor is fabricated by selecting a 5Fi Shirotsutokinori type control electrode (gate electrode).The metal used is aluminum (A/
), and 06, which is completely free, has a pair of input/output electrodes (source/drain electrodes) -t%, and in this example, a gold/gold germanium film (mu/AuG) is deposited. A further heat treatment is performed to alloy the region indicated by 7 and to establish electrical conductivity with the two-dimensional electron gas induced at the interface between the nosofa layer 3 and the electron transport layer 2.

Figure 2 is an energy inoton P/diagram 1 in a thermal equilibrium state of a high electron mobility transistor whose conceptual cross-sectional view is shown in Figure 1. Aq represents the Fermi level, B represents the valence band level, and 0 represents the . . . 1 conduction band level. First, it is well known that a high density of surface states exists on the surface of arsenide oxide (OAAs), and a pinning effect at the surface level of 7 hermi occurs. As long as sufficient electrons are contained in the semiconductor or semiconductor system, the energy of this pinning effect is not controlled by various conditions ('-), including the impurity concentration, and has a constant value of 1; ,
2/3 of the energy gap of the semiconductor or semiconductor system
It is also well known that the value corresponding to -I'S. the result,
The built-in potential Vbi ij of the semiconductor stack whose layer structure is illustrated in FIG. 1 is constant.

On the other hand, this value is
) surface potential v3 of layer 4 and arsenic (A/GaAs) layer 4 that does not contain substantial impurities.
) is equal to the sum of the potential PLozzo v, I in the layer 3 and the surface potential V of the gallium arsenide (GaAs) layer 2 with a low impurity content. That is, vbt=vl-11-v2+v,'1. Among the variables constituting the right-hand side of this equation, there is a
aAs) The surface potentials v1 and v3 of the layer 2 are functions of the type of semiconductor, impurity concentration and thickness, and
The potential drop V in the layer 3 is mainly due to the thickness of the gallium arsenide (GaAs) layer 2 and the gallium arsenide (GaAs) layer 2.
Since the surface potential V1 of the arsenide arsenide layer 2 is controlled by the surface potential V1 of the arsenide arsenide layer 2,
There is a possibility that 0 (zero) v1 d. The energy node die and diagram in this case are as shown in FIG. A high electron mobility transistor with such an energy pan diagram has a pinch-off voltage of 0 (zero).
It functions as a V enhancement type transistor.

That is, in a state of thermal equilibrium, there is no electrical continuity between the input and output electrodes (source and P-rain electrodes) 6, but when a positive voltage is applied to the control electrode (gate electrode) 6, the /7 in the electron transport layer 2 Electron group (two-dimensional electron gas) at the interface with layer 3
is induced and functions as a conductive medium. At this time, 79
This is because the energizer gap of the 171 layer 3 functions as a potential barrier and effectively prevents the above electron group from flowing into the control layer 4.

An example of requirements for realizing such conditions is shown below. The N-type impurity concentration of the gallium arsenide (GaAs) layer 2, which is sufficiently thick with a thickness of about 000 sq.
The impurity concentration of the layer 3 is O (zero) and the thickness is 200X, and the impurity concentration and thickness of the N-type arsenide IJ & Lamb (eaAa) layer 4 are varied. As mentioned above, since a sufficient amount of electrons exist in this semiconductor stack as a whole system, the built-in voltage of the semiconductor stack as a whole is 7.
1) i is constant and in this case α97-1'. There-1', the impurity concentration of the N-type gallium arsenide (GaAs) layer 4 is 1018/C111" and 10"/6113.
) Varying the thickness of layer 4, the above variable 71 + M
*Figure 84 shows how the distribution of V3 changes.

It is shown in FIG. FIG. 4 shows the former case, and FIG. 5 shows the latter case. As is clear from the figure, in the former case, NT
The thickness of the arsenide gas IJ zram (eaAa) layer 4 of l1 is 2
When it is about 210
When the thickness of the GaAs) layer 4 increases to about 350 mm, the surface potential of the electron transit layer 2 becomes 0 (zero), which satisfies the above requirements.
Similarly, the potential drop v2 in 1a is 0 (zero) V.
becomes. In the latter case, N-type arsenide Gariu A (G&A@
) The above requirements are satisfied when the thickness of layer 4 is approximately 1.1''OO'A. That is, under these conditions, the enhancement type high electron mobility transistor according to the embodiment of the present invention functions as an enhancement type field effect transistor (20 or less). The manufacturing process will be explained to further clarify the structure and unique effects of the present invention. Using the molecular beam epitaxial growth method (see FIG. 6),
A semiconductor stack is formed whose layer parameters are shown below. The numbers shown in the figure are the same as those shown in Figure 1! be.

1 Gallium arsenide 4 X 10 0r 1
0" vertical GaAs 2 Den 1 5,000 Si 10143 Aluminum 1 Um Gallium Arsenic 200
None A/6,3Ga(,,7As 4Gallium arsenide 1,100 '8110
17 However, gallium arsenide (Ga,
As) The layer 2 may be a non-doped type or a thin P type f. However, when it is a thin P type, the built-in pressure Vb
The difference is that the minimum value of i will be slightly lower than the Fermi level. ○Also, when this is consciously controlled, the built-in potential Vbi of the semiconductor stack can be accurately controlled, resulting in a product with high electron mobility. The pinch-off voltage of the transistor can be easily controlled and a high electron mobility transistor with a precise pinch-off voltage can be created.
In order not to inhibit the high electron mobility of the child gas, the impurity concentration should be at least as high as that of the control layer 4.
1 digit is a level that should be kept to a low level 0 See Figure 7.
, ooo X, and then a control electrode (gate electrode) 5 is formed using a photolithography method. 1. The reason for using a high melting point metal is that it can withstand heat treatment at 700 to 800° C. after ion implantation, which is performed in the next step, the output electrode (sonis drain electrode) region. Therefore, if the ion implantation step and the heat treatment step are not used, the control electrode (gate electrode) 5 may be made of aluminum-TIL (A/), etc., and is not essential to the present invention.

Refer to FIG. 8 Using the control electrode (gate electrode) 5 as a mask, silicon (81
) with an energy of 153 KeV and i, 7 X 10”/
The ion implantation is performed with a dose of Cl''.Depending on this energy, silicon (Sl) is implanted into the region shown as 9 in the figure.The purpose of this ion implantation is to form input/output electrodes and two-dimensional electron gas. In order to reduce the contact resistance of Next, a photolithography method is used to remove gold/gold germanium (Au/AuGe) from the input/output electrode (source/P-rain electrode formation region 8). A layer is deposited, heat-treated to alloy it, and the mask used in the photolithography method is removed using the 7-to-7 method except for the input/output electrode (source/drain electrode) region 1.1. Pair of input and output electrodes (source and drain electrodes) 6
complete. The purpose of making the mesa shape as described above is to reduce the contact resistance between the input/output electrodes (source/drain electrodes 6 and the two-dimensional electron gas), so it is not a stupid thing that is not essential to the present invention. In integrated circuits in which many transistors are formed on a single chip, it is desirable to use a planar type as much as possible, so this process is not necessarily desirable. It is desirable to carry out the process under optimal conditions 1 to form a planar type.

The energy number P diagram in the thermal equilibrium state of the enhancement type high electron mobility transistor according to an embodiment of the present invention manufactured as described above is shown in the third diagram.
Mapping as shown in the figure. Here, the control electrode (gate electrode)
When a positive voltage is applied to the electron transit layer 5, an electron group (two-dimensional electron gas) is induced in the electron transit layer 2 near the hetero interface between the electron transit layer 2 and the 79277 layer 3. The thickness of this electron group is extremely small, and it is spatially separated from the control layer 4 containing impurities, so it is not affected by impurity scattering and is kept at low temperatures, such as 77°K, at which impurity scattering prevents an increase in electron mobility. In this case, it is possible to achieve large electron mobility as in the case of conventional high electron mobility transistors.

Here, it must be noted that (a) a potential node exists between the electron transport layer 2 and the node layer 3, and the two-dimensional electron gas flows into the control layer 4. (b) Since the packer layer 3 is a non-doped layer, there is no fear that impurities in the control layer 4 will be diffused into the electron transport layer 2, and the high electron mobility of the conventional It is possible to obtain higher electron mobility than transistors, and (
c) For exactly the same reason, the use of ion implantation in the input/output electrode (source/drain electrode) formation region is permitted without any hindrance; The surface potential of an electron transit layer made of gallium arsenide (GaAs) is determined by the surface potential of an electron transport layer made of gallium arsenide (GaAs), which has a larger energy ear and is substantially impurity-free (in this example, aluminum gallium arsenide). 79277 layers consisting of 3Ga6.
Due to the essence of the present invention that the pinch-off voltage of the enhancement type high electron mobility transistor according to the present invention is controlled by the presence of a control layer made of a type semiconductor (GaAs in Example 1), the pinch-off voltage of the enhancement type high electron mobility transistor according to the present invention is completely controlled. In the above explanation, gallium arsenide (GaAa) and aluminum gallium Although the combination with GaAs is described as an example, several examples of combinations of conductors that can constitute an enhancement type transistor according to the present invention are shown in the table below.
Engineering nAs GaAsSb Engineering nAs2 GaAg
A/GaAsP GaAs3
Engineering nP Engineering nGa5b
InP As explained above, according to the present invention, electrons spatially separated from the semiconductor layer containing impurities are generated near the hetero interface formed by combining two or three types of conductors with different energy sources. group (two-dimensional electron gas)
is induced, a high electron mobility transistor Wb is formed using this group of electrons as a conductive medium, and the semiconductor layer directly adjacent to the conductive medium is doped with an impurity. Is it possible to provide a high-electron-mobility transistor having a novel layer structure with improved electron mobility compared to the conventional one without the need for high-electron-mobility transistors? Wear.

[Brief explanation of drawings]

Fig. 1 is a conceptual cross-sectional view 1 of a high electron mobility transistor according to an embodiment of the present invention, Figs. 2 and 3 are energy node diagrams in its thermal equilibrium state, and Figs. 4 and 5 are: This is a graph showing the relationship between the pinch-off voltage and the thickness of the control layer (there is a graph showing the thickness of the control layer necessary to set the pinch-off voltage to 0). 6.7.8.9 are cross-sectional views of a substrate at main stages of the manufacturing process of an enhancement type high electron mobility transistor according to an embodiment of the present invention. 1...Chromium-doped semi-insulating gallium arsenide substrate, 2...Electron transit layer (gallium arsenide single crystal layer with low impurity content), 3...Nexus layer ( Aluminum gallium arsenide single crystal layer that does not substantially contain impurities), 4... Control layer (N-type gallium arsenide single crystal layer), 5... Carbon dioxide/# rear type control Electrode (gate electrode fi), 6...1 pair of input/output type 1f# (source/P rain electrode), 7... Alloyed area completed, mu...
・Fermi level, B, B'...Valence band level, 0.0'...Conduction level, Vbi...Built-in potential of the conductor laminate, vl...Arsenide gallium with low impurity content Surface potential of Gourd layer 2, v
2... Potential drop in the aluminum gallium arsenide layer 3 that does not substantially contain impurities, v3...
・Surface potential of N-type gallium arsenide N4, 8.
・・Input/output electrode (source/P-rain electrode) formation area,
9...Ion implanted region 0N-G4AsJ thickness

Claims (3)

[Claims] (1) A medium insulating substrate, an electron transit layer formed on the substrate and made of a semiconductor single crystal layer with low impurity content,
a notch layer formed on the electron transit layer and consisting of a single crystal layer of a semiconductor having an energy gap larger than that of the semiconductor forming the electron transit layer and containing no impurities; a control layer formed on the 7th layer and made of a single crystal layer of an N-type semiconductor having an energy gap not larger than the energy gap of the semiconductor forming the electron transport layer; at least one control electrode provided;
a pair of input/output electrodes provided in mutually opposing regions sandwiching the control electrode on another part of the surface of the control layer or a part of the surface of the electron transport layer; In the layer structure, the size of the energy gap, the thickness, and the impurity concentration of the control layer are selected so that the surface potential between the electron transport layer and the 9-layer layer is O (zero), A semiconductor device in which a group of electrons is emitted in the vicinity of a hetero interface between the electron transport layer and the anti-transfer layer by a positive voltage applied to the control electrode, thereby functioning as an enhancement type transistor. (2) A patent characterized in that the lower regions of the l pairs of input and output electrodes contain a high concentration of N-type impurity up to the electron transport layer, and the control electrode is made of a high melting point metal. A semiconductor device according to claim 1. (3) The semiconductor device according to claim 1 or 2, wherein the control layer and the notch layer are removed in the pair of input/output electrode regions.