JPS584460A - Automatic verifying device for program - Google Patents

Abstract

PURPOSE:To automatically verify a test program, depending whether a test program in a computer normally detects an equivalent error or not by generating the equivalent error from the computer with a data from a service processor. CONSTITUTION:A service processor 2 is provided with an address generating section 33, a data generating section 31 and a timer 24 stopping a computer for a prescribed time. The computer executed with a test program from the service processor is stopped by said timer 24 for a prescribed time and an error is generated equivalently by writing a data from said data generating section 31 to at least one of a memory 67 or an input and output device designated with said address generation section 33 while the stopping. After a prescribed time, a computer 1 is restarted, and said equivalent error is detected with the test program to detect if the test program normally detects errors

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention automatically verifies whether or not the computer system performs correctly, and furthermore, automatically verifies a test program to find out where the fault is if the system does not perform correctly, i.e. there is a fault. related to a device for

Previously, Maemisaki test! Verification of log 2m was done manually. That is, run the test program, for example, 4. The bottle of cupane is logically @O” by hand.

- causing a human failure and determining whether the test fa Datsum correctly points out the human failure location;
However, there are various problems with the above method.The first problem is the occurrence of human failures due to manual intervention.
It is. In other words, when rounding is done manually, for example, the bin number on the d-tsuku panel is incorrectly rounded, there are multiple roundings, and so on.
When using a WA, there are fewer
), the second problem is that it takes a lot of time due to manual intervention, especially when creating complex failures.

In view of the above-mentioned conventional problems, the present invention improves an automatic test f-gram verification device that automatically performs test program verification by using a test program verification service that has conventionally been performed manually. With the goal.

This special feature is achieved by providing the service ftx sensor with an address generation section, a data generation section, and a tie that stops the combination for a certain period of time.
The test f-Datsum is executed by Rossenna, and the input/output main phone or memory specified by the address generator is stopped for a certain period of time by the tie i. By writing the generated data to at least one of the data seller's main phones, an equivalent error is generated, and after a certain period of time, the combination is returned to -
Restart the evening, use the test frodatum to detect the equivalent error generated by the above writing, and verify whether the test llogzum correctly detected the error. An object of the present invention is to provide an automatic verification device.

Hereinafter, one embodiment of the actual Ij 10 will be described in detail with reference to page 111.

In the first diagram, a computer 1 and a service gross set t (hereinafter referred to as 8V'P) 2 are connected to an address bus 3 and a data bus 4.
, start signal line 5, strike,! Connected by signal line 6, error status II 7, and signal line 8.

FIG. 2 shows the process of the present invention 1M71:1-, which starts from the start Stella f9 and prepares the write destination address and data by 8VP2, 7"l
This preparation step 1G prepares to output the first address and data of the error occurrence to the address bus 3 and data bus 4, respectively. When this preparation step flG is completed, the test Execute the fa program execution step, fll. This operation is performed from the start signal line sK to the 0th order, 8VP
In step 7"l, the test fμ is temporarily stopped after a predetermined time according to the timer of No. 2.
The time from l to the temporary stop step 121 is aVP
Thailand in Z! Set by. Data writing step 13 is performed by the 8VP 2 during the temporary suspension of the test program. In the write operation step 13, the data prepared in the preparation step 1O in 8VP2 is stored at a location designated by a similarly prepared address. The write operation is completed and 8V
'When the timer in the PR reaches the test fa data sum execution time, the test f log sum O execution 14 is performed. Execution of the test frodatum is resumed from where it was paused. If the test frodatum is executed again and an error occurs, the test fadatum will detect the error occurrence.
15 and performs error detection. If an error is detected, Stella f stores the error contents in memory.
Error details are logged in step 16. test! In Rodatsum, since Day I changed during execution, it is assumed that an error has occurred. Tate in said action!・Even if there is no abnormality in the Datsum, there may be cases where the error is not detected.
Errors are detected in most cases except for special registers such as the input/output device O status register. However, test fa datum pada ie! - If there is a gram error, etc., the error may not be detected. When error detection is completed, the next step is to prepare the write destination address and data for writing.

17. Once this preparation is complete, test again.
Run LogTsum. Thereafter, the above operations are repeated in sequence.

FIG. 3 shows computers 1 and 8V! of the verification apparatus according to the present invention. ' 2 O is a diagram showing a specific configuration. The key is -
180 output 19 is connected to a first input 21 of control circuit 20. Key? - When a predetermined start button on the keypad 18 is pressed, a start output 22 of the control circuit 20 is generated, and this output is used as a start output 23 of the central processing unit CPU.
Start timer 24 enters human power 25. The stop, f output 26 of tie ff24 is applied to the stop input 27 of the CPU. A tie with the same polarity as the octopus strug output 26! 24
The r-)on output 28 of the unrr-tom 1. A2 is connected to each of the tenth amplifiers Pr-) 29.30. Data generation $310 output 32 is sent to the second r-to 35 of AND r-tom 2, and output 34 of address generator 33 is sent to 77
1'? -) A 101111t201" -t3・
are connected to each. An1'ff-) Ml.

Output line driver/receiver for System 2! 7O human power 38°39
and a resistor force of 400 Å and a force of 41.4 m, respectively. Driver registers 4370/f buses 43 and 44 are connected to data bus 4 and address bus 3 of computer 1, respectively. The discrimination output 46 of the driver register d37 is applied to the discrimination input 47 of the discrimination circuit 45, and the discrimination circuit 4SO output 48 is applied to the input 49 of the data generation section 31 and the address generation section 3.
30 inputs 50. Ann Y? ”-)Mu3.Mu4
The error signal line 8 is connected to 51.52 of 0@l. The output s3 of the register 40 is applied to the second gate 54 of the ANDGUTOM 4, and the F-Status line 7 is connected to the ANDR-)MU StV second r-)s!!. 3. M40 output 56, 57tl'
*Followed by 580 people and 59.60%. Output of memory 58/1 Expansion device 6 Input 63 of Glinter, etc.
The input and output terminals 64 of the output device 2 are applied to the 20th human power 65 of the control circuit 2°. The data bus 4 of the computer 1 includes a CPU, a storage 66, and a memory 67.
, a display device 68 are connected, and the address bus 31 is connected to a CP
U, f:z-/69, 70 display device 68, memory 6
7 is connected. Further, the error signal line 8 is connected to the cpv error signal input cuff 1. Or? -) The output cuff 21 of 72 is connected. Processing device 739, for example, input/output device, auxiliary storage device OAV Tichi, Tsuk circuit 74.7! l is reso staff 6
connected to each bit of Output 7 of register '16 is connected to output 2-status line 7. The output of each bit in the register 76 is OR'd by r-) 720 and each r-)K is added.

The processing unit 730 processing section 78 is connected to the register 66, ΔLitiet/1lj174.7.5.

When a start message is received from key 1g, the control circuit 2o determines that it is a start and starts the CPU. The test program stored in the memory 67 is executed by the CPU. Further, the control circuit 2
0d tie-v24 starts its timing. After the preset time elapses in the timer 24, C
It outputs the strike and f signals to the PH, and turns on the AND GOUTOM 1.degree. 20 gate, that is, turns it 111. When the gate is turned ON, the address generation section first calculates the first address value and data value by un1i'? ”-)
Mu1. output to the dry receiver 37 via the system 2,
Output the address value and data value to the driver letter/43F Hiropath Twin. At the same time, the value is stored in the register 40. When the data is written to the register 40, Δritichi, ivy circuit 74.7! ! FiΔritietsu-72 is output to the reso staff 6. Reso Stuff 6
Then, store the above Δritietsu-7 lag, or r-)7
! Output to. The OR gate 72 outputs an error detection result to the output T1!1 if even one of the contents (bits) of the reso-staff 6 becomes l. Cuff out! Since it is connected to the la etsu signal line 8, the CPUK outputs the error detection result, and also outputs the error detection result. Turn on 4t. Andr-)mu3. When the system 4 is turned on, the data value and address value written to the register 66 stored in the register 40 and the detection result stored in the resistor 6 are stored in the memory 58. Ru. The contents of the memory are outputted to an output device, and when the output is completed, a signal is outputted that causes the control circuit 6s to perform the next verification.

The above operation is performed by the data generating section 31 and the address generating section 33.
It is repeated for all the preset amount of data.

As explained above, according to the test fa-gram automatic verification device according to the present invention, verification of test fa-grams, which was conventionally performed manually, is automatically performed, and not only can the verification time be shortened, but also the verification time can be reduced manually. This eliminates the need for operating chairs. In other words, by writing data in the ``8VP2t'' area and generating an error equivalently, the test fa-gram generates the equivalent error. It is possible to provide a device that can automatically verify a test program depending on whether or not it is detected.

In the above description of the invention, everything is tested! Although the explanation has been made using Rodarum, the present invention can also be used in a troubleshooting procedure using 8VP.

[Brief explanation of the drawing]

Fig. 1 is a conceptual diagram of an embodiment of the present invention, Fig. 2 is a diagram illustrating the process 70- according to the present invention, and Fig. 3 is an ivy diagram of the automatic verification device of the present invention. Calculator, 2-Service Fa Sessa (tm), 24...Tie! , 31-...
Data generation section, 33--Address generation section.

Claims (1)

[Claims] An address generator that generates an address, a data generator that generates data, and a certain period of time; a tie that stops the voice! and 13. stopping the combination machine on which the fa dam is being executed for a certain period of time according to the timer;
generating an equivalent error by writing the data generated (by the data generator) to at least one of the nine output devices or the printer specified by the address generator while the address generator is stopped; After a certain period of time, restart the combination and let the fgI gum detect the error caused by the write K!
Verify whether Rodalum has correctly detected errors! Logzum automatic verification device.