JPS5843553A - マルチチツプｌｓｉパツケ−ジ - Google Patents

マルチチツプｌｓｉパツケ−ジ

Info

Publication number
JPS5843553A
JPS5843553A JP56141934A JP14193481A JPS5843553A JP S5843553 A JPS5843553 A JP S5843553A JP 56141934 A JP56141934 A JP 56141934A JP 14193481 A JP14193481 A JP 14193481A JP S5843553 A JPS5843553 A JP S5843553A
Authority
JP
Japan
Prior art keywords
chip
wiring layer
multilayer
hole
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56141934A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6135703B2 (enExample
Inventor
Toshihiko Watari
渡里　俊彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56141934A priority Critical patent/JPS5843553A/ja
Publication of JPS5843553A publication Critical patent/JPS5843553A/ja
Publication of JPS6135703B2 publication Critical patent/JPS6135703B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/647—Resistive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP56141934A 1981-09-08 1981-09-08 マルチチツプｌｓｉパツケ−ジ Granted JPS5843553A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56141934A JPS5843553A (ja) 1981-09-08 1981-09-08 マルチチツプｌｓｉパツケ−ジ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56141934A JPS5843553A (ja) 1981-09-08 1981-09-08 マルチチツプｌｓｉパツケ−ジ

Publications (2)

Publication Number Publication Date
JPS5843553A true JPS5843553A (ja) 1983-03-14
JPS6135703B2 JPS6135703B2 (enExample) 1986-08-14

Family

ID=15303540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56141934A Granted JPS5843553A (ja) 1981-09-08 1981-09-08 マルチチツプｌｓｉパツケ−ジ

Country Status (1)

Country Link
JP (1) JPS5843553A (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02119164A (ja) * 1989-09-20 1990-05-07 Hitachi Ltd 半導体モジユール
US5045922A (en) * 1989-09-20 1991-09-03 Hitachi, Ltd. Installation structure of integrated circuit devices
JP2002111222A (ja) * 2000-10-02 2002-04-12 Matsushita Electric Ind Co Ltd 多層基板
JP2007165932A (ja) * 2007-02-22 2007-06-28 Matsushita Electric Ind Co Ltd 多層基板

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02119164A (ja) * 1989-09-20 1990-05-07 Hitachi Ltd 半導体モジユール
US5045922A (en) * 1989-09-20 1991-09-03 Hitachi, Ltd. Installation structure of integrated circuit devices
JP2002111222A (ja) * 2000-10-02 2002-04-12 Matsushita Electric Ind Co Ltd 多層基板
JP2007165932A (ja) * 2007-02-22 2007-06-28 Matsushita Electric Ind Co Ltd 多層基板

Also Published As

Publication number Publication date
JPS6135703B2 (enExample) 1986-08-14

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