JPS5842244A - 半導体チツプとその支持体との結合方法 - Google Patents

半導体チツプとその支持体との結合方法

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Publication number
JPS5842244A
JPS5842244A JP57142568A JP14256882A JPS5842244A JP S5842244 A JPS5842244 A JP S5842244A JP 57142568 A JP57142568 A JP 57142568A JP 14256882 A JP14256882 A JP 14256882A JP S5842244 A JPS5842244 A JP S5842244A
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Japan
Prior art keywords
semiconductor chip
support
bonding
chip
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57142568A
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English (en)
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JPH0230576B2 (ja
Inventor
ラデイム・バダレツク
ウエルナ−・バウムガルトナ−
ダフイツト・クツタ−
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Schuckertwerke AG
Siemens AG
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Siemens Schuckertwerke AG
Siemens AG
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Application filed by Siemens Schuckertwerke AG, Siemens AG filed Critical Siemens Schuckertwerke AG
Publication of JPS5842244A publication Critical patent/JPS5842244A/ja
Publication of JPH0230576B2 publication Critical patent/JPH0230576B2/ja
Granted legal-status Critical Current

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    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
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    • H01L2924/1204—Optical Diode
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は半導体テップとその支持体とを接着又はろう付
けｆ二よって結合する方法に関する。
例えば集積半導体回路又は高出力半導体デバイスの半導
体チップはその一面を金属支持板又は金属化されたセラ
ミック支持板６二ろう付けするか接着剤で接着する。こ
の結合個所は機械的≦二頑丈であって負荷の変動が繰り
返されて半導体チップと支持体との間にせん断応力が生
じても破壊されないようになっていなければならない、
更にチップ支持体は同時に冷却体となるかあるいは適当
な冷却体に熱を運ばなければならないから、チップとチ
ップ支持体との間にできるだけ低い熱伝達抵抗が再現性
良く作られるものでなければならない。
本発明の目的は、最良の永続性を持つと同時に低い熱伝
達抵抗を再現性よく達成することができる半導体チップ
とその支持体との結合方法を提供することである。
この目的は本発明によれば半導体チップと結合面とをレ
ーザー光線で処理し、その際レーザー光線のエネルギー
を半導体材料の局部的の溶融によって凹みが作られ、溶
融した半導体材料が少くとも部分的に凹みの縁に押し上
げられるような値に選ぶことによって達成される。
図面を参照し、いくつかの工程パラメータな採用して本
発明を更に詳細に説明する。
イオン注入、拡散、エツチング等の通常の工程段階を経
た半導体チップに対してその支持体と結合する面にレー
ザー元を照射する。レーザー元は例えばパルス動作のＮ
ｄ：ＹＡＧ　　（ネオジム：イツトリウム・アルミニウ
ム・ガーネット〕レーザーから発生させる。レーザーに
加えるエネルギーは例えばシリコン半導体板に深さ２な
いしｌＯμ島、直径５０ないし２００μ賜のクレータが
作られるように選ぶ。このようなりレータは例えば同波
数４ｋＨ！、約５０Ｗの出力を導くことによって作るこ
とができる。レーザー党ビームがシリコン表面に当ると
、シリコンを溶融しクレータから外方に融体を飛散させ
る。これによってクレータを取巻いて高さ２ないし１０
μ屏の盛り上りができる、溶融はアルゴン、窒素等の保
護ガス又は酸素のような反応性ガス中で行ってもよい。
このようにして作られたクレータの断面を図面に示す。
１は照射によって作られたシリコン表面であり、２はそ
こに作られたクレータ、３はクレータを取巻く盛り上り
である。クレータの深さと盛り上りの高さは元のシリコ
ン基板の最高点を結ぶ線４を基準にして計る。クレータ
の幅又は直径も線４で表わされた表面において計ったも
のである。
半導体チップと支持体との間の良好な結合を達成するた
め１：は総ての凹み２の面積の、レーザーで処理されな
かった半導体チップ面に対する比率ヲ少くトも３０チ近
くにすることが必要である。
これによってろう又は接着剤が半導体チップ表面に十分
強く付着しチップと支持体との間の強固な結合が達成さ
れる。盛り上り３は半導体チップと支持体との間に一定
の間隔を保持し、熱伝達抵抗値の再現性を良くする。半
導体チップと支持体との間に残された間隙は良伝導性の
接着剤又はろうで埋める。半導体チップの結合面の全体
を結合に先立って金属化すると一層効果的である。これ
によって熱伝達抵抗が低くなり電気接触性が改善される
。
【図面の簡単な説明】
図面はレーザー元によって処理された半導体チップ面の
断面形状を示す説明図である。 １・・・処理後の表面、　２・・・クレータ、　　３・
・・盛り上り、　　４・・・チップの原表面。

Claims (1)

  1. 【特許請求の範囲】 ｌ〕　接着またはろう付けによって半導体チップとチッ
    プ支持体とを結合する方法において。 半導体チップの結合面をレーザー光線で処理し、その際
    レーザー光線のエネルギーを半導体チップ材料が局部的
    に溶融して凹みが作られ溶融した半導体材料が少くとも
    部分的に凹みの縁に押し上げられる値に選定することを
    特徴とする半導体テップとその支持体との結合方法。 ２、特許請求の範囲第１項記載の結合方法において、凹
    みが直径５０ないし２００μ島、深さ２ないし１０μ搗
    であり、押し上げられた半導体材料が２ないし１０μ鳩
    の高さとなることを特徴とする半導体チップとその支持
    体との結合方法。 ３】　特許請求の範囲第１項または第２項記載の結合方
    法において、パルス発振のＮｄ：ＹＡＧレーザーが使用
    されることを特徴とする半導体チップとその支持体との
    結合方法。 ４】　特許請求の範囲第１項〜第３項のいずれかＣ二記
    載の結合方法において、保護ガス又は反応性のガスを使
    用して溶融を実施することを特徴とする半導体チップと
    その支持体との結合方法。 ５〕　特許請求の範囲第１項〜第Ｅ項のいずれかＣ二記
    載の結合方法において、レーザー処理の後結合面を金属
    化することを特徴とする半導体チップとその支持体との
    結合方法。
JP57142568A 1981-08-20 1982-08-17 半導体チツプとその支持体との結合方法 Granted JPS5842244A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19813132983 DE3132983A1 (de) 1981-08-20 1981-08-20 Verfahren zum verbinden eines halbleiterchips mit einem chiptraeger
DE3132983.7 1981-08-20

Publications (2)

Publication Number Publication Date
JPS5842244A true JPS5842244A (ja) 1983-03-11
JPH0230576B2 JPH0230576B2 (ja) 1990-07-06

Family

ID=6139751

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57142568A Granted JPS5842244A (ja) 1981-08-20 1982-08-17 半導体チツプとその支持体との結合方法

Country Status (4)

Country Link
US (1) US4746390A (ja)
EP (1) EP0072938B1 (ja)
JP (1) JPS5842244A (ja)
DE (2) DE3132983A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008282834A (ja) * 2007-05-08 2008-11-20 Fuji Electric Device Technology Co Ltd 半導体装置の製造方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4861407A (en) * 1985-06-18 1989-08-29 The Dow Chemical Company Method for adhesive bonding articles via pretreatment with energy beams
US4968383A (en) * 1985-06-18 1990-11-06 The Dow Chemical Company Method for molding over a preform
DE3725269A1 (de) * 1987-07-30 1989-02-09 Messerschmitt Boelkow Blohm Verfahren zum einkapseln von mikroelektronischen halbleiter- und schichtschaltungen
US5314003A (en) * 1991-12-24 1994-05-24 Microelectronics And Computer Technology Corporation Three-dimensional metal fabrication using a laser
DE4235908A1 (de) * 1992-10-23 1994-04-28 Telefunken Microelectron Verfahren zum Verlöten eines Halbleiterkörpers mit einem Trägerelement
AU5416694A (en) * 1992-10-28 1994-05-24 Jorg Meyer Metal-plastic composite, process for producing it and apparatus for carrying out the process
US20020170897A1 (en) * 2001-05-21 2002-11-21 Hall Frank L. Methods for preparing ball grid array substrates via use of a laser
US8802553B2 (en) 2011-02-10 2014-08-12 Infineon Technologies Ag Method for mounting a semiconductor chip on a carrier
JP6441295B2 (ja) * 2016-12-26 2018-12-19 本田技研工業株式会社 接合構造体及びその製造方法
JP2022001255A (ja) 2020-06-19 2022-01-06 ザ エルゴ ベビー キャリア， インコーポレイテッド 複数の担持向きを有する調節可能チャイルドキャリア

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JPH0230576B2 (ja) 1990-07-06
EP0072938B1 (de) 1986-12-03
EP0072938A2 (de) 1983-03-02
EP0072938A3 (en) 1985-01-09
DE3132983A1 (de) 1983-03-03
US4746390A (en) 1988-05-24
DE3274600D1 (en) 1987-01-15

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