JPS5839336A - インラインシステムにおける子機のメモリクリア処理方式 - Google Patents

インラインシステムにおける子機のメモリクリア処理方式

Info

Publication number
JPS5839336A
JPS5839336A JP56137928A JP13792881A JPS5839336A JP S5839336 A JPS5839336 A JP S5839336A JP 56137928 A JP56137928 A JP 56137928A JP 13792881 A JP13792881 A JP 13792881A JP S5839336 A JPS5839336 A JP S5839336A
Authority
JP
Japan
Prior art keywords
memory
slave
unit
data
slave unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56137928A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6138513B2 (https=
Inventor
Masayuki Sumimoto
住本　正幸
Soichi Onishi
大西　荘一
Fusahiro Shiono
塩野　房弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP56137928A priority Critical patent/JPS5839336A/ja
Publication of JPS5839336A publication Critical patent/JPS5839336A/ja
Publication of JPS6138513B2 publication Critical patent/JPS6138513B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Cash Registers Or Receiving Machines (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
JP56137928A 1981-08-31 1981-08-31 インラインシステムにおける子機のメモリクリア処理方式 Granted JPS5839336A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56137928A JPS5839336A (ja) 1981-08-31 1981-08-31 インラインシステムにおける子機のメモリクリア処理方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56137928A JPS5839336A (ja) 1981-08-31 1981-08-31 インラインシステムにおける子機のメモリクリア処理方式

Publications (2)

Publication Number Publication Date
JPS5839336A true JPS5839336A (ja) 1983-03-08
JPS6138513B2 JPS6138513B2 (https=) 1986-08-29

Family

ID=15209956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56137928A Granted JPS5839336A (ja) 1981-08-31 1981-08-31 インラインシステムにおける子機のメモリクリア処理方式

Country Status (1)

Country Link
JP (1) JPS5839336A (https=)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5734082U (https=) * 1980-08-07 1982-02-23
JPS57172465A (en) * 1981-04-15 1982-10-23 Tokyo Electric Co Ltd On-line cash register

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5734082U (https=) * 1980-08-07 1982-02-23
JPS57172465A (en) * 1981-04-15 1982-10-23 Tokyo Electric Co Ltd On-line cash register

Also Published As

Publication number Publication date
JPS6138513B2 (https=) 1986-08-29

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