JPS5836003A - Digital oscillator - Google Patents

Abstract

PURPOSE:To reduce the coefficient precision for deciding on an oscillation frequency by modulating the output of a digital oscillator, using secondary cyclic digital filter, at a quarter frequency as high as a sampling frequency, and extracting only a low frequency component from the modulated signal. CONSTITUTION:An input signal to the 1st delay device 1 is led to a modulator 7, which modulates the input by a modulating wave having a period four times as long as a signal of sampling frequency fs. The output signal of the 1st delay device 1 is modulated by the 2nd modulator 8 when the digital value sequence phi1 which lags a digital value sequence phi0 in phase by pi/2. The output signal of the 2nd delay device 2 is modulated similarly by the 3rd modulator 9 with a sequence phi2 which further lags the sequence phi1 by pi/2. The output of the modulator 8 is multiplied by a coefficient alpha1 through the 2nd multiplier 10, and the output of the modulator 9 is multiplied by a coefficient alpha2 through a multiplier 11. The outputs of the multipliers 10 and 11 are added together by the 3rd adder 12, whose output is supplied to an adder 13, which adds the input to the output of the modulator 7. The coefficients alpha1 and alpha2 are set adequately to remove an unnecessary frequency component from the modulator 7 in the output value of the adder 13.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit structure of a digital oscillator using a cyclic digital filter.

With the digitization of communication devices, it has become important to generate sine waves used for modulation and demodulation as digital signals. A first method for generating a digital sine wave is to store sample values obtained by sampling a sine wave at regular intervals in a memory, and to sequentially read out the contents of the memory at each sampling period. This method, called the table method, is simple, but has the disadvantage that it requires a large amount of memory if the ratio between the generation frequency and the sampling frequency is an irrational number. Therefore, conventionally, a digital type vibrator using a second-order cyclic circuit as shown in FIG. 1 has been used. The generator 4 has a first delay 1 and a second delay 2 connected in series, each having a delay time of 6 equal to the sampling period.
The output of the delay device 1 is multiplied by the coefficient b1 in the first multiplier 3, and the output of the 2KS2 delay device 2 is multiplied by the coefficient b2 in the multiplier 4. Then, the outputs of the multipliers 3 and l[ are weighted by the first addition 'fi' and the multiplier 5. The output of the 17th III multiplier 5 is added to the input impulse in the second adder 6 and connected to the input of the first delay device 1. 1. After clearing the contents of the second delay circuits 1 and 2, a digital sine wave can be oscillated by applying an input impulse to the second adder 6.The oscillation frequency f of this oscillator and sampling The relationship with 8 in terms of frequency is that the coefficient S is set to 1 and is constant, so by appropriately setting the coefficient S, it is possible to oscillate at any frequency. However, such a conventional digital oscillator has an oscillation frequency f compared to the sampling frequency f8. When is extremely small, there is a drawback that the oscillation frequency fo varies greatly due to a slight difference in the coefficient b1 for reasons described later.

Therefore, in order to obtain the desired oscillation frequency, the coefficients are calculated.

It is necessary to define precisely. In other words, it is a coefficient.

It is necessary to make the coefficient word length representing the value sufficiently long, which results in an increase in hardware.

The oscillation frequency f0, the sampling layer θν number f8, and the coefficient S...
b, there is a relationship given by the following equations (1) and (2).

b+=2C082πfo/f, (1) b, -
1 (2) Therefore, the oscillation frequency f when the coefficient S is changed by db. If the change in is dfo, then the sensitivity to f and no can be expressed as: θ=2πt0/l, (4). That is, when θ is 1, ain θ in equation (3) becomes small, so the sensitivity becomes extremely high. For example, when fs = 100 Hz and f, = 2I (2), in order to suppress the fluctuation of fO within 10-4, it is necessary to suppress the adjoining error of the square to 1.6×10' or less.

This means that the coefficient word length is about 19 bits. Note that since the coefficient bt is 1, there is no particular need to provide the multiplier 4, and it is sufficient to leave it through.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital oscillator which can solve the above-mentioned conventional drawbacks and can significantly reduce the coefficient word length compared to the conventional circuit.

The oscillator of the present invention includes a cascaded circuit of a first delay device and a second delay device having a delay time equal to a constant sampling period, and a first multiplication circuit that multiplies the output of the first delay device by a constant coefficient. a first adder that adds the output of the first multiplier and the output of the second delay device, and adds the input impulse and the output of the first adder and inputs the result to the first delay device. Second
an adder, the digital oscillator generates a digital sine wave of an arbitrary frequency corresponding to a coefficient to be input to the first multiplier; A first modulator that modulates a modulated wave with a period twice as long as the modulated wave, and an output signal of the first delay device that is pπ/
a second modulator that modulates with a modulated wave whose phase is delayed by 2;
The output signal of the second delay device is further π/
a third modulator that modulates with a modulated wave whose phase is delayed by 2;
a second multiplier that multiplies the output of the second modulator by a certain coefficient; a third adder that adds the output of the second multiplier and the output of the third modulator; and the third adder. and a fourth adder for adding the output of the first modulator and the output of the first modulator, and the output of the fourth adder generates a digital sine wave of a desired period.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing one embodiment of the present invention. That is, as in the conventional case, the first delay device 1 and the second delay device 2
are connected in cascade, and the output of the first delay device 1 is multiplied by a coefficient β in the first multiplier 3. The delay times of the first and second delay devices are equal to the sampling period T, that is, the reciprocal of the sampling frequency fs. Then, the 1[1 power of the first multiplier 3 and the second delay device 2
The output of the first adder 5 is added to the human impulse in the second adder 6. Second addition? 4. The output of the device 6 is connected to the input of the first delay device 1. However, in this embodiment, for example, the sampling frequency af
s is 1. When you want to obtain a 2■I2 sine wave using OOIT, it, -, 1: Oscillation frequency f to be oscillated by the above-mentioned component. Coefficient β so that becomes 23H2.

Set. Then, the nucleus 23H2 is (1
00T (4 times the number of laps of 7) 25H2, change le 1M and 2
After obtaining the modulated output signal of 23H, 5, and 23H, unnecessary components are removed and the component of 2H7 is output.

That is, when the first Ilu <+ is set, the first input signal is
The modulator 7 is operated manually and modulated with a modulated wave having a cycle four times the sampling frequency fB. The modulation with the fourth modulator 7
This can be easily done by inputting a digital value of 10"11"o-pi for each sample substitute and multiplying it by the input signal of the delay device 1, as shown in FIG. The above digital value series is φ. That's what I will say. The digital value series φ. However, since the values are only "1", "0" and "-1#," the modulator 7 can be easily constructed using, for example, a sign inversion circuit and a gate, without using a multiplier. The output signal of the first delay device 1 is converted to the digital value series φ by the second modulator 8.
It is modulated by a digital value sequence φ1 as shown in FIG. 4(b) in which the phase is thickened by . Further, the output signal of the second delay device 2 is similarly modulated by the third modulator 9 using the digital value sequence φ, and the sequence φ delayed by π/2 (see FIG. 4(c)).

Then, the output of the second modulator 8 is multiplied by a coefficient α in the second multiplier 10, and the output of the third modulator 9 is multiplied by the coefficient α.
is multiplied by the coefficient α. The outputs of the multipliers 10 and 11 are added by a third adder 12;
The output of the modulator 2 is input to the fourth adder 13 and added to the output of the first modulator 7. The above coefficient α1. If α is set appropriately, the output value of the fourth adder 13 will be the same as that of the first modulator 7.
From the output of 5 frequency components can be removed.

For example, in the above example, the component 25+23H7 can be removed and only the component 25-23=2FI2 can be output. That is, there is a low-pass filter effect, and its attenuation characteristics are determined by the coefficient α1. Sufficient damping can be obtained by setting α2 to, for example, 2 and 1, respectively. Therefore, the multiplier 10 may be configured with a simple shift circuit, etc.
It is also possible to pass through the multipliers without providing 11 multipliers.

FIG. 3(a) shows the spectrum of the input signal of the first delay device 1 (that is, also the input signal of the first variable frequency converter 1, 1 device 7), and the sampling frequency t, = 1.00 Hz - modulation The case where the frequency is 25T (7 (100IT, /4) and the oscillation frequency f is 23Hz is shown.Modulation frequency 2
The period of 57(, is the sampling frequency fa (J 00Hz
), the angular frequency of the modulation frequency 25H3 is π/2, and the angular frequency of the oscillation frequency 23) ) is small, so its spectrum becomes as shown in FIG. 3(a)K. This signal is a sine wave with an angular frequency of π/2 (25H
2), the variable N,' is the angular frequency! ±(u-e
) signals are obtained. Therefore, as shown in FIG. 3(b), the spectrum of the output signal of the first modulator 7 is as follows:
Book, disrupting the glandular spectrum. On the other hand, when the coefficients α and α2 are set to 1.9 and 1, respectively in FIG. 2, the fourth addition J! [13] A signal near the angular frequency π is attenuated and outputted, and its attenuation characteristic is as shown in curve c in FIG. 3(b). Therefore, the signal (25, H8+23H,) near the angular frequency π is removed, and only the signal (2H7) with the angular frequency e is output from the fourth addition band 13.

In the above, in order to set the oscillation frequency f0 to 23H7, the coefficient β is determined by β1=2cos2π from the equation (1) above.
f 6 / r B, and from equation (4), θ
=2π 23 From the equation (3), the sensitivity of the oscillation frequency fo to β is as follows. Therefore, the accuracy of the pot β required to suppress the fluctuation of fo within 10-4 is 1. 1jy is sufficient for lX10''-3. In other words, the coefficient word only requires about 10 bits, which can be significantly reduced compared to the 19 bits required in the conventional circuit. The containers, feeders, etc. can also be made smaller, and the overall effect is that less hardware is required.

As shown above, in the present invention, the output of a conventional digital oscillator using a second-order delay dish digital filter is
It is configured to modulate at a frequency that is 1/4 of the sampling frequency, remove high frequency components from the modulated signal, and output only low frequency components. In cases where output is desired, the precision of the coefficients for determining the excavation frequency can be reduced. That is, the coefficient word length can be reduced, and the circuit scale can be significantly reduced compared to the conventional method.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an example of a conventional digital oscillator.
Figure 2 is a circuit diagram showing an embodiment of the present invention, Figure 3 (,)
is a diagram showing the spectrum of the modulator input in the above embodiment, FIG. 3(b) is a diagram showing the spectrum of the modulator output and a diagram showing the attenuation characteristic at the output neck of the fourth adder, ), (b) and (c) are diagrams showing modulation signals input to the first to third modulators, respectively. In the figure, 1...first delay device, 2...second delay device, 3...first multiplier, 4...multiplier, 5...first
adder, 6... second adder, 7... first modulator,
8... Second modulator, 9... Third modulator, 10...
Second multiplier, 11... Multiplier, 12... Third adder, 13... Fourth addition Ri, blpb7. β1, β7
．． α1. α, ... coefficient. Representative Patent Attorney Sumi 1) Sou Toshi

Claims (1)

[Claims] a cascaded circuit of a first delay device and a second delay device having a delay time equal to a constant sampling layer 1υj; a first multiplier that multiplies the output of the first delay device by a constant coefficient;
a first adding the output of the multiplier and the output of the second delay device;
an adder; and a second adder that adds the input impulse and the output of the first adder and inputs the result to the first delay device; a first modulator that modulates the input signal of the first delay device with a modulation wave having a period four times the sampling period;
a second modulator that modulates the output signal of the delay device with a modulation wave whose phase is delayed by π/2 from the modulated wave; and a second modulator that modulates the output signal of the second delay device with a modulation wave whose phase is delayed by π/2 from the modulated wave. a third modulator that modulates with a delayed modulation wave; a second multiplier that multiplies the output of the second modulator by a constant coefficient; a third adder that adds the output of the third adder and the output of the first modulator; and a fourth adder that adds the output of the third adder and the output of the first modulator; A digital oscillator characterized by generating a sine wave.