RU8856U1 - DIGITAL FREQUENCY SYNTHESIS - Google Patents

Abstract

A digital frequency synthesizer comprising a controlled oscillator connected in a ring, a frequency divider with a variable division coefficient, a frequency-phase detector and a first low-pass filter, a reference oscillator and a frequency divider with a fixed division coefficient, the output of which is connected to the second input of the frequency-phase detector in series characterized in that, in order to increase the suppression of spurious frequency modulation while increasing the speed, series-connected the second integrator, the first adder, the inverter and the controlled phase shifter, the phase shifter connected to π / 2, the phase detector, the second low-pass filter and the second adder, the output of which is connected to the second input of the first adder, and the second input of the second adder is connected to the integrator output, at this integrator input through an isolation capacitor is connected to the output of the first low-pass filter, the second input of the phase detector and the second input of the controlled phase shifter are connected to the output of the controlled generator, the input The rotator on π / 2 is connected to the output of the controlled phase shifter, which at the same time is the output of the device.

Description

/ UG / OG

 FC ,, (1)

N R where fyj. - frequency at the output of the UG,

fof. is the frequency of the reference crystal oscillator, N is the division coefficient of the DPKD, R is the division coefficient of DF1SD, is the comparison frequency at the reference input of the PD. From here, the output frequency of the synthesizer is defined as

,,. N (2)

Thus, by changing the division coefficient of the DPKD N, it is possible to change the frequency of the output signal of the DSC in discrete increments (steps). Moreover, the frequency grid step F is equal to the comparison frequency, and the step accuracy is determined by the accuracy and stability of the reference frequency / o .. Such a synthesizer is distinguished by the comparative simplicity of the circuit implementation, has the ability to generate any practically necessary number of frequencies, but has a significant drawback that follows from the principle of operation such a CSS. This disadvantage is that it is impossible to choose a comparison frequency above a given step of the frequency grid, i.e. Ff.p F.

With the current tendency to reduce the frequency grid spacing and tighten standards for suppressing spurious frequency modulation due to pulsed interference with the comparison frequency in the control circuit

UG, the passband in the IFAPH ring is usually 50-100 times less than the value of the comparison frequency, which dramatically reduces the speed of the DSC.

One of the most famous attempts to overcome the contradiction between the choice of the comparison frequency and the given step of the frequency grid is to use frequency dividers with a fractional variable division coefficient (DDGZD) instead of the DPKD (see, for example, AS USSR No. 470901, NOZV 21/02, 1975 ; US patent No. 3976945, 1976). The use of DDDR in the IFAPH ring allows one to increase the comparison frequency by 10 or 100 times relative to the step of the frequency grid and by the same amount reduce the integer division coefficient of the DDHD, making it fractional. At first glance, it seems that at the cost of a significant complication of the DGD, the difficulties associated with obtaining a small step of discreteness of the output frequencies in the CSC are overcome. However, upon a detailed examination of the processes in the circuit, it can be found out that the frequency of the noise that creates the secondary components; that is, in the spectrum of the output signal of the CSC (the so-called “fragmentation noise”), turns out to be equal to the step of the frequency grid and does not depend on the selected higher comparison frequency (see A . S. Galin "Band-quartz stabilization of the microwave, M., 1976, S. 77). Therefore, the PLL in the control circuit of the UH turns out to be as narrow-band as in the conventional DSC with DPKD, with all the disadvantages arising from this.

The closest in technical essence to the proposed one is the CSC (see US patent No. 3714463, Kl.307-232 from 01.30.73), containing a controlled oscillator connected in a ring, a frequency divider with a variable division ratio, a frequency-phase detector and a low-pass filter as well as a series-connected reference oscillator and frequency divider with a fixed division ratio. However, the speed of the known DSC remains insufficient, due to the inertia of the PLL, which is determined by the need to suppress to a given level of interference with frequency in the control circuit of the UH.

The aim of the proposed technical solution is to increase the suppression of spurious frequency modulation while increasing speed.

This goal is achieved by the fact that in a digital frequency synthesizer containing a controlled oscillator connected in a ring, a frequency divider with a variable division ratio, a frequency-phase detector and a first low-pass filter, a reference oscillator and a frequency divider with a fixed division ratio, the output of which is connected with the second input of the frequency-phase detector, an integrator, a first adder, an inverter and a controlled phase shifter are connected in series, connected in series phase shifter

the second adder is connected to the output of the integrator. The input of the integrator through the isolation capacitor is connected to the output of the first low-pass filter, the second input of the phase detector and the second input of the controlled phase shifter are connected to the output of the controlled generator,

the input of the phase shifter on is connected to the output of the controlled phase shifter,

which is also the output of the device.

Comparative analysis with the prototype device shows that here, with the help of the introduced new elements, combined with the corresponding links with the other nodes of the circuit, there is an additional suppression of spurious frequency modulation (FFM) of the output signal of the synthesizer. And this, in turn, made it possible to reduce the inertia of the low-pass filter in the control circuit of the exhaust gas and thereby increase the speed of the central clock. Thus, in the proposed CSC, at the same time, the suppression of the IFM level is increased and the speed is increased.

Technical solutions with similar features are unknown to the applicant. Therefore, we can conclude that the proposed solution has existing differences.

The drawing shows a block diagram of a digital frequency synthesizer.

The digital frequency synthesizer contains a controllable generator UG1 connected to a ring, a frequency divider with a variable coefficient of the real DPKD2, a frequency-phase detector ChFDZ and the first FPCH4, series-connected reference generator OG5 and a frequency divider with a fixed division coefficient DFKD6, the output of which is connected to the second input of ChFD4, series-connected integrator INT7, the first adder SUM8, inverter INV9 and controlled phase shifter UV 10,

series-connected phase shifter on - FVP, phase detector

FD12, the second FPCH13 and the second adder SUM 14, the output of which is connected to the second input of the adder SUM8, and the second input of the second adder SUM 14 is connected to the output of the INT7 integrator. In this case, the second input PfflT through the isolation capacitor 15 is connected to the output of the first low-pass filter 4, the second input FD12 and the signal input UV 10 is connected to the output UG1, the input

phase shifter on - FVP is connected to the output of UV 10, which at the same time

is the output of the device.

Digital frequency synthesizer operates as follows. After establishing the synchronism mode in the IFAPCH ring, the signal from the output of UG1 with a frequency fyf. arrives at the input DPKD2, where it is divided by frequency into

division coefficient N. From the output D1iKD2 signal in the form of short pulses with

the output DFKD6 come short reference pulses with a comparison frequency of Ff.p. As a result of comparing the frequency and phase of the two streams of input pulses, the control voltage is generated at the ChFDZ output, which is fed through the first low-pass filter to the control input of UG1 and adjusts its frequency to the frequency of OG5 up to phase.

At the same time, at the output of the first low-pass filter, there are interfering components in the common control signal with frequencies that are multiples of 7, which cause the corresponding spurious frequency modulation (FFM) of the output signal UG1.

From the output of UG1 to the signal input UV 10 and the second FD12 receives a high-frequency signal modulated by interference

C /, and, co8 (d) oG + r,), (3)

where d) o is the frequency of the carrier oscillation of UG1,

, is the instantaneous phase shift caused by the spurious interference component from the output of the low-pass filter.

After the controlled phase shifter UV 10 high-frequency signal

passes through the phase shifter on - ФВ11 and enters the first input

PD12 phase detector in the form

t / 2 u, sin (6Jo + 32), (4)

where 2 is the instantaneous residual total phase shift,

caused by

incomplete compensation of parasitic angular modulation of the output signal UG1 and parasitic angular modulation arising due to different phase shift at the UV 10 and FVP nodes, and also due to fluctuations of this phase shift under the influence of destabilizing factors (moreover, 2) (p} Thus Thus, from the output of UG1 high-frequency signal with

phase shifter on - FVP is divided into two quadrature

components, i.e. oscillations of the same frequency are generated at the PD12 inputs, but 90V phase-shifted relative to each other in the PD12 phase detector, two quadrature signals (3) and (4) are multiplied and a signal is generated at the output of the second LPF13

ifnt fd ((P2 - ((5)

where Kfd - transmission coefficient FD12.

From the output of the second low-pass filter, the error of the error is proportional to (). arrives at the first input of the second adder SUM 14, and its second input through the isolation capacitor 15 and the integrator INT7 receives an interference signal that varies by law,. As a result of the linear summation of these signals at the output of the second adder SUM 14

a signal is formed that changes only according to the law ((because (+ 1 2) At the output of the first SUM8 as a result of adding the signals from the output of the SUM 14 and from the output of INT7, a voltage is formed that changes according to law 2 (p. After the INV9 inverter to the control input a controlled phase shifter UV 10, a signal arriving that changes according to the law {- ((which will turn the phase of the original signal from UG1 so that a high-frequency signal with almost completely suppressed spurious angular modulation (/ uv c.

In the proposed CSC, it is possible to significantly reduce the inertia of the low-pass filter at the control input of UG1 without fear that this will cause an increase in the level of interference components from its output and, accordingly, an increase in spurious angular modulation of the output signal of the device, since at the output of UV 10 (device output) this parasitic modulation will be almost completely suppressed. Moreover, due to the redistribution of the IF frequency suppression between the low-pass filter 4 and the newly introduced nodes of the quadrature signal UG1 conversion, it is possible to increase the total IF frequency suppression in the output signal of the device and at the same time increase the speed of the digital frequency converter by reducing the inertia of the low-frequency filter 4.

The proof of the feasibility of the proposed device is that the input units are typical and can be performed on widely used microcircuits: adders, an inverter and integrators can be performed on operational amplifiers (for example, on a K544UD2A microcircuit), and a phase detector on a microcircuit

174PS1 or 174PS2. The phase shifter on - represents a resonant circuit (for example, an LC circuit) in which a certain

selection of reactive elements (L, C) achieves a phase shift by -

output signal relative to the input. A controllable phase shifter can be built on paralleled 11 parallel and sequential oscillatory circuits. As a variable parameter in such devices, the capacitance of the varicap is used, to which the control voltage is applied (see, for example, Designing Radar Receiving Devices: Textbook for Radio Engineering Special Universities. Edited by MA Sokolov. - M .: High School, 1984, p. 122).

Thus, the use of the proposed digital frequency synthesizer allows you to almost completely suppress spurious frequency modulation of the output signal from the effects of interference with the comparison frequency while increasing performance.

Claims (1)

A digital frequency synthesizer comprising a controlled oscillator connected in a ring, a variable divider frequency divider, a frequency-phase detector and a first low-pass filter, a reference oscillator and a fixed divisor frequency divider, the output of which is connected to the second input of the frequency-phase detector characterized in that, in order to increase the suppression of spurious frequency modulation while increasing the speed, series-connected the second integrator, the first adder, the inverter and the controlled phase shifter, the phase shifter connected to π / 2, the phase detector, the second low-pass filter and the second adder, the output of which is connected to the second input of the first adder, and the second input of the second adder is connected to the integrator output, at this integrator input through an isolation capacitor is connected to the output of the first low-pass filter, the second input of the phase detector and the second input of the controlled phase shifter are connected to the output of the controlled generator, the input The rotator on π / 2 is connected to the output of the controlled phase shifter, which at the same time is the output of the device.