JPH0439243B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit configuration of a digital oscillator using a cyclic digital filter.

BACKGROUND ART With the digitization of communication devices, it has become important to generate sine waves used for modulation and demodulation as digital signals. A first method for generating a digital sine wave is to store sample values obtained by sampling a sine wave at regular intervals in a memory, and to sequentially read out the contents of the memory at each sampling period. This method is called a table representation method, and is simple, but has the disadvantage that the memory capacity becomes enormous if the ratio between the generation frequency and the sampling frequency is an irrational number. Therefore, conventionally, a digital oscillator using a second-order cyclic circuit as shown in FIG. 1 has been used. The oscillator has a first delay device 1 and a second delay device 2 connected in series, each having a delay time equal to the sampling period, and the output of the first delay device 1 is multiplied by a coefficient b ₁ in a first multiplier 3. and the second delay device 2
The output of is multiplied by the coefficient b ₂ by the multiplier 4. Then, the outputs of multipliers 3 and 4 are added by a first adder 5. The output of the first adder 5 is added to the input impulse in the second adder 6, and the output is added to the input impulse in the first delay unit 1.
is connected to the input of This oscillator has a coefficient
After appropriately setting b ₁ and b ₂ and clearing the contents of the first and second delay circuits 1 and 2, a digital sine wave can be oscillated by applying an input impulse to the second adder 6. The relationship between the oscillation frequency ₀ and the sampling frequency _s of this oscillator is as follows: the coefficient b ₂ is 1
Since it is determined corresponding to the coefficient b ₁ , it is possible to oscillate an arbitrary frequency by appropriately setting the coefficient b ₁ . However, such conventional digital oscillators have a lower oscillation frequency than the sampling frequency _s .
When ₀ is extremely small, there is a drawback that the oscillation frequency ₀ varies greatly due to a slight difference in the coefficient b ₁ for reasons described later. Therefore, in order to obtain the desired oscillation frequency, it is necessary to precisely define the coefficient _b1 . In other words, it is necessary to make the coefficient word length representing the coefficient b ₁ sufficiently long, which results in an increase in hardware.

Oscillation frequency ₀ , sampling frequency _s , coefficient b ₁ ,
b ₂ has the relationship given by the following equations (1) and (2).

b ₁ = 2 ^cos 2π ₀ / _s (1) b ₂ = 1 (2) Therefore, if the change in oscillation frequency ₀ when the coefficient b ₁ is changed by db ₁ is d ₀ , b ₁ of ₀ The sensitivity to d ₀ / ₀ b ₁ / db ₁ = − _s / 2π ₀ cosθ/sin
θ(3) However, it can be expressed as θ=2π ₀ / _s (4). That is, when θ≪1
Since sin θ in equation (3) becomes small, the sensitivity becomes extremely high. For example, when _s = 100 Hz and ₀ = 2 Hz, in order to suppress the fluctuation of ₀ within 10 ^-4 , it is necessary to suppress the quantization error of b ₁ to 1.6 × 10 ^-6 or less. This means that the coefficient word length requires approximately 19 bits. Note that since the coefficient b ₂ is 1, there is no particular need to provide the multiplier 4, and it is sufficient to leave it through.

The purpose of the present invention is to solve the above-mentioned conventional drawbacks and
An object of the present invention is to provide a digital oscillator whose coefficient word length can be significantly reduced compared to conventional circuits.

The oscillator of the present invention includes a cascade-connected circuit of a first delay device and a second delay device having a delay time equal to a constant sampling period, and a first multiplier that multiplies the output of the first delay device by a constant coefficient. a first adder that adds the output of the first multiplier and the output of the second delay device; and a first adder that adds the input impulse and the output of the first adder and inputs the result to the first delay device. 2 adder and generates a digital sine wave of an arbitrary frequency corresponding to the coefficient input to the first multiplier, the input signal of the first delay device is a first modulator that modulates the output signal of the first delay device with a modulation wave having a period that is four times as long; a second modulator that modulates the output signal of the first delay device with a modulation wave that is delayed in phase by π/2 from the modulation wave; a third modulator that modulates the output signal of the second delay device with a modulation wave whose phase is further delayed by π/2 than the modulation wave input to the second modulator; a second multiplier for multiplying, a third adder for adding the output of the second multiplier and the output of the third modulator, and an output of the third adder and an output of the first modulator; and a fourth adder that performs addition, and the output of the fourth adder is a digital sine wave output.

Note that it is also possible to provide a third multiplier that multiplies the output of the third modulator by a constant coefficient, and to add the outputs of the second and third multipliers.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing one embodiment of the present invention. That is, as in the prior art, the first delay device 1 and the second delay device 2 are connected in series, and the output of the first delay device 1 is multiplied by the coefficient β ₁ in the first multiplier 3. The delay times of the first and second delay devices are equal to the sampling period T, that is, the reciprocal of the sampling frequency _s . And the first
The output of the multiplier 3 and the output of the second delay device 2 are added by a first adder 5, and the output of the first adder 5 is added to the output of the second delay device 2.
The adder 6 adds the input impulse. The output of the second adder 6 is connected to the input of the first delay device 1. However, in this embodiment, for example, if you want to obtain a 2Hz sine wave using a sampling frequency _s of 100Hz, the oscillation frequency to be oscillated by the above-mentioned components
Set the coefficient β ₁ so that ₀ is 23Hz. Then, as described later, the 23Hz is modulated at 25Hz (4 times the period of 100Hz) to obtain a modulated output signal of 25±23Hz, and then unnecessary components are removed to output a 2Hz component. There is.

That is, the input signal of the first delay device 1 is input to the first modulator 7, and modulated with a modulated wave having a cycle four times the sampling frequency _s . This modulation is performed by inputting digital values "0", "1", "0", and "-1" to the first modulator 7 at every sampling period T as shown in FIG. This can be easily done by multiplying. The above digital value series is φ ₀
That's what I will say. The digital value series φ ₀ is
Since the values are only "1", "0", and "-1", the modulator 7 can be easily constructed using, for example, a sign inverting circuit and a gate, without using a multiplier. . Further, the output signal of the first delay device 1 is converted into the digital value series φ ₀ by the second modulator 8.
It is modulated by a digital value sequence φ ₁ as shown in FIG. 4b whose phase is delayed by π/2. Also,
Similarly, the output signal of the second delay device 2 is transmitted to the third modulator 9.
The digital value sequence φ ₂ is further delayed by π/2 from the digital value sequence φ ₁ (see FIG. 4c). Then, the output of the second modulator 8 is multiplied by a coefficient α ₁ in a second multiplier 10, and the output of the third modulator 9 is multiplied by a coefficient α ₂ in a multiplier 11. Multiplier 1
The outputs of 0 and 11 are added by a third adder 12, and the output of the third adder 12 is input to a fourth adder 13, where it is added to the output of the first modulator 7.
By appropriately setting the coefficients α ₁ and α ₂ , the output value of the fourth adder 13 can remove unnecessary frequency components from the output of the first modulator 7 . For example, in the example above, the 25+23Hz component is removed, and the 25−23Hz component is removed.
It is possible to output only the =2Hz component. In other words, there is a low-frequency filter effect, and a sufficient amount of attenuation can be obtained by setting the coefficients α ₁ and α ₂ to, for example, 2 and 1, respectively. Therefore, the multiplier 10 may be configured with a simple shift circuit or the like, and the multiplier 11 may be omitted and passed through.

Figure 3a shows the spectrum of the input signal of the first delay device 1 (that is, also the input signal of the first modulator 7), the sampling frequency obtained is s = 100Hz, the modulation frequency is 25Hz (100Hz/4), and the oscillation frequency is 25Hz (100Hz/4). The case where frequency ₀ is set to 23Hz is shown. Since the period of the modulation frequency of 25 Hz is four times the period of the sampling frequency _s (100 Hz), the angular frequency of the modulation frequency of 25 Hz is π/2, and the angular frequency of the oscillation frequency of 23 Hz is near π/2. teπ/
Since it is slightly smaller (by ε) than 2, its spectrum is as shown in FIG. 3a. If this signal is modulated by a sine wave (25 Hz) with an angular frequency of π/2, a signal with an angular frequency of π/2±(π/2−ε) is obtained. Therefore, the spectrum of the output signal of the first modulator 7 has angular frequencies ε, π±, as shown in FIG. 3b.
Contains four line spectra: ε, and 2π-ε.
On the other hand, in Figure 2, the coefficients α ₁ and α ₂ are
When set to 1.9 and 1, the fourth adder 13
The signal near the angular frequency π is attenuated and outputted, and the attenuation characteristic is as shown by the curve c in FIG. 3b. Therefore, the signal near the angular frequency π (25Hz
+23Hz) is removed and the signal with angular frequency ε (2Hz) is obtained.
only is output from the fourth adder 13.

In the above, in order to set the oscillation frequency ₀ to 23Hz, the coefficient β ₁ is set to β ₁ = 2cos2π ₀ / _s = 2cos2π23/100 from equation (1), and θ = 2π23 from equation (4). /100, the sensitivity to β ₁ at oscillation frequency ₀ is obtained from equation (3) as follows: d ₀ / ₀ β ₁ /dβ ₁ = -100/46π cosθ/sin
θ≒0.087. Therefore, the accuracy of β ₁ required to suppress the fluctuation of ₀ within 10 ^-4 is sufficient to be around 1.1×10 ^-3 .
In other words, the coefficient word length may be approximately 10 bits, which can be significantly reduced compared to the 19 bits required in the conventional circuit. Along with this, a multiplier,
The scale of the adder etc. can be small, and the overall structure can be configured with less hardware.

As described above, in the present invention, the output of a conventional digital oscillator using a second order cyclic digital filter is modulated at a frequency of 1/4 of the sampling frequency, and high frequency components are extracted from the modulated signal. Since it is configured to remove and output only low frequency components, it is possible to lower the accuracy of the coefficients used to determine the oscillation frequency when it is desired to obtain an output with an extremely low frequency relative to the sampling frequency. can. That is, the coefficient word length can be reduced, and the circuit scale can be significantly reduced compared to the conventional method.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional digital oscillator, FIG. 2 is a circuit diagram showing an embodiment of the present invention, FIG. 3a is a diagram showing the spectrum of the modulator input in the above embodiment, and FIG. Figure 3b shows the spectrum of the modulator output and the attenuation characteristics up to the output of the fourth adder, and Figures 4a, b and c show the modulation signals input to the first to third modulators, respectively. FIG. In the figure, 1...first delay device, 2...second delay device, 3...first multiplier, 4...multiplier, 5...
First adder, 6... Second adder, 7... First modulator, 8... Second modulator, 9... Third modulator, 10
... second multiplier, 11 ... multiplier, 12 ... third
Adder, 13...Fourth adder, b ₁ , b ₂ , β ₁ , β ₂ ,
α ₁ , α ₂ ... Coefficients.

Claims (1)

[Claims] 1. A cascaded circuit of a first delay device 1 and a second delay device 2 having a delay time equal to a constant sampling period, and multiplying the output of the first delay device by a constant coefficient β ₁ a first multiplier 3 for adding the output of the first multiplier and the output of the second delay device; and a first adder 5 for adding the output of the first multiplier and the output of the second delay device; a second adder 6 which is input to the first delay device 3, and which generates a digital sine wave of an arbitrary frequency corresponding to the coefficient β ₁ which is input to the first multiplier 3; a first modulator 7 that modulates the input signal of the device 1 with a modulation wave having a period four times the sampling period;
and a second modulator 2 that modulates the output signal of the first delay device 1 with a modulation wave whose phase is delayed by π/2 from the modulation wave; a third modulator 9 that modulates with a modulated wave whose phase is further delayed by π/2 than the modulated wave input to the modulator; and a second multiplier 10 that multiplies the output of the second modulator by a constant coefficient _α1 . , a third adder 12 that adds the output of the second multiplier and the output of the third modulator 9; and a fourth adder 12 that adds the output of the third adder and the output of the first modulator 7. A digital oscillator comprising an adder 13, the output of the fourth adder being a digital sine wave output. 2. A cascaded circuit of a first delay device 1 and a second delay device 2 having a delay time equal to a constant sampling period, and a first multiplier 3 that multiplies the output of the first delay device by a constant coefficient β ₁ . a first adder 5 that adds the output of the first multiplier and the output of the second delay device; and adds the input impulse and the output of the first adder and inputs the result to the first delay device. a second adder 6, and generates a digital sine wave of an arbitrary frequency corresponding to the coefficient _β1 input to the first multiplier 3, the input signal of the first delay device 1 is a first modulator 7 that modulates with a modulated wave having a period four times the sampling period;
and a second modulator 2 that modulates the output signal of the first delay device 1 with a modulation wave whose phase is delayed by π/2 from the modulation wave; a third modulator 9 that modulates with a modulated wave whose phase is further delayed by π/2 than the modulated wave input to the modulator; and a second multiplier 10 that multiplies the output of the second modulator by a constant coefficient _α1 . , a third multiplier 11 that multiplies the output of the third modulator 9 by a constant coefficient α ₂ , and a third adder 12 that adds the output of the third multiplier 9 and the output of the second multiplier 10. a third adder 12 that adds the output of the second multiplier and the output of the third modulator 9; and a third adder 12 that adds the output of the third adder and the output of the first modulator 7. 4 adder 13, and the output of the fourth adder is a digital sine wave output.