JPH0221712A - Sampling frequency converter - Google Patents

Abstract

PURPOSE:To obtain an output sample string with high accuracy by applying prediction calculation to a ratio of each of an input sampling period and an output sampling period to a local clock period by means of the accumulation processing of errors and applying the interpolation processing to an input sample string based on a filter coefficient address data obtained through the accumulation of divided values. CONSTITUTION:Ratio data obtained by prediction calculation means 15, 16 calculating the prediction of the ratio of the input sampling period and the local clock period and the ratio of the output sampling period and the local clock period are divided with each other and the results are accumulated. Then a coefficient address generating means 17 calculating the filter coefficient address data required for the interpolation processing and giving the result to a digital signal processing means 7 and a memory control means detecting overflow of the result of the accumulation processing and applying the write/read control to each buffer memory are provided. Moreover, a local clock generating means outputting a local clock signal with a period of 1/integral number (2N) of the local clock period is provided. Thus, the sampling frequency conversion with optional conversion ratio is implemented with high accuracy and simple constitution.

Description

[Detailed description of the invention] Hereinafter, the present invention will be explained in the following order.

A. Field of industrial application B. Summary of the invention C. Prior art D. Problem to be solved by the invention E. Means for solving the problem F. Effect G. Example G, description of the overall configuration of the sampling frequency conversion device (see (Figure 1) Explanation of each component of the 62-sampling frequency conversion device (Figures 2 to 7) G2-1 Digital signal processing section (Figure 2) G! −□ Local clock generator G! -1 Conversion control unit (Figures 3 to 7) G! -:l-1
Event detection unit (Figures 3 and 4) at-s- adaptive prediction processing unit (Figures 5 and 6) G1-2-3 coefficient address generation unit (Figure 7) Effect A: Industrial Application Field The present invention relates to a sampling frequency conversion device that converts a human sample sequence into an output sample sequence with a different sampling frequency, for example, conversion of sampling frequency between various PCM audio signal transmission systems. applied to processing.

B. Summary of the Invention The present invention provides a sampling frequency conversion device that converts an input sample sequence into an output sample sequence with a different sampling frequency.
, the ratio between the input sampling period and the local clock period and the ratio between the output sampling period and the local clock period are predicted by cumulative addition processing of error values, and obtained by cumulatively adding the division values of each ratio data. A highly accurate output sample sequence is obtained by performing interpolation processing on the input sample sequence based on the filter coefficient address data.

C. Conventional technology Conventionally, compact discs (CDs) have recorded PCM audio signals with a sampling frequency of 44.1 kHz, processing for sampling input audio signals at a sampling frequency of 44.056 kHz and converting them into PCM data, and their A PCM processor that performs inverse transformation processing and a sampling frequency of 3
Various PCM signal transmission systems that use different sampling frequencies have been put into practical use, such as a satellite broadcasting system that broadcasts PCM audio signals in A mode that uses 2 kHz or B mode that uses 48 kHz. and,
In order to make PCM signals with different sampling frequencies in the various PCM signal transmission systems compatible with each other, a sampling frequency conversion device that converts the sampling frequency (sampling rate) is required.

As the above-mentioned sampling frequency conversion device, there is one that samples an analog signal obtained by digital-to-analog conversion of a PCM signal again using a desired sampling method and converts it into PCM data. This sampling frequency conversion device uses digital
Since an analog converter and an analog-to-digital converter are required, not only the configuration is complicated and the price of the device is high, but also the signal passes through the digital-to-analog converter and analog-to-digital converter, so the signal f! The disadvantage was that the sound quality (for example, sound quality) deteriorated.

Furthermore, as a sampling frequency converter that converts the sampling frequency of a PCM signal as a digital signal without converting it into an analog signal, a configuration as shown in FIG. 115015, JP-A-61-204700).

That is, in the block diagram of FIG. 8 showing the conventional sampling frequency conversion device, (101) represents the sampling frequency (fs li
s+ ) with a sampling clock signal (Fs(i,,k
) is the clock signal input terminal to which the clock signal is supplied. The sampling clock signal CFstrn,) supplied to this clock signal input terminal (101) has a frequency (fs t
PLL that multiplies jn> ) by 2N times (for example, 2? times)
the circuit (102). The above PLL circuit (1
A signal with a frequency of 2''fs'fin+ obtained at the output side of the counter (103) is supplied to the clock input terminal (C) of the counter (103).

(104) is the output sample sequence (yj
) is a clock signal input terminal to which a sampling clock signal (F) (., 5.) having a sampling frequency (fsi., )) is supplied. This clock signal input terminal (104)
The sampling clock signal (Fsl., 〉) supplied to
'' is supplied to the reset input terminal (R) of the counter (103), and is also supplied as a latch timing signal to the latch terminal (L) of the register (105) that latches the count data of the counter (103). .

Note that the counter (103) performs a counting operation with a counting period of 17fsfIn+, and thus requires a length of N bits.

The counter (103) has its count data launched into the register (105) at the output sampling frequency (fs (ot+tl)), and is reset immediately thereafter.
Next, start counting from 0. Therefore, the data stored in the above register (105) ultimately indicates the phase of the output sample point with respect to the input sample point immediately before it (however, this phase is an instantaneous value and is normalized with 2N as 1). (Think of it as such.)
, the hold data in the register (105) is given to an arithmetic circuit (106).

In addition, (107) is the sampling frequency to be converted (
This is a data input terminal to which an input sample sequence (x,) of fsii-+) is supplied. This data input terminal (107)
The input sample string (X, ) supplied to ) and the data output terminal (10
8) is output.

Phase data (φJ) obtained in the above register (104)
The relationship between the input sample sequence (Xl) and the output sample sequence (yJ) is shown on the time axis as shown in FIG. ), the sample value of the desired output sample point of the output sample sequence (yj) can be calculated from the input sample sequence (xi) by a method such as polynomial interpolation or digital filtering as follows.

For example, in the schematic diagram in Figure 10, which shows a method of calculating approximate values of output sample values by linear interpolation (linear interpolation) using polynomial interpolation calculations, (X,) (x +-,) is the input sample sequence (X , ), (y,) is each amplitude value of the output sample sequence (yj), (φ4) is the phase (0
≦φ, <1), and the amplitude value of the output sample point <
VJ) is VJ=Xl-r+(XtXr
−+ )・φ.

The phase data of the output sample point (φJ
), each amplitude value (X t) +
It can be calculated from (X +-+).

Furthermore, in the method that applies digital filtering, the transformation ratio is L/M (L
, M: an integer) can be subjected to sampling frequency conversion using the following procedure.

First, between each sample of the input sample sequence (Xl), (
Fill samples with L-1) zero values.

As a result of this processing, the apparent frequency is increased by a factor of L, but the frequency spectrum of the sample sequence remains unchanged. Next, this sample sequence is converted to the lower of the input sampling frequency (fs, NM,) and the output sampling frequency (fs(.□l)) in the range up to (L/2) times the sampling frequency. Coefficient sequence <Ko, KI, Kt, ~K, consisting of an impulse response having the characteristics of a low-pass filter whose passband is only the signal band of .

~X2□I + Kxr), a sample sequence interpolated by L times is obtained.

The convolution processing to obtain the double interpolated sample sequence (y,) is as follows: )' = = ””
j+ X r-Io to r-L-1j+g°Kp-L-
t, jlj+ x 1e+°K r −t L −L
−I j+... (φ, =φ le, 1/L, 2/L, ~, (L-1) le), and in order to calculate one output sample, every L coefficient is It is only necessary to extract the sum of products and perform the sum of products calculation, and a digital signal processing processor (D
SP: Digital Signal r'roce
ssor). Note that the convolution processing to obtain the sample sequence (y,) by the DSP is as follows:
Sampling frequency of human sample sequence (χ,) “3+1n))
and/or a high-speed clock signal suitable for driving the DSP formed by multiplying the sampling frequency (fs(.ul,)) of the output sample sequence (y,) is used.

D Problems to be Solved by the Invention By the way, as described above, in the PLL circuit, using a clock signal formed by multiplying the sampling frequency (fs(!-1) of the input sample sequence (x8) by 2N times) , obtain the phase data (φ,) which is normalized by setting 2″ to 1 for the phase with respect to the input sample point immediately before the output sample point, and convert the phase data (φ,) into the input sample sequence with B as a parameter or control I. (In the conventional sampling frequency conversion device that obtains the output sample sequence (yj) by approximately calculating the sample value of the desired output sample point from Xtl, in order to reduce the approximation error of the output sample value, The frequency of the clock signal is increased by increasing the multiplication ratio of the PLL circuit, and the phase data (φ
j) It is necessary to improve the decomposition accuracy. In addition, the sampling frequency ( f31in and/or a high-speed clock signal multiplied by the sampling frequency (fs+.utl) of the output sample sequence (yd) is required.

In this way, in the conventional sampling frequency conversion device, in order to form the above-mentioned clock signal, P L L
Moreover, this PLL circuit requires a sampling clock signal (Fs (I
There is a problem in that a sufficiently wide capture range is required to be able to follow the frequency fluctuations of the sampling clock signal (Fs (.11.) of the output sample sequence (y,) and/or the output sample sequence (y,). Sample column (X,
) to approximately calculate each sample value of the output sample sequence (y4).
The sampling clock signal (F
Sii n)) and/or output sample sequence (yJ
There is a problem in that synchronization is difficult because it operates with a high-speed clock signal formed from the sampling clock signal (Fs (.Eng. 5.)).

In addition, in conventional sampling frequency conversion devices, averaging is performed using oven loop control n, for example, 1-Z-' calculation processing, so when a step-like phase error occurs, , n, and a step-like phase control amount corresponding to the phase error is not achieved, resulting in a control error remaining.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, the present invention provides a sampling frequency conversion device with a novel configuration that can perform sampling frequency conversion of an arbitrary conversion ratio with high precision and with a simple configuration. The purpose is to

E. Means for Solving the Problems In order to achieve the above-mentioned object, the sampling frequency conversion device according to the present invention converts an input sample string into a sample string with a sampling frequency that is an integer (2M) times the input sampling frequency. oversampling processing means for converting, a first buffer memory for temporarily storing sample values of the sample sequence output from the oversampling processing means, and operating at a local clock period shorter than the input sampling period and the output sampling period. Then, the sample sequence read from the first buffer memory is subjected to an interpolation calculation process using a filter coefficient that gives the impulse response characteristic of a low-pass filter with respect to a sampling frequency 2'4 times the input sampling frequency, and an output sample is obtained. digital signal processing means for calculating interpolated sample values at each sample point of an output sample sequence having a frequency of , by cumulatively adding error values of the sampling period quantized with the local clock period to the predicted sampling period, the ratio of the input sampling period and the local clock period and the output sampling period and the local clock are calculated. By dividing each of the ratio data obtained by the prediction calculation means and the prediction calculation means for predicting the ratio with the period, and cumulatively adding the values,
Coefficient address generation means that calculates filter coefficient address data necessary for the interpolation processing and supplies it to the digital signal processing means, and detects overflow of each cumulative addition processing result in the prediction calculation means or coefficient address generation means, The present invention is characterized in that it comprises a memory control means for controlling writing and reading to and from a buffer memory, and a local clock generation means for outputting a local clock signal having a period equal to l/an integer (2N) of the local clock period.

F Function In the sampling frequency conversion device according to the present invention, the input sampling period and the output A digital signal processing means that operates with a local clock period shorter than the sampling period performs interpolation calculation processing using filter coefficients that give the impulse response characteristic of a low-pass filter with respect to a sampling frequency that is 2''' times the input sampling frequency. The interpolated sample value at the output sample point is computed by applying

In addition, in this sampling frequency conversion device, by cumulatively adding the error value of the sampling period quantized by the local clock period in the prediction calculation means to the predicted sampling period,
A ratio between the manual sampling period and the local clock period and a ratio between the output sampling period and the local clock period are predictively calculated.

Then, the coefficient address generation means divides each ratio data of the input sampling period and the output sampling period with respect to the local clock period obtained by the prediction calculation means, and cumulatively adds the values. Calculate filter coefficient address data necessary for interpolation processing.

Furthermore, the memory control means in this sampling frequency conversion device detects an overflow of each cumulative addition process in the prediction calculation means or coefficient address generation means, and temporarily stores the sample values of the sample sequence obtained by the oversampling process. Write/read control is performed in response to the overflow detection output of each of the cumulative addition processes, with respect to a first buffer memory for temporarily storing each sample interpolated value of the output sample point obtained by the interpolation calculation process. hand,
Each sample string is read from each buffer memory at a desired timing.

G. Embodiment 1 Below, an embodiment of the sampling frequency conversion device according to the present invention will be described in detail with reference to the drawings.

01 Overall configuration of sampling frequency conversion device The embodiment shown in the block diagram of FIG.
In this embodiment, the present invention is applied to a sampling frequency conversion device that converts the output sample sequence (y,) of the second sampling frequency (fs(.uLl)). is supplied with the input sample sequence (X,) to be converted, and the sampling frequency (fs++s+) of the input sample sequence (X,) is supplied to the first clock signal input terminal (2).
), that is, a first sampling clock signal (FS u −+ ) having an input sampling frequency is supplied, and the second clock signal input terminal (3) is further supplied with a signal output terminal (4
), a second sampling clock signal (pst.uLl) having an output sampling frequency (sampling frequency of yJl<fs(.□)), that is, an output sampling frequency to be obtained, is supplied.

The sampling frequency conversion device of this embodiment converts the input sample sequence (X,) supplied to the signal input terminal (1) into an integer (2) of the input sampling frequency (fs++++i).
an oversampling unit (5) that performs oversampling processing of 5 times the input sampling frequency (fst+a+) obtained by the oversampling unit (5); frequency (4・
Sample value (χ, ·) of sample sequence of rS(i+++)
a first buffer memory (6) for storing - time, and the above-mentioned 4
The sample sequence (x, .) read out from the first buffer memory (6) is subjected to digital filtering processing using a filter coefficient that gives the impulse response characteristic of a low-pass filter with respect to the sampling frequency (4.fs<(M, >) The output sampling frequency (fst
. a digital signal processing unit (7) that calculates an interpolated sample value at the sample point of the sample sequence [yjl) converted to
The above output sampling frequency (fs(.vtl) obtained at
a second buffer memory (8) for temporarily storing each interpolated sample bond of the sample sequence (y,); and each of the buffer memories (6).

(8) and a local clock generating section (9) that forms a local clock signal (Fc) that provides the operation timing of the digital signal processing section (7), and the first and second clock input terminals (2) and (3). ), each sampling clock signal (FS <+,, + ), (FS (
. Each sampling frequency (fsn-+
), (fst.-c+) information and local clock frequency (fc) information given by the local clock signal (Pc), each of the buffer memories (6)
, (8) and a conversion control section (10) that controls the operation of the digital signal processing section (7).

08 Description of each component of sampling frequency conversion device Gt-1
Digital Signal Processing Unit The digital signal processing unit (7) is composed of a digital signal processing processor (DSP) that operates based on the local clock signal (Pc) given by the local clock generating unit (9). The sampling frequency (fs+is+), which is four times the input sampling frequency (fs+is+), is read from the coefficient memory (not shown) in accordance with the coefficient address given by the coefficient address generation section (17) of the conversion control section (10). The sample string (X,
A desired digital filtering process is applied to the filter. For example, the digital signal processing section (7)
As an example of the interpolation process is schematically shown in FIG.
A sample sequence (
xi・), the center of the filter coefficient set (C) that gives the impulse response characteristic of the low-pass filter related to the sampling frequency (4・fsfill), which is written in advance in the coefficient memory (not shown). address (AC) and the output sampling frequency (fs, o
With the sample points (L, ) of the output sample sequence (y)) of ut, ) matching, the sample sequence (Xi・)
Four filter coefficients (
ctL(cj), (cm)+(2) is read from the coefficient memory, and the four sample values (Xi), (x)), (x
++), (xt) and add the outputs of each multiplication product, the interpolated sample fa(y
r).

G! -20-1 Kaltaronok generation unit The above local clock generation unit (9) is fc=K・fo
It is composed of a crystal oscillator etc. that oscillates at a local clock frequency ('C) of The sampling frequency (fs(inl)) and the sampling frequency (fst) of the output sample sequence (y,).

utl). Each of the above sampling frequencies (fs (IIIL (fs (.uL)) is a frequency near or below 48 kHz for boat fishing, and the frequency (fo) is set near 48 kHz.And,
The local clock frequency (fc) is a frequency suitable for the DSP chip constituting the digital signal processing section (7), and is used to perform the digital filtering process in which the quantization error of the output sample sequence (y,) is one step or less. The frequency is set to a frequency that can be processed by the digital signal processing section (7).

G! -1 conversion control unit The conversion control unit (10) also includes a base counter (11) for counting the local clock signal (Fc) supplied from the local clock generation unit (lO), and a base counter (11) for counting the local clock signal (Fc) supplied from the local clock generation unit (lO). 11) Based on the counting output of each sampling clock signal (PSti,,+), (FS+out+), the local clock period (To=1/fo) and each sampling period (Tsti,,+=1/fs fiat) +
(Ts (.uL) = 1 / Is +ouL!
) g each relative time difference (d tq ti nl / T
o) + (dt, (.../TO) first and second event detection units (12), (13)
and a timing generator (1) that forms various timing signals.
4), each relative time difference (d 5 tial /
To) + (d tq +outy/To), each of the above sampling clock signals (PSti7.), (
FS t. . 2. ) for each predictive sampling 11J1 (TSa
it (In+/To), (Ts,,z t.-
ti / To), the first and second adaptive prediction processing units (15) and (16), each of the above adaptive prediction processing units (
15), each predicted sampling period obtained in (16) (
Ts*5tttA+/To), (Ts*mt+.□,/
↑0), etc., which calculates the above-mentioned coefficient address based on the coefficient address generation section (17).

G□-3-, Event Detection Unit Each of the above event detection units (12) and (13) receives each sampling clock signal (FS (1ml)) supplied from each of the above clock signal input terminals (2) and (3). ,
Each sampling period (Ts(ial) of (FS (.1.))
+ (Ts t. @) and the above local clock period (
Each relative time difference (d to (r
al) (dt, t. ++1 ) + (F
S (.1t)), each sampling period (Ts
Each edge portion or synchronization pattern is detected at each local clock period (To = 1/fo) shorter than 11+++ ) + (Ts 1end+ ), and each sampling period (
Each relative time difference (dtqt+f
i, )+(dtqt.uL) ) is the unit time (Tc=
The arithmetic processing for measuring l/Pc) on the time axis is performed based on the counter output of the advance counter (11) as described above.

That is, each of the above event detection units (12), (13
), the block diagram of FIG. 3 shows the functional configuration of arithmetic processing in the first event detection unit (12).
For input sampling! 'Jl (Ts (+ al )) The adder (21) is supplied with the input sampling period (T
A cumulative addition operation is performed to add s tinl ) information to the relative time difference (dt (-11)) information from l sampling period (Ts tr −+ ) before stored in the register (22), and the addition output is The above input sampling period (
Ts ci ,, + ) and the local clock period (To
), and this relative time difference (dt) information is supplied to the register (22) and also to the quantization circuit (23).

As shown in FIG. 4, the quantization circuit (23) receives the relative time difference (dt) information given as the addition output of the adder (21) at the frequency (Fc) of the local clock signal. Measurement is performed on the time axis of unit time (Tc), and a measured relative time difference (dta/To) is calculated and output, which is expressed as a ratio of the relative time difference (dt) information to the local clock period (To).

62~. - Adaptive prediction processing unit Each measurement relative time difference (dtq (ill / To) obtained by each of the above event detection units (12) and (13)
+ (dtq f+1wt) / To) The first and second adaptive prediction processing units (15) to which the information is supplied
, In (16), the input sampling period (Ts+i+o) and the output sampling period (Ts (.Ui)) are expressed as a ratio to the local clock period (To) based on the measured relative time difference (dtQ/To) information. Arithmetic processing is performed to calculate the predicted input sampling period (Tsast 11al/To) and the predicted output sampling period (Tso, 5..ut+/To), respectively.

That is, each of the above adaptive prediction processing units (15) and (16
), the first adder (5) to which the measured relative time difference (dtQ/To) information is given is shown in the block diagram of FIG.
1) subtracts the predicted relative time difference (dLst/To) information given as the addition output of the second adder (52) from the measured relative time difference (dtq/To) information to obtain the predicted relative time difference (dtast). /↑0) The error of the above measured relative time difference (dt, /To) information is calculated.

Then, the error information obtained by the first adder (51) is observed by the error monitoring section (53), and the error information obtained by the first adder (51) is observed by the error monitoring section (53).
As shown in the figure, correction information Δ(Ts li , y / To) for the next predicted sample position calculated by the calculation processing unit (54) based on the above error information is given to the third adder (55). It is now possible to

The third adder (55) is connected to the first register (56).
1 predicted input tank regularization period (TSast) that is fed back via
(i++1) previous predicted input sample other M(Ts*mt++
−+/To), the above correction information Δ(Ts li
By adding nl/To), the predicted input sampling period (Ts*st fi++)/To) is calculated and output. Note that the first register (56) has the following information:
The output of the third adder (52), that is, the initial value (T,.) information of the predicted input sampling period (T!l*sz +=n,/To) information is given in advance.

Then, the predicted input sampling period (Ts*st (iml/To
) information is provided to the first register (56) and the second adder (52).

Further, the second adder (52) is connected to the second register (52).
7) 1 prediction input bar book conversion Shuho (TS*
gLfin+) previous predicted relative time difference (dtast/T
o) (-n information for the above predicted input sample and other pJl(ding!
By adding the dtsit/To) information, predicted relative time difference (dtsit/To) information is calculated and output. The second register (57) stores the predicted relative time difference (dt) output from the second adder (52).
*st/To) Initial value of information Cdt9°) Information is given in advance.

The output of the second adder (52), that is, the predicted relative time difference (dtstt/'') information is given to the second register (57) and the first adder (51).

Here, each initial value (atq6) given to each of the above registers (56) and (57) + CTs@. ) information is obtained, for example, by direct quantization measurement of the relative time difference (atq).

In this way, the predicted input sampling period (TSIIIL trn+ / To
) information to the second adder (52) to calculate the predicted relative time difference (dt--L/To), and the predicted relative time difference (dt--L/To) obtained by the second adder (52).
dt*st/To) information and the above measurement relative time difference (
dtq/TO) information error to the first adder (51).
and the correction information Δ(Ts t= lll / To) calculated by the calculation processing unit (54) based on the error information obtained by the first adder (51) is added to the third adder (51). By feeding back to the adder (55) and correcting the predicted input sampling period (Ts*s□1fi)/To), the relative time difference information obtained by direct quantization measurement of the relative time difference (dt,) Based on the input sampling period (Toast
(1+c) /To) information can be obtained. In addition, the above predicted relative time difference (dt*ic/To) information is
By updating with the accurate predicted input sampling period (TSes□-1/To), it is guaranteed to remain within the observation range of the measured relative time difference (dt, ) over a long period of time. In addition, the above correction information Δ(Ts, r II) / To)
The correction according to the above predicted input sampling period (TS*ttu
s)/To) This is done within a range that does not cause phase reversal or distortion due to excessive changes in the information.

The event history of where the predicted relative time difference (dtest) is relative to the measured relative time difference (dt4) is used in calculations to appropriately correct the predicted manual sampling period (Ts, %□□Ill/To). can also be used.

For example, the predicted input sampling period (Ts*st fiA,)
Assuming that it takes 500 samples for the predicted relative time difference (dtest) to change from a value below the range of the measured relative time difference (dt,) to a value above the range of the measured relative time difference (at,) with The error from the current predicted input sampling period (TSast (1y)) is the measured relative time difference (
It can be predicted that the quantization step of dt4) is 11500.

In addition, the above predicted manual sampling period (Tsestt+7))
Furthermore, by monitoring changes in I [crude cases can of course be handled by more complex algorithms.

G! -3-ff coefficient address generation unit Predicted input sampling period (TS*s=-+/To) information and prediction obtained by the above-described arithmetic processing in each of the adaptive prediction processing units (15) and (16). The coefficient address generation unit (17) to which the output sampling period (TS@s□.ut+/To) information is supplied uses the predicted input sampling period (TSes□tn+/To) and the predicted output sampling period (TSll). From the ratio with $L (.
Coefficient addresses for reading k) and (ch) from the coefficient memory are generated as follows.

In other words, a filter coefficient set (c (relating to the cyclic address space of a coefficient memory (not shown) in which 2"N is written in advance For each quadrant, the coefficient address generation unit (17) first sets the initial value of the address variable (x) indicating the address space as the interval (0
Give the coefficient address (AI) to read the filter coefficient (C6) located at ~0.25), and write
The coefficient address (A
x), X ths+ −[X , an +0.25]
The coefficient address (A,) in the third quadrant is given by the operation of mad 1, and X tsa+ −[X +ms+ +0.25] ts
The coefficient address (
A4) is given.

Then, in the next calculation process of the coefficient address necessary for calculating the sample point value, if there is an overflow, X (an-[X nar Ts (o*t+]
The coefficient address (AI) in the first quadrant is given by the operation of sod 1, and if there is no overflow, X (All = [X tAa+ +0.
25] The above coefficient address (A
,)give.

In this case, the above x = [x +0.25) mod
The operation of 1 is fs (auLl > fs fin
+ amplifier conversion mode, the practical ratio (Ts
fouL) / TS (inl) < 1 to 2
by calculating with a quantization step equal to the hex fraction nod? 4ii Eliminate the need for arithmetic, and in fact,
The ratio value of Ts 1ouLl / To > 1 and the ratio value of Ts r,rn+ / To > 1 are calculated by each of the adaptive prediction processing units (15) and (1
6), the 111 input sampling period (Tsait fi
n) / ”) and predicted departure sample etc.!'Jl (T
The error address generating section (17) calculates each sampling period (Ts*ttt++++/To) by performing arithmetic processing using the functional configuration shown in FIG. , (Tsam
T. . . /To) When calculating each coefficient address based on the information, [Ts (.1, /T S + t n , Co =
[Ts(.ut+/To] * 2 n/ [T
s tr , u / To ], the ratio of the output sampling period (Tstcut+) to the manual sampling period (Tut-+) is calculated as a normalized high-precision value [Ts (.t+ /To ). I am trying to obtain it as follows.

In FIG. 7 showing the functional configuration of arithmetic processing in the coefficient address generation section (17), the predicted input sampling period (Tsait li*l/To) information and the predicted output sampling period (That□.□+/To) ) information is supplied to the divider (71), and the division output (Tsast lou&+ /Tsait (
In the adder (72) to which i+t)) is supplied, a register (73) and an overflow check circuit (74)
New coefficient address data is calculated by cumulatively adding the coefficient address data of one cycle before and its overflow check data (2-'), which are fed back via . In addition, the above-mentioned overflow check circuit (7
The overflow check data according to 4) is stored in the first buffer memory (2), such as by reading twice the sample value (Xt) of the sample sequence fXt) necessary for the correction process in the digital signal processing unit (7). 6) is used for control.

H Effects of the Invention In the sampling frequency conversion device according to the present invention, the input sampling period and A digital signal processing means that operates with a local clock period shorter than the output sampling period performs interpolation calculation processing using filter coefficients that give the impulse response characteristic of the low-pass filter with respect to a sampling frequency that is 2M times the input sampling frequency. By doing so, interpolated sample values at output sample points can be calculated with high precision. In addition, in this sampling frequency conversion device, the input sampling period and the local clock period are calculated by cumulatively adding the error value of the sampling period quantized by the local clock period in the prediction calculation means to the predicted sampling period. A coefficient address generating means predicts and calculates the ratio and the ratio of the output sampling period and the local clock period, and calculates the input sampling period and the output sampling period with respect to the local clock period obtained by the predictive calculation means. By dividing each ratio data and cumulatively adding the values, the filter coefficient address data necessary for the above interpolation processing can be calculated with high accuracy without generating a control error even for step-like phase errors. be able to. Furthermore, the memory control means in this sampling frequency conversion device detects an overflow of each cumulative addition process in the prediction calculation means or coefficient address generation means, and temporarily stores the sample values of the sample sequence obtained by the oversampling process. The write/read control for the first buffer memory for temporarily storing each sample interpolation value of the output sample point obtained by the interpolation calculation process is performed in accordance with the overflow detection output of each of the cumulative addition processes described above. Then, each sample string can be read out from each buffer memory at a desired timing, and sampling frequency conversion at an arbitrary conversion ratio can be performed with high accuracy with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a sampling frequency conversion device according to the present invention, FIG. The figure is a block diagram showing the functional configuration of the event detecting section constituting the sampling frequency converter, FIG. 4 is a schematic diagram for explaining the operation of the event detecting section, and FIG. 5 is the sampling frequency converter. 6 is a schematic diagram illustrating the operation of the adaptive prediction processing section, and FIG. 7 is a coefficient address generation section configuring the sampling frequency conversion device. FIG. 3 is a block diagram showing the functional configuration of the section. FIG. 8 is a block diagram showing a configuration example of a conventional sampling frequency conversion device, FIG. 9 is a schematic diagram showing the phase relationship between an input sample sequence and an output sample sequence in the conventional sampling frequency conversion device, and FIG. 10 and FIG. 11 are schematic diagrams for explaining the cotton interpolation processing operation and the digital filtering processing operation in the conventional sampling frequency conversion device. (1)...Signal input terminal (2), (3)...Black 2 input terminal (4)...
... Signal output terminal (5) ... Oversampling section (6), (8
) ... Buffer memory (7) ... Digital signal processing section (9) ... Local clock period section (10) ... Conversion system tn section

Claims (1)

[Claims] Oversampling processing means for converting an input sample sequence into a sample sequence with a sampling frequency that is an integer (2^M) times the input sampling frequency; and a sample sequence output from the oversampling processing means. a first buffer memory for temporarily storing sample values;
The sample string read from the first buffer memory is subjected to interpolation calculation processing using a filter coefficient that gives the impulse response characteristic of a low-pass filter with respect to the double sampling frequency, and each sample point of the output sample string having the output sampling frequency is a second buffer memory for temporarily storing the interpolated sample values of the output sample sequence output from the digital signal processing means; and a sampling quantized at the local clock period. Predictive calculating means for predicting and calculating the ratio of the input sampling period to the local clock period and the ratio of the output sampling period to the local clock period by cumulatively adding error values with respect to the predicted sampling period of the period. By dividing each of the ratio data obtained by the prediction calculation means and cumulatively adding the values, filter coefficient address data necessary for the interpolation process is calculated and the coefficient address is given to the digital signal processing means. generating means; memory control means for detecting overflow of each cumulative addition processing result in the prediction calculation means or coefficient address generation means and controlling read/write to each of the buffer memories; 1/an integer (2) of the local clock cycle; A sampling frequency conversion device comprising: local clock generation means for outputting a local clock signal with a period of ^N).