JPS5835932A - Gettering of impurities - Google Patents

Gettering of impurities

Info

Publication number
JPS5835932A
JPS5835932A JP13419581A JP13419581A JPS5835932A JP S5835932 A JPS5835932 A JP S5835932A JP 13419581 A JP13419581 A JP 13419581A JP 13419581 A JP13419581 A JP 13419581A JP S5835932 A JPS5835932 A JP S5835932A
Authority
JP
Japan
Prior art keywords
substrate
thin film
stress
defects
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13419581A
Other languages
Japanese (ja)
Inventor
Yoichi Mada
間田 洋一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP13419581A priority Critical patent/JPS5835932A/en
Publication of JPS5835932A publication Critical patent/JPS5835932A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

Abstract

PURPOSE:To make defects to be generated in the whole region of the pattern adhering part, and to control quantitatively distribution inside of the surface of the defects having ability to absorb impurities by a method wherein a thin film having the edges is provided on the back of a semiconductor substrate, and the heat treatment is performed at the prescribed temperature. CONSTITUTION:An Si3N4 film or a polycrystalline Si thin film, etc., having internal stress is adhered on the back of the semiconductor substrate 2 of Si, GaAs, InSb, etc., according to the means of evaporation, etc. Then the film is made to be survived locally according to the photo etching method to form the thin film 1 having the edges. At this constitution, stress to be applied to the substrate 2 is decided as follows. Namely, when the substrate is the Si substrate, because yield stress to be generated when the heat treatment at 1,000 deg.C is performed to the substrate thereof is 7X10<5> dyne/cm<2>, the value obtained by dividing the product of internal stress of the thin film and thickness of the film by pattern breadth is specified to 2.8X10<5> dyne/cm<2> or more. Accordingly distribution inside of the surface of the defects to act as to absorb impurities is controlled quantitatively.

Description

【発明の詳細な説明】 本発明は、半導体装置の製造工程において、半導体基板
から重金属粒子のような有害不純物を捕集するゲッタリ
ング法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gettering method for collecting harmful impurities such as heavy metal particles from a semiconductor substrate in a semiconductor device manufacturing process.

一般に、半導体装量の材料である半導体基板に重金属粒
子(例えばFe、Or等)等が含まれると、その基板中
に形成される半導体素子の電気特性を劣化させることが
知られている。従来からこのような有害不純物をゲッタ
リング法 ング等の手段によリウエノ・の裏面に機械的に歪を加え
たり、膜応力を有する薄膜を一面に被着する方法等が提
案されている(例えば、特開昭55−17073号公報
参照)。しかし、これらの方法は、裏面の歪の程度を制
御しにくいため再現性に乏しく、また歪を加えることに
より、そりが発生するなどの問題点がある。
It is generally known that when heavy metal particles (eg, Fe, Or, etc.) are contained in a semiconductor substrate, which is a material for a semiconductor device, the electrical characteristics of a semiconductor element formed in the substrate are deteriorated. Conventionally, methods have been proposed in which such harmful impurities are mechanically strained on the back surface of the RIUENO by means such as gettering, and methods are applied such as applying a thin film with film stress to the entire surface (for example, , see Japanese Patent Application Laid-Open No. 55-17073). However, these methods have problems such as poor reproducibility because it is difficult to control the degree of distortion on the back surface, and warping may occur due to the addition of distortion.

本発明は、半導体基板の裏面に工、ソジを有する薄膜を
形成する工程と、その後この基板を熱処理する工程とを
含むことを特徴とし、その目的は基板の歪を定量的に制
御可能でかつ基板のそり発生の少ない不純物ゲッタリン
グ法を提供することにある。
The present invention is characterized in that it includes a step of forming a thin film having a roughness and a hardness on the back surface of a semiconductor substrate, and a step of subsequently heat-treating the substrate.The purpose of the present invention is to quantitatively control the distortion of the substrate. Another object of the present invention is to provide an impurity gettering method that causes less warping of the substrate.

先ず、本発明によるゲッタリング方法の原理を図面を用
いて説明する。
First, the principle of the gettering method according to the present invention will be explained using the drawings.

第1図は幅りの帯状パタンの薄膜を半導体基板の裏面に
形成した場合の断面を示した斜視図である。図において
、1は薄膜、2は半導体基板を表わす。幅りの薄膜1の
エツジはX=Oとx = Lとに対応する。この場合、
基板2は薄膜1のX二〇とx = Lの2個のエツジか
ら力を受ける。基板内の応力の各成分は、弾性体理論を
用いて次式のように表わされるわ ここで、σ8.σ、は各々X方向、X方向の垂直応力を
、τ8.はせん断応カ、を表わす。右辺の第1項目、第
2項目は各X ”” 0 +  x =Lのエツジによ
る応力成分である。定数Fは薄膜1の内部応力と膜厚と
の積である。式(1)〜(3)より、応力の絶対値の大
きい基板裏面付近(y二〇)では、σ8が他の成分より
も数桁以上大きく、基板の歪が主として叛により制御さ
れることが導かれる。
FIG. 1 is a perspective view showing a cross section of a thin film having a wide strip pattern formed on the back surface of a semiconductor substrate. In the figure, 1 represents a thin film and 2 represents a semiconductor substrate. The edges of the wide thin film 1 correspond to X=O and x=L. in this case,
The substrate 2 receives forces from two edges of the thin film 1, X20 and x=L. Each component of stress within the substrate is expressed as follows using elastic body theory. Here, σ8. σ represents the normal stress in the X direction and the normal stress in the X direction, respectively, and τ8. represents shear stress. The first and second items on the right side are stress components due to the edges of each X ``'' 0 + x =L. The constant F is the product of the internal stress of the thin film 1 and the film thickness. From equations (1) to (3), near the back surface of the substrate (y20) where the absolute value of stress is large, σ8 is several orders of magnitude larger than other components, indicating that the distortion of the substrate is mainly controlled by repulsion. be guided.

第2図は帯状パタンの薄膜により発生する応力の基板内
分布を示す図で、基板裏面付近でのσ の分布である。
FIG. 2 is a diagram showing the distribution of stress within the substrate generated by a thin film with a band-like pattern, and is the distribution of σ near the back surface of the substrate.

図は、膜応力3.5 X 109dyn/7 、膜厚3
000^、パタン幅100μmの場合である。
The figure shows a film stress of 3.5 x 109dyn/7 and a film thickness of 3.
000^, and the pattern width is 100 μm.

σ8はパタン中央部で最小値をとる。一般に、応力の値
が材料の降伏応力を越えると欠陥(転位等の結晶欠陥)
が発生する。従って、バタン中央部の応力の値が降伏応
力よりも大きい条件では、パタン被着部の全域で欠陥を
発生できる。
σ8 takes the minimum value at the center of the pattern. In general, if the stress value exceeds the material's yield stress, defects (crystal defects such as dislocations) will occur.
occurs. Therefore, under conditions where the stress value at the center of the batten is greater than the yield stress, defects can occur throughout the pattern adhered area.

この条件では、本発明の目的である不純物吸収の働きを
する欠陥の量を増加できるとともに、欠陥の量を定量的
に制御しやすい。
Under these conditions, it is possible to increase the amount of defects that function as impurity absorption, which is the object of the present invention, and it is easy to quantitatively control the amount of defects.

一般に、材料の降伏応力は高温に保持する場合には減少
するため、薄膜を被着した状態で熱処理(例えば、75
0〜1300℃の温度に一旦上げて下ろす)を行なうこ
とにより、勢処理を行なわない場合よりも小さい応力で
欠陥を発生できる。
In general, the yield stress of a material decreases when held at high temperatures, so heat treatment (e.g., 75
By raising the temperature once to 0 to 1300° C. and then lowering it, defects can be generated with less stress than when no stress treatment is performed.

このための条件は、 で弐わされる。The conditions for this are It makes me laugh.

以下、本発明を実施例によって詳細に説明する。Hereinafter, the present invention will be explained in detail with reference to Examples.

第3図は本発明の実施例を示す半導体基板の断面斜視図
である。本発明のゲッタリング方法は。
FIG. 3 is a cross-sectional perspective view of a semiconductor substrate showing an embodiment of the present invention. The gettering method of the present invention is as follows.

上記原理に基づくものであり、帯状パタンの薄膜1を複
数個用いることにより、不純物吸収の働きをする欠陥を
基板2の裏面の全域で形成できるとともに、その面内分
布を定量的に制御できる。この方法では、薄膜被着部分
の面積を基板面積に比較して小さくできる(欠陥はエツ
ジ部分で発生しやすい)ため、薄膜を一様に被着した従
来のゲッタリング法に比べて基板のそりを低減できると
いう利点もある。
It is based on the above principle, and by using a plurality of thin films 1 having a band-like pattern, it is possible to form defects that function as impurity absorption over the entire back surface of the substrate 2, and also to quantitatively control the in-plane distribution. With this method, the area of the thin film deposited part can be made smaller compared to the substrate area (defects are more likely to occur at the edges), so the warpage of the substrate is better than with the conventional gettering method, which deposits the thin film uniformly. It also has the advantage of being able to reduce

以下、具体的に説明する。This will be explained in detail below.

半導体基板2(本実施例の場合はSi基板であるが、G
aAs基板、 InSb基板等であってもよい)の裏面
に内部応力を有するシリコン窒化膜もしくはポリシリコ
ン等の薄膜をOVD、蒸着、スパッタ法等の手段により
形成する。次にこの薄膜を通常の写真食刻法により局所
的に残すことにより、容易にエツジを有する薄膜1を半
導体基板2の裏面に形成できる。基板2に与える応力は
以下のようにして決定する。8i基板にたいして100
0℃の熱処理を行なう場合には、その温度における降伏
応力が7 X 105dyn/(Jであるため、式(5
)より、薄膜の内部応力と膜厚との積Fをバタン幅りで
割った値が2.8 X 105dyn/(7以上である
必要がある。例えば、内部応力が3.5 X 10’ 
dyn/c4 。
Semiconductor substrate 2 (Si substrate in this example, but G
A thin film such as a silicon nitride film or polysilicon having internal stress is formed on the back surface of a substrate (which may be an aAs substrate, an InSb substrate, etc.) by OVD, vapor deposition, sputtering, or the like. Next, by leaving this thin film locally by ordinary photolithography, the thin film 1 having edges can be easily formed on the back surface of the semiconductor substrate 2. The stress applied to the substrate 2 is determined as follows. 100 for 8i board
When heat treatment is performed at 0°C, the yield stress at that temperature is 7 x 105 dyn/(J, so the formula (5
), the product F of the internal stress of the thin film and the film thickness divided by the batten width must be 2.8 x 105 dyn/(7 or more. For example, if the internal stress is 3.5 x 10'
dyn/c4.

バタン幅が3.2屡の場合、薄膜の膜厚は1000A以
上にする。
If the batten width is 3.2 mm, the thickness of the thin film should be 1000 A or more.

以上エツジを有する帯状パタンの薄膜の場合について述
べて来たが、他の形状例えば格子状でも円形状パタンの
場合でも同様な効果を期待できる。
Although the case of a thin film with a band-shaped pattern having edges has been described above, similar effects can be expected in the case of other shapes such as a lattice-like or circular pattern.

第4図は本発明の他の実施例であって、円形状パタンの
薄膜を半導体基板の裏面に形成した場合の断面を示した
斜視図である。
FIG. 4 is a perspective view showing a cross section of another embodiment of the present invention, in which a thin film with a circular pattern is formed on the back surface of a semiconductor substrate.

円形状パタンの直径を充分小さくすることにより、パタ
ン被着部会域で欠陥を発生できるため、不純物吸収の働
きをする欠陥の面内分布を定量的に制御できる。
By making the diameter of the circular pattern sufficiently small, defects can be generated in the area where the pattern is adhered, so that the in-plane distribution of defects that act as impurity absorption can be quantitatively controlled.

以上説明したように、本発明によるゲノタリングのため
の基板裏面歪の形成方法は、裏面に被着する薄膜の膜応
力・膜厚・バタン寸法(バタンの疎・密)ならびに熱処
理温度を制御するととにより、基板内の有害不純物を吸
収する働きをする欠陥の面内分布を定量的に制御できる
という特長を有する。また、薄膜被着部分の面積を基板
面積に比較して小さくできるため、裏面に歪を与える薄
膜を一様に被着した従来のゲッタリング法に比べて、そ
り発生を少なくできるという利点もある。
As explained above, the method for forming distortion on the back side of a substrate for genotattering according to the present invention involves controlling the film stress, film thickness, batten size (sparseness/denseness of the batten), and heat treatment temperature of the thin film deposited on the backside. This method has the advantage of being able to quantitatively control the in-plane distribution of defects that function to absorb harmful impurities within the substrate. Additionally, since the area of the thin film deposited part can be made smaller compared to the substrate area, it has the advantage of reducing warpage compared to the conventional gettering method, which uniformly deposits a thin film that causes distortion on the back surface. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の詳細な説明するための半導体基板の断
面を示した斜視図、第2図は帯状バタンの薄膜により発
生する応力の基板内分布を示す図第3図及び第4図はい
ずれも本発明の実施例で半導体基板の断面を示した斜視
図である。 1・・・薄膜    2・・・半導体基板特許出願人 
日本電信電話公社 代理人弁理士 中 村 純 之 助2013 わ 11 図 第2図 /ぐタンキe、4.4
FIG. 1 is a perspective view showing a cross section of a semiconductor substrate for explaining the present invention in detail, FIG. 2 is a diagram showing the distribution of stress within the substrate caused by the thin film of the band-shaped baton, and FIGS. 3 and 4 are Both are perspective views showing a cross section of a semiconductor substrate in an embodiment of the present invention. 1...Thin film 2...Semiconductor substrate patent applicant
Nippon Telegraph and Telephone Public Corporation Patent Attorney Junnosuke Nakamura 2013 Wa11 Figure 2/Gutanki e, 4.4

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の裏面にエツジを有する薄膜を形成する工程
と、その後この基板を熱処理する工程とを含むことを特
徴とする半導体基板の不純物ゲッタリング法。
An impurity gettering method for a semiconductor substrate, comprising the steps of forming a thin film having an edge on the back surface of the semiconductor substrate, and then heat-treating the substrate.
JP13419581A 1981-08-28 1981-08-28 Gettering of impurities Pending JPS5835932A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13419581A JPS5835932A (en) 1981-08-28 1981-08-28 Gettering of impurities

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13419581A JPS5835932A (en) 1981-08-28 1981-08-28 Gettering of impurities

Publications (1)

Publication Number Publication Date
JPS5835932A true JPS5835932A (en) 1983-03-02

Family

ID=15122649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13419581A Pending JPS5835932A (en) 1981-08-28 1981-08-28 Gettering of impurities

Country Status (1)

Country Link
JP (1) JPS5835932A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5189508A (en) * 1988-03-30 1993-02-23 Nippon Steel Corporation Silicon wafer excelling in gettering ability and method for production thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5189508A (en) * 1988-03-30 1993-02-23 Nippon Steel Corporation Silicon wafer excelling in gettering ability and method for production thereof

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