JPS63114144A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To decrease crystal grain boundaries having a large number of defects existing in a metallic wiring, and to improve the reliability of the metallic wiring by previously arranging and forming a plurality of fine grooves in parallel to each other to the surface of an insulator layer before shaping a metallic wiring layer. CONSTITUTION:A plurality of fine grooves 13 are disposed and shaped in parallel to each other to the surface of a insulator layer 12, and an Al film 14 is formed onto the insulator layer 12 through a sputtering method. When a semiconductor substrate is heated during sputtering at that time, an effect that surface mobility is increased is displayed at a time when sputtering Al atoms are shaped onto the insulator layer, and a crystal orientation is made easy to be further aligned. Accordingly, since separate crystal grain constituting a metallic wiring layer mutually has approximately the same crystal orientation, there hardly exist crystal defects on the crystal grain boundaries, and the wiring approximately close to a single crystal can be formed, thus preventing the generation of defective such as stress migration, then improving the reliability of the wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device in which a metal wiring layer is improved.

(Prior Art) In recent years, the dimensions of semiconductor elements have been miniaturized for the purpose of increasing the integration of semiconductor devices, and elements with submicron dimensions of 1 μm or less have become a reality. Aluminum (17') is most commonly used as metal wiring between elements. AI wiring depends on the quality of the film forming process,
Low resistance.

This is because it has many advantages such as easy formation of contact with Si. On the other hand, A and f' wirings have drawbacks such as easy growth of hillocks, weakness to electromigration, and weakness to stress, and there are many unresolved problems in using them as wiring with a submicron width of 1 [μm] or less. There is a problem.

Recently, tungsten (W) has been used instead of AI.

Attempts have been made to use high melting point metals such as molybdenum (MO) as wiring. High melting point metal wiring is resistant to hillocks, electromigration, etc., and has higher reliability than AI. However, in addition to the drawback of high interconnect resistance, submicron-width interconnects have a coefficient of thermal expansion that is about an order of magnitude different from that of the passivation insulating layer, so as the interconnect width becomes thinner, the stress applied to the interconnect metal increases, causing stress. There is a concern that wire breakage may occur.

The various reliability problems of metal wiring described above are thought to be caused by the following phenomenon.

A, f? , W, Mo, etc. are formed by methods such as sputtering and vapor deposition, and the metal films formed in this way exhibit a polycrystalline structure consisting of many fine crystal grains. Therefore, in wiring formed from a metal film having a polycrystalline structure, grain boundaries 4 are formed between individual crystal grains 41 as shown in FIG.
2 exists. Many crystal defects such as dislocations, stacking faults, and voids exist in the grain boundaries, and the grain boundaries serve as diffusion paths for the constituent metal atoms. It is no exaggeration to say that reliability problems such as hillocks, electromigration, and stress migration in metal wiring are all caused by the existence of these grain boundaries (Reference “Th1n Films -!ntcrdil
'('usions and Reactions'
, Edited by Poate, J.M.,T.
u, ni, n, and mayer, j, m, john
Willey (1987)).

Therefore, in order to solve these reliability problems,
It is desirable to form single crystal metal interconnects without grain boundaries. However, using sputtering, vapor deposition, etc., LSI
It is extremely difficult to form a single crystal metal film over the entire size of the chip (approximately 10+u+2). for example,
In the case of the sputtered A film, since the film formation rate is currently high (1 μm/m 1 nt), it is possible to form a relatively large polycrystalline film with a grain size of several [μ77Z], and moreover, as shown in Fig. 5(a).
As shown in the figure, the planes parallel to the substrate surface have a preferred orientation aligned with the [1111 plane. In the figure, 43 indicates crystal grains with uniform crystal orientation, 44 indicates crystal grains with greatly different crystal orientations, and 4 indicates crystal grains with substantially different crystal orientations.
5 indicates a base insulating layer. However, Fig. 5(b)
As shown in the figure, the orientations vary within the plane, and moreover, there are always crystal grains with greatly different orientations in some parts.

As described above, since a considerable number of crystal grains having different orientations exist inside the wiring, wiring defects are likely to occur from such locations. The reason why crystal grains with different orientations as described above always exist is because microcrystal grains with different orientations have already grown during the t-month cutting process in which the A film grows on the underlying insulating film. be.

(Problems to be Solved by the Invention) As described above, in the conventional method, it is difficult to form a single-crystal metal wiring without grain boundaries, and there are many crystal grains with different orientations. Defects such as hillocks, electromigration, and stress migration occur at crystal grain boundaries where the crystal orientations differ greatly, which causes wiring defects.

The present invention has been made in consideration of the above circumstances, and its purpose is to provide a semiconductor device that can reduce defect-prone crystal grain boundaries that exist in interconnects and improve the reliability of metal interconnects. The purpose of this invention is to provide a method for manufacturing the same.

[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to control the orientation of microcrystal grains in the initial growth process of a metal film to form a metal film closer to a single crystal on an insulating film. The purpose is to form fine grooves on the underlying insulating layer as a means of controlling the orientation of crystal grains.

That is, the present invention provides a method for manufacturing a semiconductor device including a step of forming an insulating layer on a semiconductor substrate on which an element is formed and then forming a metal wiring layer on the insulating layer. In this method, a plurality of fine grooves are arranged and formed in parallel on the surface of the insulating layer in advance.

(Function) According to the present invention, since the individual crystal grains constituting the metal wiring layer have substantially the same crystal orientation, there are almost no crystal defects at the grain boundaries, and the wiring is almost monocrystalline. can be formed. Therefore, conventionally, hillocks were caused by grain boundaries.

Defects such as electromigration and stress migration are less likely to occur, and the reliability of wiring is improved.

Furthermore, since the influence of electron scattering due to grain boundaries is reduced, it becomes possible to suppress an increase in wiring resistance to a minimum.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a cross-sectional view showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. First, as shown in FIG. 1(a), on a Si substrate (semiconductor substrate) 11 on which an element is formed,
Deposit an insulator layer 12, such as 5i02. The steps up to this point are completely the same as the conventional method.

Next, as shown in FIG. 1(b), a plurality of fine grooves 13 are formed in parallel on the surface of the insulating layer 12. Here, it is desirable that the tray 13 has a level difference that does not cause defective step coverage or etching residue of the metal wiring pattern when forming metal wiring, which will be described later. For example, a desirable amount of step is greater than or equal to the diameter of the metal atom to be grown (1 Å or more), but less than a step that does not cause step coverage defects at all (1/1 degree or less of the thickness of the metal wiring layer), that is, 1 to 1. It is about 1000 [in]. Furthermore, considering the surface mobility of the metal atoms to be grown, it is sufficient for the patterning density to be about 100 μml to 1 μml. Further, the method for forming the fine grooves may be a pattern forming method using a normal resist, or a direct etching method using a fine ion beam.

Next, as shown in FIG. 1(c), A! is deposited on the insulating layer 12 by sputtering. A film 14 is formed.

At this time, the semiconductor substrate was heated at 100 to 500 ['
It is desirable to heat to about C]. This heating has the effect of increasing the surface mobility at the time when the sputtered A atoms are formed on the insulating layer, making it easier to align the crystal orientation. In addition, in order to grow larger crystal grains, A,
After forming the 11' film 14, heat treatment may be performed at the above temperature.

In the above-mentioned A film formation, the metal atoms that have reached the uneven substrate generally move through the substrate and then form nuclei along the stepped portions. The reason for this is that at the step part,
This is because the free energy of metal atoms is the lowest, making it a stable place (Journal of Chemi
cal Physics, 38 p2698-2704
(1963), Walton et al., “Nu
creation of 511veron Sodi
um Chlorlde'') o In the case of A, it was mentioned earlier that the (111) preferred direction is shown even on an uneven substrate, but on an uneven substrate, the two-dimensional direction is shown along the direction of the unevenness within the substrate. Therefore, in the A, 11' film formed in this way, even if grain boundaries exist, the difference in orientation is small, and the film, which is close to a single crystal, has a large area. It is formed over a period of time.

Here, the crystal orientation in the state where the A-no film 14 is formed as shown in FIG. 2 is as shown in FIG. 3. That is, when A, 17 Ill 14 shown in FIG. 2 is viewed from the direction of arrow A, the crystal grains 21 are nearly rectangular as shown in FIG. 3(a), and each crystal grain 21 in the plane is The crystal orientation becomes well aligned. Similarly, the A membrane 14 shown in FIG.
The crystal orientation in the thickness direction when viewed from the direction of arrow B is also well aligned as shown in Figure 3(b).In particular, as shown in Figure 3(a), the crystal orientation in the plane is The main difference from the conventional method is that they are all aligned.

Next, as shown in FIG. 1(d), the A film 14 is patterned to form wiring. AI obtained in this way! The wiring does not contain many defects because it is close to a single crystal throughout the wiring, or even if it includes grain boundaries, the difference in orientation is small. Therefore, the entire wiring is strengthened without any weak points, and is highly reliable against hillocks, electromigration, stress migration, etc.
, f? It is wired.

Thus, according to the method of this embodiment, the crystal orientation of the AI film 14 formed on the insulator layer 12 can be aligned, and the occurrence of defects at crystal grain boundaries can be significantly reduced.

Therefore, the reliability of the A wiring can be improved, and its usefulness in manufacturing semiconductor devices is enormous. Another advantage is that it can be realized by a simple process of just providing the grooves 13 on the surface of the insulating layer 12.

Note that the present invention is not limited to the method of the embodiment described above. For example, the metal film is A, l? The material is not limited to, and high melting point metals such as W and Mo can be used. Further, the step of the groove does not need to be vertical, and may be inclined. Furthermore, the arrangement pattern of the grooves is not limited to a multiline pattern, but may be a grid pattern. In addition, various modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] As detailed above, according to the present invention, by forming grooves in advance on the surface of the insulating layer, the crystal orientation of the metal film formed on the insulating layer can be aligned. . Therefore, the occurrence of defects at grain boundaries can be reduced.

The reliability of metal wiring can be improved.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIGS. 2 and 3 are for explaining the operation of the above embodiment, respectively. FIG. 3 is a schematic diagram showing the state of crystal orientation in the direction of arrows A and B in FIG. 2, and FIGS. 4 and 5 each explain the problems of the conventional method. FIG. 4 is a schematic diagram showing the state of grain boundaries, and FIG. 5 is a schematic diagram showing the state of crystal orientation in the thickness direction and in-plane. DESCRIPTION OF SYMBOLS 11... Si substrate (semiconductor substrate), 12... Insulator layer, 13... Groove, 14... A film (metal film), 21
...Crystal grain, 22...Crystal grain boundary. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3

Claims (6)

[Claims] (1) A step of forming an insulating layer on the semiconductor substrate on which the element is formed, a step of forming a plurality of fine grooves in parallel on the surface of the insulating layer, and then a step of forming a plurality of fine grooves on the surface of the insulating layer. 1. A method for manufacturing a semiconductor device, comprising the step of forming a metal wiring layer. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the depth of the groove is 1 to 1000 [Å]. (3) The mutual spacing between the grooves is 100 [Å] to 1 [μm]
A method for manufacturing a semiconductor device according to claim 1, characterized in that: (4) The method of manufacturing a semiconductor device according to claim 1, wherein the groove has an inclination. (5) The method for manufacturing a semiconductor device according to claim 1, wherein the metal wiring layer is formed on the insulator layer and then subjected to a heat treatment. (6) The method of manufacturing a semiconductor device according to claim 1, wherein the grooves are arranged in a grid pattern.