KR101276317B1 - Method of controlling wafer warpage by SiGe layer deposition and Wafer manufactured thereof - Google Patents

Abstract

The present invention discloses a method of controlling warpage of a wafer by deposition of a Si _{1 - x} Ge _x layer and a wafer made by the method. The warpage control method of the wafer by the deposition of the Si _{1 - x} Ge _x layer according to the present invention, (a) Ge mol of the Si _1-x Ge _x layer required to cancel the warpage according to the degree of warpage of the wafer through repeated experiments. Quantifying the content% and the formation thickness of the Si _1-x Ge _x layer; (b) loading the wafer in need of warpage control into a deposition chamber of a Si _1-x Ge _x layer; And (b) depositing a Si _1-x Ge _x layer on the back surface of the wafer, not the process surface, and according to the degree of warpage of the wafer to be offset when the Si _1-x Ge _x layer is deposited. The Si _1-x Ge _x layer is deposited by the Ge molar content% and thickness quantified in the step).

In accordance with the present invention, controlling the molar content% and the Si _1-x Ge _x layer thickness of the Ge and it is possible to quantitatively control the amount of deflection caused by the Si _1-x Ge _x layer relatively simply compared to conventional There is an advantage that the warpage of the wafer can be eliminated, and contaminants are not caused as compared with the prior art, which forms a metal silicide layer to offset the warpage of the wafer.

Wafer, warpage, warpage offset

Description

Method of controlling the warpage of a wafer by deposition of a silicon layer and a wafer manufactured by the method {Method of controlling wafer warpage by SiGe layer deposition and Wafer manufactured Technical}

The following drawings attached to this specification are illustrative of preferred embodiments of the present invention, and together with the detailed description of the invention to serve to further understand the technical spirit of the present invention, the present invention is a matter described in such drawings It should not be construed as limited to.

1 is a cross-sectional view of a silicon wafer in which warpage with a bow value of (−) occurs.

2 is a cross-sectional view of a silicon wafer in which warping with a positive bow value occurs.

FIG. 3 is a graph showing changes in bow values according to the molar content of Ge when the Si _1-x Ge _x layer is deposited on the back surface of the silicon wafer.

Figure 4 is a graph showing the change of bow values of the Si _1-x Ge _x layer thickness at the time of depositing the Si _1-x Ge _x layer on the back surface of the silicon wafer.

FIG. 5 is a graph showing the thermal expansion coefficient of the Si _{1 - x} Ge _x layer according to the molar content of Ge.

6 is a graph showing the thermal expansion coefficient of the Si _1-x Ge _x layer with the formation temperature of the Si _1-x Ge _x layer.

7 and 8 are cross-sectional views illustrating a method of controlling warpage of a wafer according to a first embodiment of the present invention.

9 and 10 are cross-sectional views illustrating a method of controlling warpage of a wafer according to a second embodiment of the present invention.

<Main reference number in drawing>

W: Wafer G: Si _1-x Ge _x Layer

A: wafer processing surface

The present invention relates to a method for controlling the degree of bending (warpage) of the wafer, and more particularly, the Ge content in the Si _1-x Ge _x layer by depositing a Si _1-x Ge _x layer on a surface of a wafer or a Si _{1 - It} relates to a method that can adjust the degree of warpage of the wafer by adjusting the thickness of the _x Ge _x layer.

In the semiconductor manufacturing process, the degree of warpage of the wafer is one of the quality of the wafer that must be controlled because it causes various problems in the chucking and handling of the wafer. In particular, when a material other than Si is epitaxially grown on a Si wafer during semiconductor manufacturing, stress is generated due to a difference in crystal lattice constant between the material layer and Si grown on the wafer and a difference in thermal expansion coefficient. Warping of the wafer is a phenomenon that occurs to release this stress. In the case of an epitaxial wafer in which a high-resistance Si epitaxial layer is formed on a low-resistance Si wafer, the low-resistance wafer and the epitaxial layer are formed depending on the dopant concentration injected into the wafer and the epitaxial layer. The difference between the crystal lattice mismatch and the coefficient of thermal expansion occurs, and in this case, the stress is induced and the warpage of the wafer occurs.

Conventionally, in order to prevent the warpage of the wafer, a method of canceling the warpage of the wafers by applying a stress in the reverse direction of the wafer bending direction on the back surface of the wafer has been mainly used. As an example of this method, US Patent No. 4,631,804 discloses a method of forming polysilicon on the entire surface of a Si wafer to minimize the degree of warpage of the wafer. However, the method according to the 804 patent has a disadvantage in that the process for adjusting the warping degree of the wafer is complicated because the grinding step of polysilicon should be accompanied. As another prior art, US Pat. No. 4,830,984 discloses a method of offsetting the warpage of a wafer caused by a material formed on the front surface of a wafer by depositing a metal silicide material on the back side of the wafer. However, as described in the 984 patent, the use of metal silicides to offset the warpage of wafers may cause metal contamination during the deposition of metal silicides, which is not suitable for the semiconductor device manufacturing process that requires thorough control of contamination levels. have.

The present invention was devised to solve the above-mentioned problems of the prior art, and deposits a material film that can offset the warpage of the wafer onto the wafer to control the warpage of the wafer, but does not require a complicated mechanism for controlling the warpage of the wafer. It is an object of the present invention to provide a wafer warpage control method which does not cause contamination in the process and a wafer manufactured by the method.

The warpage control method of the wafer by the deposition of the Si _1-x Ge _x layer according to the present invention for achieving the above technical problem is (a) Si _1-x necessary to offset the warpage according to the degree of warpage of the wafer through repeated experiments the step of quantifying the Ge mole% and the content of _1-x Ge _x layer is formed Si thickness of the Ge _x layer; (b) loading the wafer in need of warpage control into a deposition chamber of a Si _1-x Ge _x layer; And (b) depositing a Si _1-x Ge _x layer on the back surface of the wafer, not the process surface, and according to the degree of warpage of the wafer to be offset when the Si _1-x Ge _x layer is deposited. The Si _1-x Ge _x layer is deposited by the Ge molar content% and thickness quantified in the step).

In the present invention, the deposition temperature of the Si _1-x Ge _x layer may be further controlled to offset the degree of warpage of the wafer.

According to an aspect of the present invention, the wafer is a wafer in which the center of the wafer is warped convexly when the processing surface of the wafer is facing upward, the Si mole content% of the Si _1-x Ge _x layer and Si ₁ It regulates the _-x Ge _x layer thickness to less than the predetermined threshold value. For example, the threshold for the group _1-x Ge _x layer Ge Si mol% and the content of _1-x Ge _x layer thickness of Si in a may be respectively 30% and 1um.

According to another aspect of the present invention, the wafer is a wafer in which the center of the wafer is warped downward when the processing surface of the wafer is turned upward, and the% Ge mole content of the Si _1-x Ge _x layer and Si Adjust the thickness of the _1-x Ge _x layer to exceed a predetermined threshold. For example, the threshold for the _1-x Ge _x layer Ge Si mol% and the content of _1-x Ge _x layer thickness of Si in a may be respectively 30% and 1um.

In order to achieve the above technical problem, a wafer whose warpage is canceled by a Si _1-x Ge _x layer includes: a semiconductor wafer in which a first magnitude of stress is induced in a first direction; And a Si _1-x Ge _x layer deposited on the back side of the wafer processing surface, wherein the Si _1-x Ge _x layer is in a direction opposite to the first direction and exerts a stress of the same magnitude as the first size. It is characterized in that applied to the back.

Preferably, the magnitude of the stress caused by the Si _1-x Ge _x layer is controlled by the molar content of Ge and the thickness of the Si _{1 - x} Ge _x layer.

Preferably, the direction of stress caused by the Si _1-x Ge _x layer is controlled by the molar content of Ge and the thickness of the Si _1-x Ge _x layer.

In the present invention, the wafer may be a Si wafer in which a semiconductor device is integrated on a processing surface, a Si epitaxial wafer on which an epitaxial layer is grown on a processing surface, or a relaxed SiGe wafer on which a strained silicon film is deposited on the processing surface.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms and words used in the present specification and claims should not be construed as limited to ordinary or dictionary terms, and the inventor should appropriately interpret the concepts of the terms appropriately It should be interpreted in accordance with the meaning and concept consistent with the technical idea of the present invention based on the principle that it can be defined. Therefore, the embodiments described in the present specification and the configurations shown in the drawings are merely the most preferred embodiments of the present invention and are not intended to represent all of the technical ideas of the present invention. Therefore, various equivalents It should be understood that water and variations may be present.

The present inventors selected Si _1-x Ge _x as a kind of material for canceling the warpage of the Si wafer. And then adjusting the Ge mole Amount% and Si forming the thickness of the _1-x Ge _x layer in forming the Si _1-x Ge _x layer on the Si wafer was evaluated in the bending amount of Si wafer quantitatively by the bow value. As a result, it was found that not only the amount of warpage of the Si wafer was changed but also the direction in which the center of the Si wafer was convex was changed by controlling the molar content of Ge and the thickness of the Si _1-x Ge _x layer. For reference, the bow value was measured by the method described in Korean Patent Standard Publication No. 02-386, "Measurement of Thickness, Thickness Change, and Bow of Si Wafer (May 29, 2002)".

Table 1 below shows the change in the bow value of the Si wafer according to the% mole content of Ge and the formation thickness of the Si _{1 - x} Ge _x layer. The Si _{1 - x} Ge _x layer was formed using chemical vapor deposition, and SiCl ₂ H ₂ gas and GeH ₄ gas were used as the reaction source gas. However, the present invention is not limited by the method of forming the Si _1-x Ge _x layer. Therefore, the Si _{1 - x} Ge _x layer may be deposited by epitaxial growth, metal organic chemical vapor deposition, or the like. The Si wafer on which the Si _{1 - x} Ge _x layer was formed was 200 mm in diameter and 725 um in thickness. In the column of the table, the DCS column represents the supply flow rate (unit: sccm) of the Ge source gas supplied to control the mole content% of Ge.

Sample # DCS Ge% Thickness
(Μm) Bow
(Μm) #One 30 14.48 0.64 22.94 #2 30 25.75 0.73 8.116 # 3 30 42.52 0.93 -4.424 #4 60 8.62 1.18 18.857 # 5 60 16.16 1.23 19.129 # 6 60 26.63 1.39 3.358 # 7 60 43.71 1.72 -29.018

In Table 1, the bow value has a (+) or (−) value, and the convex direction of the center of the Si wafer is changed depending on what the sign of the bow value is.

Specifically, FIG. 1 is a cross-sectional view of the wafer when the bow value is (-) and FIG. 2 is a cross-sectional view of the wafer when the bow value is (+). If the bow value is (-), the wafer W is convex downward when the cross section of the wafer W is viewed with the Si _1-x Ge _x layer G faced up on the deposited wafer W. Have If the bow value is (+), the wafer W has a convex shape when the cross-section of the wafer W is viewed with the Si _1-x Ge _x layer G facing the surface of the wafer W deposited thereon. Have In addition, the larger the absolute value of the bow value, the greater the degree of deformation of the wafer W.

FIG. 3 is a graph illustrating a change in bow value of Si wafers based on the% Ge mole content of the Si _{1 - x} Ge _x layer in the bow value measurement results of the Si wafers shown in Table 1 above, and FIG. It is a graph showing the change of the bow value of the Si wafer on the basis of the thickness of the Si _{1 - x} Ge _x layer in the measurement result of the bow value of the Si wafer.

In Figures 3 and 4, ◆ is the case where the flow rate of SiCl ₂ H ₂ gas used for the deposition of the Si _1-x Ge _x layer is set to 30sccm, ■ is SiCl ₂ used for the deposition of the Si _1-x Ge _x layer This is the case when the flow rate of the H ₂ gas is set to 60 sccm.

3 and 4, the Si _1-x Ge _x layer, if this be deposited Si _1-x Ge _x layers of Ge molar content% and Si _1-x Ge _x layer thickness of contained within on a Si wafer Therefore, it can be seen that the warping degree of the wafer is changed. That is, as the molar content% of Ge increases or as the thickness of the Si _1-x Ge _x layer increases, the bow value increases in the negative direction. Specifically, when it is more than 30% of the molar content% _1-x Ge _x layer and the Si has a thickness of the Si _1-x Ge _x layer exceeds 1um bow value - is a (). If the bow value is negative, the center of the wafer will be convex down. Conversely, as the% content of Ge decreases or the thickness of the Si _{1 - x} Ge _x layer decreases, the bow value tends to increase in the (+) direction. Specifically, the mol% of the content of _1-x Ge _x layer is Si and less than 30% and the thickness of the Si _1-x Ge _x layer is less than 1um bow value (+). When the bow value becomes positive, the center of the wafer becomes convex upward.

Referring to Table 1 and FIGS. 3 and 4 described above, when the Si _{1 - x} Ge _x layer is deposited on a Si wafer, the Ge mole content% and the thickness of the Si _{1 - x} Ge _x layer are controlled, based on the Bow value. It can be seen that it is possible to adjust the warping degree of the wafer to about +20 ~ -30um.

5 is a graph showing the measured and as a result a change of the thermal expansion coefficient of the Si _1-x Ge _x according to the mol% of the content of Ge in 27 ℃, 6 is Si _1- due to temperature for each mol% of the content of Ge _It is a graph showing the change of thermal expansion coefficient of _x Ge _x .

5 and 6, the thermal expansion coefficient of Si _1-x Ge _x increases as the molar content of Ge increases at the same temperature, and especially when the molar content of Ge exceeds 0.85%. The increasing slope of becomes larger. Under the condition that the molar content of Ge is fixed, the coefficient of thermal expansion increases as the temperature increases, and as the molar content of Ge increases, the coefficient of thermal expansion of Si (X = 0) and the coefficient of thermal expansion of Si _1-x Ge _x It can be seen that the difference gradually increases. As shown in FIG. 5, when the mole content% of Ge is low, the difference in thermal expansion coefficient between Si _1-x Ge _x and Si is not large, so that the lattice constant mismatch between Si _1-x Ge _x and Si is less than the difference in thermal expansion coefficient. Although the main cause of warpage, the increase in the mole content of Ge increases the difference in coefficient of thermal expansion between Si _1-x Ge _x and Si, so that the difference in thermal expansion coefficient is higher than the lattice constant mismatch between Si _1-x Ge _x and Si. It is a major cause of bending. Therefore, it can be seen that the large mole content of Ge can be a factor that can control the warpage of the Si wafer even at the temperature at which the Si _1-x Ge _x layer is formed.

Then, on the basis of the above description, when the Si _1-x Ge _x layer is deposited on the Si wafer, the mechanism in which the warpage shape of the wafer varies according to the mole content of Ge and the thickness of the Si _1-x Ge _x layer is as follows. same. When first depositing a Si _1-x Ge _x layer on a Si wafer, if the molar content of Ge is less than 30% and the thickness of the Si _1-x Ge _x layer is less than 1 um, then the thermal expansion coefficient between Si _1-x Ge _x and Si The stress generated by the crystal lattice mismatch between Si and Si _1-x Ge _x dominates more than the stress caused by the difference of. Therefore, even when the Si _1-x Ge _x layer is deposited at a high temperature (600 to 1200 degrees) and cooled to room temperature, the wafer is convexly deformed upward due to the stress caused by lattice constant mismatch, rather than the difference in thermal expansion coefficient. In contrast, when depositing a Si _1-x Ge _x layer on a Si wafer, if the molar content of Ge is greater than 30% and the thickness of the Si _1-x Ge _x layer is greater than 1 um, the lattice of Si and Si _1-x Ge _x Rather than the effect of stress due to mismatch, the stress caused by the difference in thermal expansion coefficient of Si and Si _1-x Ge _x is dominant. Therefore, after depositing the Si _1-x Ge _x layer at a high temperature (600-1200 degrees) and cooling to room temperature, the wafer is convexly deformed downward.

Meanwhile, in depositing a Si _1-x Ge _x layer on the surface of a Si wafer, the bow value of the wafer according to the% mole content of Ge and the thickness of the Si _1-x Ge _x layer is affected by the diameter of the wafer and the thickness of the wafer. Receive. Therefore, it is obvious that the threshold value for the thickness of the Si _1-x Ge _x layer and the mole content% of Ge in which the bow value is converted from (+) to (-) can be changed.

When the wafer warpage control method according to the present invention is applied to the actual process, the molar content of Ge and Si _1-x Ge _x which can accurately cancel the warpage through an iterative test-run process on the wafer where the warpage actually occurs. After calculating the thickness of the layer quantitatively, the Si _1-x Ge _x layer may be deposited on the wafer according to the calculated conditions to offset the warpage generated in the wafer. At this time, the Si _1-x Ge _x layer is formed on the back side of the wafer processing surface, and the Si _1-x Ge _x layer applies the same size stress to the back side of the wafer in a direction opposite to the stress that caused the warpage of the wafer. Herein, the processed surface of the wafer means a surface of a wafer on which various semiconductor devices are integrated. It is apparent that the tester-run process can be easily performed by those skilled in the art with the configuration of the present invention. In addition, according to the above, when the molar content of Ge is high at the temperature at which the Si _1-x Ge _x layer is formed, it may be a major factor that can cancel the warpage of the wafer, and thus the molar content of Ge and Si _1-x test depositing a _1-x Ge _x layer Si by varying the Si-forming temperature of _1-x Ge _x layer, while it is fixed to form the thickness of the Ge _x layer, the warpage degree of the wafer as possible to offset conducted repeatedly run Si It can also be quantified depending on the formation temperature of the _1-x Ge _x layer. In this case, it is obvious that the formation temperature of the Si _1-x Ge _x layer also becomes a control factor that can cancel the warpage of the wafer.

Meanwhile, the present invention is not only applicable to Si wafers, but can be applied to any wafer if the bow value of the wafer can be quantitatively controlled through deposition of a Si _1-x Ge _x layer. Accordingly, the technical idea of the present invention is that when depositing a Si _1-x Ge _x layer on a wafer, the molar content of Ge and the thickness of the Si _1-x Ge _x layer (additionally, formation of a Si _1-x Ge _x layer) It is to be understood that by controlling the temperature), the warpage of the wafer is to offset the warpage of the wafer such that the warpage of the wafer is zero based on the bow value.

Hereinafter, the configuration of the present invention will be described with reference to specific embodiments.

7 and 8 are cross-sectional views illustrating a method of controlling the degree of warpage of a wafer according to the first embodiment of the present invention.

Referring to FIG. 7, as the semiconductor device is integrated on the surface of the Si wafer W, the warpage of the wafer W is convex downward when the semiconductor device integration surface A is turned upward. In this case, as shown in FIG. 8, the Si _1-x Ge _x layer G is deposited on the back surface of the Si wafer W to offset the stress causing the warp of the wafer W. FIG. The molar content of Ge for this stress cancellation and the thickness of the Si _1-x Ge _x layer are specifically determined according to the bow value of the wafer W in which warpage is caused. Preferably, the mole content of Ge and the thickness of the Si _1-x Ge _x layer for compensating stress for each Bow value of the wafer W are calculated in advance through repeated experiments, and then referred to this. In the case of the first embodiment, the molar content of Ge can be adjusted in the range above 30% and the thickness of the Si _1-x Ge _x layer can be adjusted in the range above 1um. Optionally, when the molar content of Ge is large, the formation temperature of the Si _1-x Ge _x layer may be further considered as a control factor for canceling the warpage of the wafer. In this case, it is apparent that the quantification of the formation temperature of the Si _1-x Ge _x layer should be preceded by the degree of warpage of the wafer. Since this has already been described above, a detailed description thereof will be omitted.

On the other hand, in the case where the center of the wafer W is convex downward when the processing surface faces upward as in the first embodiment described above, Si epitaxially grown N type low concentration silicon epitaxial layer on the N type high concentration Si wafer. The same applies to tactile wafers and relaxed SiGe wafers grown with strained silicon layers thereon.

Also in this case, as in the first embodiment, the Si _1-x Ge _x layer G may be deposited on the back surface of the wafer W to offset the warpage of the wafer W. FIG. At this time, the molar content% of Ge and the thickness of the Si _1-x Ge _x layer (G) (additionally, the formation temperature of the Si _1-x Ge _x layer) are controlled in the same manner as in the first embodiment.

9 and 10 are cross-sectional views illustrating a method of controlling the degree of warpage of a wafer according to a second embodiment of the present invention.

Referring to FIG. 9, when the semiconductor device is integrated on the surface of the Si wafer W, the warpage of the wafer W is convex upward when the semiconductor device integration surface A is turned upward. In this case, as shown in FIG. 10, the Si _1-x Ge _x layer G is deposited on the back surface of the Si wafer W to offset the stress causing the warp of the wafer W. FIG. The molar content of Ge for this stress cancellation and the thickness of the Si _1-x Ge _x layer (G) are specifically determined according to the bow value of the wafer W in which warpage is caused. Preferably, the mole content of Ge and the thickness of the Si _1-x Ge _x layer for compensating stress for each Bow value of the wafer W are calculated in advance through repeated experiments, and then referred to this. For example, since the wafer W shown in FIG. 10 has a convex shape upward, the molar content of Ge may be controlled in the range of less than 30%, and the thickness of the Si _1-x Ge _x layer may be adjusted in the range of less than 1 μm.

On the other hand, in the case where the center of the wafer W is convex upward when the processing surface is facing upward as in the second embodiment described above, the Si epitaxial layer in which the P type low concentration silicon epitaxial layer is grown on the P type high concentration Si wafer. The Si wafer having a thermal oxide film formed thereon may also correspond to the wafer.

Also in this case, as in the second embodiment, the Si _1-x Ge _x layer G may be deposited on the back surface of the wafer W to offset the warpage of the wafer W. FIG. At this time, the molar content% of Ge and the thickness adjusting method of the Si _1-x Ge _x layer (G) are substantially the same as in the second embodiment.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be understood that various modifications and changes may be made without departing from the scope of the appended claims.

According to the present invention, the Si _{1 - x} Ge _x layer may be deposited on the back surface of the wafer where warpage has occurred to offset the warpage of the wafer. Si _{1 - x} Ge _x layer is relatively process simply because formed by a chemical vapor deposition method, a molar content% and Si _1-x Ge _x layer thickness of the Ge (Additionally, Si _1-x Ge _x layer forming temperature ), The degree of warpage caused by the Si _1-x Ge _x layer can be quantitatively controlled, so that the warpage of the wafer can be removed relatively simply, and the metal silicide layer is formed to offset the warpage of the wafer. Compared to the prior art, there is an advantage that no contaminants are caused.

Claims (11)

In the method of controlling the warpage of the wafer by depositing a Si _1-x Ge _x layer on the back of the wafer, (a) quantifying the percent Ge molar content of the Si _1-x Ge _x layer and the formation thickness of the Si _1-x Ge _x layer necessary to offset the warpage according to the degree of wafer warpage through repeated experiments; (b) loading the wafer in need of warpage control into a deposition chamber of a Si _1-x Ge _x layer; And (c) depositing a Si _1-x Ge _x layer on the back side of the wafer that is not a process surface, In accordance with the deflection amount of the wafer to be offset during the deposition of the Si _1-x Ge _x layer wafer, characterized in that the deposition of the Ge mole Amount% and Si _1-x Ge _x layer with a thickness quantified in step (a) How to control the warp. The method of claim 1, The wafer is a wafer in which the center of the wafer is bent upward when the processing surface of the wafer is facing upward, Deflection control method of the wafer, characterized in that adjusting the Si _1-x Ge _x layer Ge content mol%, and _1-x Ge _x layer thickness of Si of less than a predetermined threshold value. 3. The method of claim 2, A threshold value for said _1-x Ge _x layer Ge Si mol% and the content of _1-x Ge _x layer thickness of Si in the way of wafer deflection control, characterized in that respectively 30% and 1um. The method of claim 1, The wafer is a wafer in which the center of the wafer is warped downward when the processing surface of the wafer faces upward, Deflection control method of the wafer, characterized in that the Si-Ge _1-x Ge _x layers and Si molar content% Thickness of the _1-x Ge _x layer is greater than a predetermined threshold. 5. The method of claim 4, A threshold value for said _1-x Ge _x layer Ge Si mol% and the content of _1-x Ge _x layer thickness of Si in the way of wafer deflection control, characterized in that respectively 30% and 1um. 5. The method of claim 4, In step (a), Si _1-x and Ge _x layer to add more forming temperature as the controlling factor of, Ge molar content%, Si _1-x Ge _x layer is formed thick and the Si _1-x Ge _x layers of the Quantify the warpage of the wafer can be offset according to the formation temperature, The (c), reference to the quantified data from steps molar content% in Ge that corresponds to the bending degree of the wafer, Si _1-x Ge _x layer is formed thick and the Si process by the forming temperature of the _1-x Ge _x layer of Method of controlling the warp of the wafer, characterized in that to deposit a Si _1-x Ge _x layer by controlling. The method according to any one of claims 1 to 6, And the wafer is a Si wafer in which semiconductor elements are integrated on a processing surface of the wafer, a Si epitaxial wafer having an epitaxial layer formed on an upper surface thereof, or a relaxed SiGe wafer having a strained silicon film formed thereon. A semiconductor wafer having a first magnitude of stress induced in a first direction; And A Si _1-x Ge _x layer deposited on the back side of the wafer processing surface, And wherein the Si _1-x Ge _x layer is in a direction opposite to the first direction and applies a stress of the same magnitude to the back surface of the semiconductor wafer. 9. The method of claim 8, The magnitude of the stress caused by the Si _1-x Ge _x layer is controlled by the molar content of Ge and the thickness of the Si _1-x Ge _x layer. 9. The method of claim 8, The direction of the stress caused by the Si _1-x Ge _x layer is controlled by the molar content of Ge and the thickness of the Si _1-x Ge _x layer. 9. The method of claim 8, Wherein the wafer is a Si wafer in which semiconductor elements are integrated on a processing surface, a Si epitaxial wafer on which an epitaxial layer is grown on a processing surface, or a relaxed SiGe wafer on which a strained silicon film is deposited on the processing surface.

Images