JPS5834688A - Time axis compensation device - Google Patents

Abstract

PURPOSE:To sharply simplify a signal processing system at the writing side, and to reduce the cost of the titled device, by efficiently using signals, such as clock information, address information, etc., formed at the reading out side, as signals of the writing side. CONSTITUTION:A reference video signal REF.S added to a terminal 6 is supplied to a synchronizing separator circuit 35, and a horizontal synchronizing signal REF.H and a burst signal REF.B are taken out. The burst signal is added to a clock generator 7 at the reading out side, and a reference subcarrier REF. SC and a readout clock R.CK are formed. The reference horizontal synchronizing signal REF.H is supplied to a line judging pulse generator 38 installed to a sequence controller 5, and a line judging pulse R.OE which is inverted in phase at every horizontal line is formed. The reference subcarrier REF.SC and the line judging pulse R.OE are also supplied to the writing side, and a write clock W.CK and a writing side line judging pulse W.OE are obtained at the writing side based on them.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a modification of a time base correction device (hereinafter referred to as TBC).

FIG. 1 is a system diagram of the main parts of a conventionally known TBC, in which an 8-inch video signal that contains jitter components, such as a Niu video signal, or has a time axis that fluctuates, is passed through terminal (1) to A After being supplied to the -D converter (2) and digitally converted, the digital video signal is supplied to the memory device (3) and written with a clock W@CK synchronized with the time axis of the input video signal 8jn. Therefore, the input video signal Sin is further supplied to the clock pulse generator (4) of the writing device.
A synchronized clock weCK is formed in synchronization with the time axis of , and is supplied to the A-D converter (2), the memory device (3), and the sequence controller 2 (5).

On the other hand, a reference video signal REF-8 having a reference time axis such as an in-house video signal is supplied to the terminal (input). The clocks R, CK are supplied to the sequence controller 2 (5), the memory value 1t (3), the dropout compensator (8), and the D-A converter (9), and the reference clocks R, CK The used digital video signal is converted to analog conversion after dropout compensation processing.

A synchronizing signal etc. is inserted in the process processing circuit aυ to this video signal whose time axis has been corrected, that is, from which jitter components have been removed, and the terminal our is connected to the reference video signal RE.
A video signal 5out synchronized with F.8 is output.

In this way, THCQI continues to flow on the writing side (input side).
ill (reference axis 11iI) husband'kK10tsu/W*CK
.

A circuit thread is provided for obtaining R and CK.

FIG. 2 shows an example of the configuration of a part of the writing side noise generator (4) and sequence controller (5), in which the input video signal (in this example, the reproduced video signal) SJn is supplied to the synchronization separation circuit a$. input horizontal synchronizing signals PB, H
and the input burst signal PB@B are separated, and the input horizontal synchronizing signals PB and H are the AF that constitutes the tsuk generator (4).
After being supplied to the C circuit ae, the input burst signal PB・
B is also supplied to the KAPC circuit aD, and the input cover burst signal PB@]Jc synchronous shifter subcarrier (continuous wave) W.8
0 and writing by multiplying this sub-medium Yarya W.8C by 4 will form ivy W and CK.

Input horizontal synchronizing signals PB and H are further provided with sequence tone lows 9 (5) K provided line discrimination pulses W and OE.
generator 01) to form a line discrimination pulse W.OE whose phase is inverted for each horizontal line, and this twin discrimination pulse W.OE is written into the memory device (3) in units of one horizontal line. A digital video signal is associated.

Therefore, this twin discrimination pulse W・OIA is supplied as a phase inversion pulse to the phase inversion circuit (2) of subcarrier W・8C, and the subcarrier W・8C is
The phase of C is inverted.

This phase-controlled subcarrier W.8C is supplied to the generator (c) of the write zero pulse W@ZERO together with the human horizontal synchronizing signals FB and H. Write zero pulse W・ZE
iRO is a write start pulse that determines the initial phase of writing a signal to the memory device (3), and star F tie construction is controlled based on input horizontal synchronization signals FB, H.

The write zero pulse W, ZERO is further supplied to the generator (c) of the write address W/MUDD, and the write address W, ADD is formed based on the generation timing of the write zero pulse W/ZERO, which is then sent to the memory device (
3).

The above explanation is about the write side, but the circuit system on the read side, that is, the reference axis side, also has a readout circuit that is configured in the same way as shown in Figure 2 to drive the memory device (3), dorubu-out compensator (8), and cape. A clock R@CK generator (7) and a sequence controller (5) are provided independently from the write side.

By the way, VTRs for broadcast stations such as 1-inch VTRs have very stable servo systems, and because they are stationary types, the video signal played by this VTR has almost no jitter components. , because the time axis fluctuation is always output as a small video signal, when handling such a reproduced video signal as an 8-inch input video signal, it is necessary to There is no problem in using the output side signal formed from the reference video signal RFiF-8 as the Yotsuta information, address information.

With this configuration, the signal processing system on the write side can be greatly simplified.

Therefore, the present invention simplifies the signal processing system for the write example by making it possible to use the read-side signal as the write-side signal as much as possible. Next, an example of the present invention will be explained with reference to FIG.

This figure 3 shows the writing side and reading side connections W, CK,
It is a system diagram of the main parts of the R/CK and sequence controller (5), and for convenience of explanation, the signal processing system on the readout side, that is, on the reference axis side will be explained first.

The reference video signal RgF.8 is supplied from the terminal (6) to the synchronization separation circuit (c), where the horizontal synchronization signal RBF, H (Figure 4) and the burst signal RBF, B are separated, and the reference burst signal RNF, B is separated. is supplied to the read-out side Kutsk generator (subcarrier generator) to form continuous reference subcarriers RBF, 8C, and this reference subcarrier RBFe8C further multiplies its subcarrier frequency by 4. The signal is supplied to a circuit 0η to form readout circuits lFL, cK.

The reference horizontal synchronizing signals REF and H are supplied to the line discrimination pulse generator (c) provided in the digital controller (5), and are phase inverted with respect to the horizontal line, as explained in FIG. 2, just like the voice. A twin discrimination pulse OR (Fig. 4B) is formed, and this line discrimination pulse R and OE is further passed through a phase inversion circuit (
A subcarrier REF, SC is formed whose phase is inverted with respect to the one horizontal line.
is supplied with the reference horizontal synchronization signal RnF@H to the generator of readout pulses R, ZERO (40) to generate readout zero pulses R, ZF which determine the initial timing of readout.
An iRO (Figure 4C) is formed. This example is configured to be read out at the same timing as the line discrimination pulses R and OE.

The reference horizontal synchronization signal REF, H is further provided with the bladder release address R.
= Read address RΦA which is also supplied to the ADD generator Qυ and regulated by the reference horizontal synchronizing signal REF, H
DD is formed. This read address R・λDD and the above-mentioned read zero pulses R, ZERO1W, output signal I
vs TsukR-CKt! The read clocks R, CK are also supplied to the dropout compensator (8) and the D-large converter (9).

Next, we will discuss the signal processing system for write information. As mentioned above, the video signal Sin reproduced from a 5-inch VTR, which operates as stably as a 1-inch VTR, is input to terminal (1). do.

First, write ptsuk W and CK are reference subcarriers RE.
Formed based on F@8C. Therefore, the ripple clock generator (4) is provided with only a quadrupling circuit and an APC circuit,
No system PC circuit is provided.

The reason why the AFC circuit is omitted is that the write tally w@cx is based on the reference subcarrier RBF, 80, which has no time axis fluctuation.
This is because 4i is achieved. However, writing ■Tsuku W, C
The phase of K is controlled based on the phase of input burst signals PB·B. Therefore, this clock generator (4) is supplied with an input burst signal PB@B.

In addition, the output of the line discrimination pulse generator (to) provided on the continuous output side, that is, the line discrimination pulse R・OE, is supplied to the phase shift circuit (c) K and phase-shifted by a predetermined amount. Discrimination pulse W・oFS (4th
Figure F) is the subcarrier W/SC position.

A phase inversion pulse 1 is supplied to the phase inversion circuit.

That is, the line discrimination pulse R.OE on the read side is used as the line discrimination pulse W.OR8 on the write side.

This is also because the time axis of the 8-inch input video signal is very stable, and the line discrimination pulses R and O on the read side
By using K, it is possible to align the lines during writing and reading.

However, the phase inversion tying is based on the input video signal Sjn
Since it is necessary to match the phase of the horizontal twin, in this example, the timing is matched to the generation timing of the write zero pulse W, ZEILO (FIG. 4E), which will be described later. Therefore, the phase amount of the phase shift circuit (c) is controlled by the write zero (W@ZERO).

With this configuration, it is possible to omit the line discrimination I (Russ generator) on the writing side.

Next, the write address W/person DD is set to the read address R/
λDD is appropriated. In this case, write at v s W-
'ADDk1 write-h'a pulse W@ZEROIIC
Since synchronization is required, a phase shift circuit (47) is provided on the writing side, and the read addresses R and DD are shifted as shown in FIG. The example in FIG. 4 shows an example of addresses when the memory device (3) is configured using three IH memories. Note that the advance amount is 1.5H.

As explained above, according to the present invention, very stable playback video signals etc. can be handled.
Since the signals formed on the reading side (such as link information, address information, etc.) are utilized as much as possible and used as signals on the writing side, according to this embodiment, the PC
The circuit, line discrimination signal generator and write address forming circuit can be omitted and shut down.

Note that in the case of a video signal reproduced at high speed as the input video signal 81, the input horizontal synchronization coefficient PB.
While the frequency of the reference video signal RE?
, because it is clocked at a constant frequency based on 8,
The playback screen based on the output video signal 8 out may expand or contract depending on the input frequency, but since it is a playback screen in high-speed driving mode, this is not a particular problem.

[Brief explanation of the drawing]

Fig. 1 is a system diagram of the time axis correction device, Fig. 2 is a system diagram of the main parts on the writing side, Fig. 3 is a system diagram of the main parts showing an example of this invention, and Fig. 4 is an explanation of its operation. FIG. Q(H-!T B C, (2) i! A-D converter, (3
) is a memory device, (4) is a clock generator on the writing side, (5) is a sequence controller, (7) is a read-out clock generator, (9) is a D-A converter, and (9) is a D-A converter. )
, @η is the same phase shift time Hidefune Matsukuma

Claims (1)

[Claims] A Mu-D converter that digitally converts the input video signal, a memory device that writes this digital video signal, a D-human wave converter that converts the digital video signal to analog, a sequence controller, and a sequence controller that converts the input video signal into an analog signal. and a pulse generator for forming a clock, etc., and the address information formed by the pulse generator and the sequence controller is used to write the input video signal to the memory device. A time axis correction device characterized in that it is also used as clock information and address information on the storage side.