JPS5853551B2 - Kijiyun Shingo Keisei Cairo - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is applied to a time axis error correction device that corrects the time axis error of an information signal (synthesized information signal) having a time axis error, such as a reproduction signal of a magnetic recording and reproducing device. The present invention relates to a reference signal forming circuit suitable for use as a reference signal forming circuit.

A composite information signal (for example, a composite color video signal) having a different time axis error than conventional information signals and synchronization signals is supplied to a sampling circuit and sampled using a write clock pulse corresponding to the time axis error of this composite information signal. , this sampled composite information signal is sequentially switched and supplied to each storage unit of a storage device consisting of a plurality of storage units, and is written and stored using a write clock pulse, so that the signal is stored in the storage unit of this storage device. A time axis error correction device has been proposed in which a synthesized information signal whose time axis error is corrected is obtained by sequentially reading out the stored contents using a reading clock pulse.

By the way, when the composite information signal is a composite color video signal, the write clock pulse according to the above-mentioned time axis error can be generated by using a burst signal (color synchronization signal) and also using a horizontal synchronization signal. can be made.

Further, the storage device is composed of a plurality of storage units as described above, and the composite color video signal is sequentially stored in the secondary storage unit line by line, that is, 1, 2, 3, . . .
Since it is written and stored line by line, a pulse with a predetermined phase relationship with the horizontal synchronizing signal, for example, the same phase, is extracted from the write clock pulse, used as a reference pulse (zero address signal), and synthesized based on this reference pulse. It is necessary to regulate the starting point of writing, storing and reading color video signals to a storage device.

Now, since the composite color video signal has a time axis error, the horizontal synchronization signal, burst signal, and write clock pulse naturally also have time axis errors, but for this reason, the phase between these signals constantly changes, Regardless of this phase change, it becomes difficult to accurately form a reference pulse.

That is, the signal reading start timing from the storage unit is always constant because it is generated from a synchronization signal and a burst signal that do not include jitter.

Therefore, if the signal write start timing to the storage unit is not constant during writing and sometimes deviates by one clock, the image of the corresponding scanning line on the playback screen will be 1 clock for the line whose start pulse is shifted by 1 clock as a result.
It shifts sideways by the amount of the clock.

In view of this, the present invention is based on a first synchronization signal of frequency f1 and a second synchronization signal of frequency f2 (where f2=αf0.α>■) in a composite information signal having a time axis error. frequency f3 (however, f3=Nf2, but N=1.2
,3. In a reference signal forming circuit that extracts a signal portion having a predetermined phase relationship with the first synchronization signal from the clock signal of . The purpose is to propose something that can be formed accurately regardless of axis errors.

The present invention provides the frequency f in the composite information signal with time error.
1 first synchronization signal and frequency f2 (however, f2αf1.α
〉Frequency f3 created based on the second synchronization signal of 1)
(However, f3=Nf2.N-1, 2゜3,...)
A reference signal forming circuit for forming a reference signal by extracting a clock signal portion having a fixed phase relationship with respect to the first synchronization signal from a clock signal train of the first synchronization signal; a phase difference determining circuit that supplies the output of the variable delay circuit and a rectangular wave signal synchronized with a clock signal, determines the phase difference therebetween, and controls the delay amount of the variable delay circuit using the determined output. The delay amount of the variable delay circuit is periodically fixed according to the phase difference of the delayed first synchronization signal output from the variable delay circuit with respect to a specific wave of a rectangular wave signal synchronized with the clock signal. A reference signal is formed by extracting a clock signal portion having a fixed phase relationship with respect to the delayed first synchronization signal.

First, an example of a time axis error correction device to which the present invention can be applied will be described below with reference to FIG.

In this example, a reproduction signal reproduced by a rotating magnetic head device of a magnetic recording/reproducing device having a rotating magnetic head device, that is, a modulated composite color video signal, is demodulated to obtain an original composite color video signal, and the composite color video signal is demodulated to obtain the original composite color video signal. This is a case where the time axis error of the signal is corrected.

A magnetic tape T is guided and run on a tape guide drum of a rotating magnetic head device diagonally, for example, so that when it is wound approximately 180°, it is wound at an angle.

1 is a pair of rotating magnetic heads (shown as one magnetic head in the figure) arranged at an angle of 180°;
In this case, it is operating as a playback head.

The reproduced signal from the magnetic head H is supplied to a high frequency amplifier 2 and amplified, and then supplied to a demodulator 3 where it is demodulated, and a composite color video signal is obtained on its output side.

In this example, the reproduced signal reproduced by the magnetic head is a mixed output of a frequency-modulated luminance signal and a low-frequency-converted carrier chrominance signal. Frequency demodulation of the frequency modulated luminance signal and reconversion of the low frequency converted carrier color signal to the original carrier color signal,
Both secondary signals are mixed to obtain an original composite color video signal having a frequency interleaved relationship.

This obtained composite color video signal is sent to the buffer amplifier 4.
The signal is supplied to a sample and hold circuit 5 through which it is sampled and held, and its output is supplied to a buffer amplifier 6.

DC feedback is applied from the amplifier 6 to the amplifier 4, so that a sampled composite color video signal reproduced by the DC current can be obtained from the amplifier 6.

The output of the amplifier 6 is then supplied to the main memory 8 through the AD converter 7 and written therein.

The sample-and-hold circuit 5 is supplied with a write clock pulse as a sampling pulse, which varies in accordance with the time axis variation of the composite color video signal obtained from the demodulator 3 to be supplied to the storage device 8 .

15 is a circuit that generates this write clock pulse, and the frequency of this clock pulse is a horizontal frequency of 15.75kHz.
It is selected to be an odd multiple of approximately 7 of the horizontal frequency so as to have a frequency interleaving relationship with z.

Furthermore, since the time axis error of the composite color video signal is detected as the time axis error of its burst signal, the frequency of this clock pulse is equal to the color subcarrier frequency of 3.58 MHz.
selected as an integer multiple of

Therefore, in this example, the frequency of this write clock pulse is set to 10.74 MHz (-3,
58MHz x 3: 15-75kHz x 2
X 1365).

The composite color video signal from the amplifier 4 is supplied to a burst separation circuit 13 and a synchronization separation circuit 14 to separate the burst signal and horizontal and vertical synchronization signals, respectively, and these signals are supplied to a write clock pulse generation circuit 15. , where a write clock pulse as described above is generated based on these signals.

The phase of the write clock pulse is corrected so that the pulse of the higher frequency matches the phase of the beginning of each burst signal obtained every horizontal period, and the phase of the pulse is corrected so that the pulse of the above frequency matches the phase of the beginning part of each burst signal obtained every horizontal period, and until the next burst signal arrives. The interval is the frequency 1 mentioned above.
The pulse is maintained at 0.74 MHz.

This write clock pulse is then supplied to the sample and hold circuit 5, the A-D converter 7, and the main memory device 8.

The above-mentioned A/D converter 7 is a circuit that converts the sampled composite color video signal output from the amplifier 6 into, for example, an 8-bit binary encoded signal.

The main memory device 8 consists of a plurality of sets (preferably three or more sets) of memory units 26 to 29, four sets in this example, and the output from the A-D converter 7 is switched and supplied to the secondary memory units 26 to 29. The memory contents are written and stored using the above-mentioned write clock pulse, and the stored contents are read using a read clock pulse that has the same frequency as the write clock pulse and is created taking into account the time axis variation. It is done like this.

Each of the storage units 26 to 29 stores the 8-bit binary encoded sampled composite color video signal in units of lines, except for part (or all) of the horizontal blanking section.

That is, as shown in FIG. 2, for example, in the horizontal blanking interval BHh of the composite color video signal, the horizontal synchronizing signal sh is at one point ((,/, t1') to one point t2 (t2', t2') on the back porch. The (IH-"α) time of the section excluding the α time (for example, 4 μs) between the lines 1 and 2) is stored in each storage unit 26 to 29 in units of lines.

In FIG. 2, Se represents a video signal and Sb represents a burst signal.

Each of the storage units 26 to 29 can be a digital memory such as a shift register, a random access memory, or an analog memory such as a capacitor memory, CCD, or BBD (in this case, the AD converter 7 is not required).

FIG. 3 shows the writing and reading states for each of the storage units 26 to 29, and each time interval I.

■、・・・・・・、■ Write WR sequentially as shown in the figure.
and read RD are performed, and each storage unit 26 to 29
The portion IH to α of one line of the composite color video signal sampled for one set is written and stored.

For example, when writing is being performed on the storage unit 26, every other storage unit in each of the storage units 26 to 29 is cyclically placed in the writing state, with one being in the writing state at the same time, so that reading is performed from the storage unit 28 at the same time. The other one is in a read state.

In this main storage device 8, if there is a dropout in the reproduced signal from the rotary magnetic head 1 for each line, the sampled composite color video signal of that line, which has been written and stored in a certain storage unit, is transferred to another line. This is replaced with a sampled composite color video signal, which will be discussed later.

When writing and storing the IH portion of one line of the sampled composite color video signal in each of the storage units 26 to 29, at the above-mentioned write clock pulse frequency of 10 and 74 MHz,
It is necessary to store 682.5 addresses (actually 682 addresses on one line and 683 addresses on the next line), but in this example, IH-α (α-4 μs) of one line is written and stored. Therefore, each storage unit 26 to 29
It is sufficient to write and store data for address 40, and the writing is stopped during time α.

18 supplies write clock pulses and read clock pulses to the main memory device 8, and each memory unit 26 to 2.
This is a control circuit for controlling the selection for writing and reading of 9 and the replacement of written contents when there is a dropout.

The output of the control circuit 18 is supplied to the drive circuit 17, whereby the main memory device 8 is controlled as described above.

16 supplies each output of the write clock pulse generation circuit 15 and the synchronization separation circuit 14, extracts one of the write clock pulses having a specific phase relationship with the composite color video signal, and uses this as the write start pulse. This is a pulse extraction circuit that supplies the control circuit 18.

Reference numeral 20 denotes a read clock pulse generation circuit, which is controlled by a synchronization signal generation circuit (another reference synchronization signal generation circuit), and determines horizontal and vertical synchronization signals, local subcarrier signals, and the read start point in the main storage device 8. A local subcarrier signal is supplied from the circuit (circuit that generates a read start pulse, etc.) 21, and a velocity error signal (a velocity error memory described later) is supplied based on the time axis error detected by the burst signal of the composite color video signal. Device 2
4) to generate a 10.74 MHz read clock pulse.

23 is a velocity error hold circuit that holds the velocity error signal detected for each IH from the write clock pulse generation circuit 15 for IH-α time of one line; the output of this circuit 23 and the output from the control circuit 18 is provided to velocity-error storage 24.

The velocity-error storage device 24 has four sets of analog storage units (for example, capacitor memories) corresponding to each other according to the number of storage units in the main storage device 8, and stores the storage units 26 to 29 corresponding thereto. Velocity errors in the content are stored and the stored output is provided to the read clock pulse generation circuit 20 as described above.

When a certain storage unit of the main storage device 8 is being read, this storage device 24 corresponding to that storage unit
10.74 in response to the error signal, and supplies the velocity-error signal to the read clock pulse generation circuit 20.
The MHz clock signal is phase modulated to create a read clock pulse, which is then supplied to the control circuit 18.

In this case, the window (time axis variation correction range) in the l line becomes 1H+α, as can be seen from FIG.

Reference numeral 12 denotes a dropout detection device that detects whether or not there is a dropout in the reproduced signal from the rotating magnetic head 1 for each line of the composite color video signal and outputs it as a digital signal.

19 is a dropout storage device, which is the main storage device 8.
There are four sets of storage units corresponding to each set of storage units, and it is checked whether or not there is a dropout in the storage contents of each storage unit of the main storage device 8 in the second storage unit. The detection output of the dropout detection circuit 12 and the control output of the control circuit 18 described above are supplied to this, and the output of this storage device 19 is supplied to the control circuit 18.
It is designed to be supplied to

Then, in the control circuit 18, if there is a dropout in the sampled composite color video signal of a certain line written in the storage unit of the main storage device 8, the dropout in the other storage unit is detected prior to reading. The sampled and synthesized color video signal of another line with similar signal content is replaced with the sampled and synthesized color video signal without any dropout, and at the time of readout, the signal without dropout can be read out from each storage unit of the main storage device 8. There is.

Now, the read output of the main memory device 8 is the buffer memory device 9.
supplied to

This buffer storage device 9 is for controlling the timing of supplying data to the DA converter 10, and consists of an 8-bit 1-address memory.

The output from this buffer storage device 9 is sent to a D-A converter 10.
and is converted into a sampled analog signal.

Incidentally, both the buffer storage device 9 and the D-A converter 10 are controlled by a read clock pulse from a read clock pulse generation circuit 20.

Then, by supplying the output of the D-A converter 10 to the processor 11, the signal missing part that was not written and stored in the main storage device 8 for each line of the composite color video signal is transferred to the synchronization signal generation circuit 21. This is supplemented by horizontal and vertical synchronization signals and burst signals.

In this way, a composite color video signal with time axis errors corrected is obtained at the output terminal 22.

Now, the reference signal forming circuit according to the present invention is applied to the above-mentioned pulse extraction circuit 16, and one embodiment thereof will be described below in f. First, referring to FIG. A specific example will be explained, and then a specific example of the pulse extraction circuit 16 to which the present invention is applied will be explained with reference to FIG.

In FIG. 4, 31 is an input terminal to which the horizontal synchronization signal obtained from the synchronization separation circuit 14 of FIG. 1 is supplied, and 32
is an input terminal to which the burst signal obtained from the burst separation circuit 13 of FIG. 1 is supplied.

And as a write clock pulse, the frequency is Nf2(
However, N=1, 2, 3. ...and in this example, N-
3) using the frequency signal As1n (ωt+φ) (where A is a constant, ω is the angular frequency, and φ is the phase), the ω and φ of the composite color video signal having a time axis error are calculated according to the time axis error. is made variable.

33 is an output terminal from which this write clock pulse is obtained.

Time axis errors in the composite color video signal reproduced from the magnetic tape are caused by changes in the apparent water wave frequency due to expansion and contraction of the magnetic tape, deformation of the tape guide drum, uneven running speed of the magnetic tape (wow, flutter), etc. There are two types, one in which the time axis error fluctuates relatively slowly due to vibration of the magnetic tape, and the other in which the time axis error fluctuates relatively quickly due to vibrations of the magnetic tape (the amount of phase fluctuation is proportional to the reciprocal of the jitter frequency). Therefore, in the former case, ω is controlled using an APC circuit (automatic frequency control circuit) 34, and in the latter case, φ is controlled using an APC circuit (automatic phase control circuit) 35.

First, the AFC circuit 34 will be explained.

36 has an oscillation frequency of Nf2 (-3X 3.58MH2=
10.74MHz) variable oscillator.

3T is a first frequency divider (counter) with a frequency division ratio of -3×456/2 to which a part of the oscillation output of the variable oscillator 36 is supplied.

38 is the frequency division output of this first frequency divider 37, that is, the frequency f
1 signal and a horizontal synchronization signal, which is the first synchronization signal supplied to the input terminal 31, whose phase is shifted (delayed) through the delay circuit 39 as necessary, and the phases are compared. This is a first phase comparator that controls the oscillation frequency of the variable oscillator 36 at its output.

Furthermore, in this example, when the rising position of the horizontal synchronizing signal from the input terminal 31 deviates significantly, the counter 31, which is the first frequency divider, is reset to cancel AFC. Comparators 40 and 41 respectively supply the horizontal synchronization signal from the input terminal 31 and compare it with predetermined upper and lower limit counter numbers, and a window signal generation circuit that generates an output signal when the horizontal synchronization signal deviates from the range. 42, a monostable multivibrator 43 which generates a pulse signal by triggering with the horizontal synchronization signal, and when an output signal is generated from the wind signal generation circuit 42, the pulse signal from the monostable multivibrator 43 is used as a reset signal. An AFC release circuit 45 is provided which includes a gate circuit 44 that supplies signals to the first frequency divider 37 and resets it.

Next, the APC circuit 35 will be explained.

47 is a variable phase shifter to which a part of the oscillation output of the variable oscillator 36 is supplied.

Reference numeral 48 denotes a second divider with a frequency division ratio (=, ) to which one part of the output of the variable phase shifter 4T is supplied.

Reference numeral 49 denotes a second frequency divider 48 which supplies the divided output of the second frequency divider 48 and a second synchronizing signal, that is, a burst signal, compares the phases, and controls the phase shift amount of the variable phase shifter 47 using the comparison output. This is a phase comparator.

A write clock pulse that follows the time axis error of the composite information signal, that is, the composite color video signal, is obtained from the variable phase shifter 4T at the output terminal 33.

Then, a color subcarrier signal having a time axis error is obtained from the second frequency divider 48 at the output terminal 51.

In this example, the output of the second phase comparator 49 is further obtained as a velocity-error signal at the output terminal 52, and this is applied to the first
The signal is supplied to the velocity-error hold circuit 23 shown in the figure.

The write clock pulse obtained from this output terminal 33 sufficiently follows the time axis error of the composite color video signal as the composite information signal.

Next, the pulse extraction circuit shown in FIG. 5 will be explained.

54 is an input terminal to which the horizontal synchronizing signal obtained from the synchronization separation circuit 14 of FIG.
6 is an input terminal to which the color subcarrier signal obtained from the fourth output terminal 51 is supplied, and 57 is an input terminal to which the write clock pulse obtained from the output terminal 33 of FIG. 4 is supplied.

Reference numeral 62 denotes a variable delay circuit to which a horizontal synchronizing signal is supplied, which includes two stages of variable delay circuits M1. M2, each consisting of a monostable multi-by-break.

The delay circuit M1 has a delay amount of 1 μs and IμS+ for each horizontal period according to the control signal supplied to the input terminal 55.
140 nS and a delay amount difference of 140 nS.

Since the phase of the burst signal is inverted every horizontal period, this delay circuit M1 is connected to the horizontal synchronizing signal and the burst signal (
This is provided in order to equalize the phase difference with the color subcarrier signal in each horizontal period, and the half period of the burst signal is approximately 140 nS.

Further, the delay circuit M2 has a delay amount of 7 μs and 7 μS−)−70 according to the determination output of the phase difference determination circuit 60, which will be described later.
nS and a delay amount difference of 70 nS.

This 70 nS approximately corresponds to the period of the burst signal.

The fixed delay amount of the entire variable delay circuit 62 is 8 μs, which approximately corresponds to the time width from the leading edge of the horizontal synchronizing signal to the final portion of the burst signal.

A phase difference determination unit 60 supplies the output of the variable delay circuit 62 and the color subcarrier signal supplied to the input terminal 56, determines the phase difference therebetween, and controls the delay amount of the variable delay circuit 62 using the determined output. It is a circuit.

This phase difference discrimination circuit 60 includes JK flip-flop circuits F1. F2, NAND circuit N1. N2. N3. N4
It consists of

The output of the delay circuit M2 is supplied to the flip-flop circuits F7 and F2, and the color subcarrier signal supplied to the input terminal 56 is supplied to the exclusive-OR circuits ER□ and ER2, so that color subcarrier signals having mutually opposite phases are supplied. The flip-flop circuits F1. It is supplied to F2 as a clock signal.

Note that +B is a power supply. Moreover, the flip-flop circuit F1
．． Each output of F2 and each output of delay circuit M2 are connected to NAND circuit N1. N2 through NAND circuit N2. N4, and the output of the NAND circuit N4 is supplied as a phase discrimination output to the delay circuit M2.

The flip-flop circuit F1 also serves as a synchronization circuit 63 that synchronizes the delayed horizontal synchronization signal output from the variable delay circuit 62 with the color subcarrier signal supplied to the input terminal 56.

59 is a synchronization circuit (extraction circuit) that further synchronizes the output signal of the synchronization circuit 63 with the write clock pulse and extracts one frequency thereof; JK flip-flop circuit F3. It is composed of F4 and a NAND circuit N5.

The output of the flip-flop circuit F is the flip-flop circuit F3-
It is supplied to the NAND circuit N5 through the flip-flop circuit F4, and the output of the flip-flop circuit F3 is supplied directly to the NAND circuit N.

Then, the write clock signal supplied to the input terminal 57 passes through the exclusive OR circuit ER3 to the flip-flop circuit F3. F, as a clock signal.

An output terminal 58 from which a reference signal (zero address signal) is obtained is led out from the NAND circuit N5.

Next, the operation of the circuit shown in FIG. 5 will be explained with reference to the waveform diagrams shown in FIGS. 6 to 8.

In Figures 6 and 7, SI in A is the input terminal 5.
82 in the same figure B shows the waveform of the output Q of the delay circuit M2, and 82 in the same figure C shows the waveform of the color subcarrier signal supplied to
3 shows the waveform of the output Q of the flip-flop circuit F1,
84 in the same figure shows the waveform of the output Q of the flip-flop circuit F2, waveform S in the same figure E shows the waveform of the output of the NAND circuit N1, and S6 in the same figure F shows the waveform of the output of the NAND circuit N3. , S7 in G of the figure shows the waveform of the output of the NAND circuit N4.

Now, the phase difference determining circuit 60 determines the phase difference between the delayed horizontal synchronizing signal S2, which is the output of the variable delay circuit 62, and the color subcarrier signal supplied to the input terminal 56, and determines the amount of delay of the delay circuit M2. The falling point of the horizontal synchronizing signal S2 is within the first half cycle FP of one frequency of the color subcarrier signal as shown in FIG. 6, or within the second half cycle RP as shown in FIG. In the former case, the sixth
The delay amount of the delay circuit M2 is set to 7 by the control signal S7 in Figure G.
In the latter case, the delay amount of the delay circuit M2 is changed to 7μ by the control signal S7 in FIG. 7G.
It is made variable to s.

81 in FIG. 8A is an enlarged view of the waveform S1 in FIGS. 6A and 7A, and the waveform S2 in FIGS. 8B and 8C.
a and waveform S2b show the waveform S2 in FIGS. 6B and T, respectively.

Furthermore, 83 in FIG. 8 shows the same waveform of the output Q of the flip-flop circuit F1 as 83 in FIGS. 6C and 7C, and 88 in FIG. 8E shows the waveform of the write clock pulse supplied to the input terminal 57. The waveform is shown, and S in FIG. 8F is the output terminal 58.
The waveform of the reference signal (zero address signal) obtained is shown below.

Now, when the rising edge of the output of the variable delay circuit 62 is within the latter half cycle RP of one frequency of the color subcarrier signal, as shown at 82b in FIG. 8C, the amount of delay of the delay circuit M2 is 7 μs, and when the falling time is within the first half cycle FP as shown by the dotted line, as shown at 82a in Figure B, the delay amount is 7 μs + 70 nS. (-70nS).

That is, in a steady state, the delay amount of the delay circuit M2 is periodically varied every two horizontal scanning periods.

Therefore, no matter where the falling point of the output of the variable delay circuit 62 is within one frequency of the color subcarrier signal S1, it is always synchronized with the predetermined time tn in A of the same figure, as shown in the figure, and one frequency before that. There is no synchronization with time 1n.

That is, in the case of S2a shown by the dotted line in FIG. 8A, if there is jitter, it is likely to be synchronized to time point 'n-1 of 81 in FIG. 8A, but that time point is moved closer to time point tn by γ. Therefore, this risk is avoided.

This delay amount difference γ is selected to be smaller than one period of the signal related to the write clock pulse, that is, the color subcarrier signal in this example, but it is practical to select it to be smaller than one period of the color subcarrier signal in the above example.

A predetermined phase portion of the horizontal synchronization signal, that is, in this example, a time point in one cycle of the signal related to the write clock pulse at the rising edge time is divided into three or more portions, and the variable delay circuit 62 is delayed accordingly. The amount may be changed by a predetermined delay difference, and in that case, the delay amount difference can be set to an appropriate value accordingly.

Further, the signal related to the clock signal may be the clock signal itself, or may be a signal obtained by appropriately dividing the clock signal.

According to the present invention described above, it is possible to obtain a reference signal forming circuit that can obtain an accurate reference signal regardless of the time axis error of the composite information signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a time axis error correction device to which the present invention can be applied, FIG. 2 is a waveform diagram for explaining it, FIG. 3 is an explanatory diagram for explaining it, and FIG. 4 is a diagram for explaining it. 1 is a block diagram showing a specific example of a part of FIG. 1, FIG. 5 is a block diagram showing an embodiment of the present invention, and FIGS. 6, 7, and 8 are waveforms for explaining the present invention, respectively. It is a diagram. 60 is a phase difference discrimination circuit, and 62 is a variable delay circuit.

Claims (1)

[Claims] 1 The first synchronization signal of frequency f1 in the composite information signal having a time error and the frequency f2 (where f2=αf1゜α〉1
) frequency f3 (however, f3=N f2.N= 1.2, 3...)
A reference signal forming circuit for forming a reference signal by extracting a clock signal portion having a fixed phase relationship with respect to the first synchronization signal from a clock signal train of A variable delay circuit, and a device that supplies an output of the variable delay circuit and a rectangular wave signal synchronized with the clock signal, determines the phase difference therebetween, and controls the amount of delay of the variable delay circuit using the determined output. a phase difference determination circuit, the variable delay circuit detects a phase difference of the delayed first synchronization signal output from the variable delay circuit with respect to a specific wave of the rectangular wave signal synchronized with the clock signal. The delay amount is periodically varied by a certain amount, and a reference signal is formed by extracting a clock signal portion having a fixed phase relationship with respect to the delayed first synchronization signal. Reference signal forming circuit.