JPS5831429Y2 - Watch board - Google Patents

Watch board

Info

Publication number
JPS5831429Y2
JPS5831429Y2 JP7542878U JP7542878U JPS5831429Y2 JP S5831429 Y2 JPS5831429 Y2 JP S5831429Y2 JP 7542878 U JP7542878 U JP 7542878U JP 7542878 U JP7542878 U JP 7542878U JP S5831429 Y2 JPS5831429 Y2 JP S5831429Y2
Authority
JP
Japan
Prior art keywords
substrate
board
substrates
circuit pattern
scraps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP7542878U
Other languages
Japanese (ja)
Other versions
JPS54177973U (en
Inventor
敏正 池上
Original Assignee
セイコーエプソン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by セイコーエプソン株式会社 filed Critical セイコーエプソン株式会社
Priority to JP7542878U priority Critical patent/JPS5831429Y2/en
Publication of JPS54177973U publication Critical patent/JPS54177973U/ja
Application granted granted Critical
Publication of JPS5831429Y2 publication Critical patent/JPS5831429Y2/en
Expired legal-status Critical Current

Links

Description

【考案の詳細な説明】 本考案は時計用基板に関するものであり、その2次加工
を廃止することを目的とするものである。
[Detailed Description of the Invention] The present invention relates to a watch substrate, and its purpose is to eliminate secondary processing thereof.

従来の時計用基板、特に回路基板において、フライスに
よる切削加工を行なった場合には次の様な問題があった
When conventional watch substrates, particularly circuit boards, are cut using a milling cutter, the following problems arise.

(1)鋭角で形成された平面形状の加工はできない。(1) Planar shapes formed at acute angles cannot be processed.

(2)断面的に段差ができる。(3)ケバ等が発生する
(2) A step is created in the cross section. (3) Fluff, etc. occurs.

(4)回路パターンを形成している部分を加工すると回
路パターンがはげる。
(4) If the part forming the circuit pattern is processed, the circuit pattern will peel off.

(5)加工工数がかかる。(5) Processing time is required.

(6)複雑な平面形状の加工が困難である。(6) It is difficult to process complicated planar shapes.

本考案は上記問題を解消するものであり、以下本考案の
実施例を示す平面図に従い詳述する。
The present invention solves the above problems, and will be described in detail below with reference to plan views showing embodiments of the present invention.

第1図は、本考案の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.

1及び2は、夫々−面側にエツチング等により形成され
た回路パターン1a、2aを有している第1及び第2基
板(側基板の板厚はほは゛同じ)である。
Reference numerals 1 and 2 denote first and second substrates (the thickness of the side substrates are almost the same) having circuit patterns 1a and 2a formed by etching or the like on the negative side, respectively.

第1基板1と第2基板2は、回路パターン1a、2aを
形成していない面を接着剤等によって1枚板の如く粘り
つけてあり、両面に回路パターン1a、2aを有した両
面基板を形成している。
The first substrate 1 and the second substrate 2 are glued together like a single board with an adhesive or the like on the surfaces on which the circuit patterns 1a and 2a are not formed, and are double-sided substrates having the circuit patterns 1a and 2a on both sides. is forming.

この両面基板にICチップ等の部材を支持、案内、或い
は他部材と両面基板との隙間を確保するために、凹部1
Cを形成する場合、両面基板を打抜き加工(半抜き加工
において、抜き落し部とそれ以外の部分が分離している
加工も含む)する。
In order to support and guide members such as IC chips on this double-sided board, or to secure a gap between other parts and the double-sided board, a recess 1 is provided.
When forming C, a double-sided substrate is punched (including half-blanking, in which the punched-out portion and other parts are separated).

そして、第1基板の打抜き部分1b(以下抜きかすと呼
ぶ)を第2基板2に押込み、第2基板2の一部を抜きか
す1bによって構成した(但し、抜きかす1bに対向す
る第2基板2の抜きかすは抜きかす1bと分離され、両
面基板の構成部分とはならない)ためにフライスによる
切削加工は不要になる。
Then, the punched portion 1b of the first substrate (hereinafter referred to as the punching scrap) was pushed into the second substrate 2, and a part of the second substrate 2 was formed by the punching scrap 1b (however, the second substrate opposite to the punching scrap 1b The punched scraps 2 are separated from the punched scraps 1b and do not become a constituent part of the double-sided substrate), so cutting with a milling cutter is not necessary.

又、打抜き加工によることから平面形状もその用途に応
じて設定でき、更に凹部1Cの深さも抜きかす1bが第
2基板2から外れない程度、に任意に選択できる。
In addition, since punching is used, the planar shape can be set according to the intended use, and the depth of the recess 1C can be arbitrarily selected to such an extent that the punching stubs 1b do not come off the second substrate 2.

次に、この両面基板を応用した回路実装方法を示す第2
図の説明をする。
Next, the second section shows a circuit mounting method using this double-sided board.
Explain the diagram.

1b及び2bは夫々第1、第2基板1,2の抜きかすで
、第1基板1の一部は抜きかす2bで、第2基板2の一
部は抜きかす1bで構成されている(これらの抜きかす
は多少力を加えても両面基板からは外れない)。
1b and 2b are the scraps of the first and second substrates 1 and 2, respectively, a part of the first substrate 1 is the scraps 2b, and a part of the second board 2 is the scraps 1b. The scraps will not come off from the double-sided board even if you apply some force).

この第1、第2基板1,2は一面側にエツチング等によ
り形成された回路パターンla、2aを有し、回路パタ
ーン1a、2aがない面を接着固定し両面基板を形成し
ている。
The first and second substrates 1 and 2 have circuit patterns la and 2a formed by etching or the like on one side, and the surfaces without the circuit patterns 1a and 2a are fixed with adhesive to form a double-sided substrate.

第1基板の凹部1CにはICチップ3を挿入してあり、
その四部1Cの平面形状はICチップ3を取付ける際に
その平面位置を案内可能に設定しである。
An IC chip 3 is inserted into the recess 1C of the first board,
The planar shape of the four parts 1C is set so that the planar position of the IC chip 3 can be guided when the IC chip 3 is attached.

4は回路パターン1aとICチップ3とを接続するため
の金線である。
4 is a gold wire for connecting the circuit pattern 1a and the IC chip 3.

そして、これらを図示の如く樹脂5によって封止してい
る。
These are then sealed with resin 5 as shown.

又、第2.基板?(り形1威した甲部2 CIには、端
子6a、6bを有したコンテ゛ンサ或いは抵抗等の素子
6を挿入し、端子6a、6bと回路パターン2aとを半
田等によって導通固着しである。
Also, second. substrate? (An element 6 such as a capacitor or a resistor having terminals 6a and 6b is inserted into the upper part 2CI having the shape 1, and the terminals 6a and 6b and the circuit pattern 2a are fixed and conductive by soldering or the like.

この四部2Cの深さは、素子6の厚みにあわせて設定す
ることもでき、その平面形状においても打抜き加工であ
ることから、その用途に応じて任意の形状にすることか
で゛き、る。
The depth of these four parts 2C can be set according to the thickness of the element 6, and since its planar shape is also punched, it can be made into any shape depending on its use. .

7はピンで゛あ、す・、回路パターン1aと回路パター
ン2aとの導通をとるとともに、両基板の固着をより確
実にしている。
Reference numeral 7 denotes a pin, which not only establishes conduction between the circuit pattern 1a and the circuit pattern 2a, but also secures the fixation of both substrates.

更に第3図に示すように、最近用いられ始めた回路実装
方法と:して、予め第1基板、1の凹部1Cを形成して
から、金属箔より戒る回路パターン1aを形成し、その
一端にバンプを有するICデツプ3を配し・、回路パタ
ーン1aとICチップのバンプ3aとを直接接合し、そ
の回路パターンを第1基板1に固着させて、その周囲を
樹脂5によって封止する方法にも応用でき、回路作りが
簡単になる。
Furthermore, as shown in FIG. 3, there is a circuit mounting method that has recently started to be used: first, a recess 1C of the first substrate 1 is formed in advance, and then a circuit pattern 1a is formed using metal foil. An IC chip 3 having a bump at one end is disposed, the circuit pattern 1a and the bump 3a of the IC chip are directly bonded, the circuit pattern is fixed to the first substrate 1, and the periphery thereof is sealed with resin 5. It can also be applied to other methods, making circuit creation easier.

又この応用として一方の基板を金属板とし、外観の向上
や基板の補強、更には導通経路としても利用できる。
Further, in this application, one of the substrates is made of a metal plate, which can be used to improve the appearance, reinforce the substrate, and even serve as a conductive path.

上述のとおり、本考案は打抜き加工により発生した一方
の基板の抜きかすを他方の基板に押込み凹部を形成じた
ことによって、時計用基掘の、、2次加工を廃止し、そ
れにかかわる幾多の欠点を、解消するものである。
As mentioned above, the present invention eliminates the secondary machining of the base for watches by pushing the scraps of one board generated during the punching process into the other board to form a recess, and eliminates the numerous steps involved. It eliminates the shortcomings.

第1図において、2枚の・基板の板□厚はほぼ同じであ
るが、異なる板厚の基板、或いは異種材料(例えばプ、
リント基板と金属板等)でもよく、少なくとも2枚の金
属板でもよく、2枚構成の基板に限らず複数枚の積層基
板でもよい。
In Figure 1, the thickness of the two substrates is almost the same, but the substrates have different thicknesses or are made of different materials (for example, plastic,
A lint substrate and a metal plate, etc.) or at least two metal plates may be used.The substrate is not limited to a two-layer structure, but may be a plurality of laminated substrates.

又、実施例において、抜きかすの板厚内に両基板の接合
面を配したことにより、両基板の接合をより確実にする
こともでき、これによって第1基板と第2基板とを接着
剤等で固着しなくてもよい。
In addition, in the embodiment, by arranging the bonding surfaces of both substrates within the thickness of the punched scrap, the bonding of both substrates can be made more secure, and thereby the first substrate and the second substrate can be bonded together using an adhesive. It does not have to be fixed with etc.

更に第2基板の抜きかすは、第・1.基板の抜きかすと
固着された状態で第1.第2基板で構成された基板を構
成していてもよい。
Furthermore, the scraps from the second board are removed from the first board. The first one is stuck to the scraps of the board. The substrate may be composed of a second substrate.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示す断面図、第2図、第3
図は本考案の応用例を示す断面図・。 1・・・・・・第1基板、1a・・・・・・回路パター
ン、1b・・・・・・抜きかす、1C・・・・・・凹部
、2・・・・・・第2基板、2a・・・・・・回路パタ
ーン、2b・・・・・・抜きかす、2C・・・・・・凹
部、3・・・・・・ICチップ、4・・・・・・金線、
5・、・・・・・樹脂、6・・・・、・・素子、7・・
・・・・ピン。
Figure 1 is a sectional view showing one embodiment of the present invention, Figures 2 and 3.
The figure is a sectional view showing an application example of the present invention. 1...First board, 1a...Circuit pattern, 1b...Damage, 1C...Concavity, 2...Second board , 2a... circuit pattern, 2b... punching residue, 2C... recess, 3... IC chip, 4... gold wire,
5...Resin, 6...,...Element, 7...
····pin.

Claims (1)

【実用新案登録請求の範囲】 時計回路の一部を構成する電気素子が装置される時計用
基板において、前記時計用基板は少なくとも一部で固定
された2枚の基板の積層構を有しており、前記時計用基
板上面に電極パターンが配置されるとともに、前記電気
素子を装置する部分は打ち抜き加工により一方の基板の
一部を他方の基板に保合固定させて形成した凹部になっ
ていることを特徴とする時計用基板。 □
[Claims for Utility Model Registration] A timepiece substrate on which an electric element constituting a part of a timepiece circuit is installed, wherein the timepiece substrate has a laminated structure of two substrates fixed at least in part. An electrode pattern is disposed on the upper surface of the watch substrate, and the portion where the electric element is mounted is a recess formed by punching a part of one substrate and fixing it to the other substrate. A watch substrate characterized by: □
JP7542878U 1978-06-02 1978-06-02 Watch board Expired JPS5831429Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7542878U JPS5831429Y2 (en) 1978-06-02 1978-06-02 Watch board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7542878U JPS5831429Y2 (en) 1978-06-02 1978-06-02 Watch board

Publications (2)

Publication Number Publication Date
JPS54177973U JPS54177973U (en) 1979-12-15
JPS5831429Y2 true JPS5831429Y2 (en) 1983-07-12

Family

ID=28989820

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7542878U Expired JPS5831429Y2 (en) 1978-06-02 1978-06-02 Watch board

Country Status (1)

Country Link
JP (1) JPS5831429Y2 (en)

Also Published As

Publication number Publication date
JPS54177973U (en) 1979-12-15

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