JPH0851267A - Circuit board and its manufacture - Google Patents

Circuit board and its manufacture

Info

Publication number
JPH0851267A
JPH0851267A JP20811494A JP20811494A JPH0851267A JP H0851267 A JPH0851267 A JP H0851267A JP 20811494 A JP20811494 A JP 20811494A JP 20811494 A JP20811494 A JP 20811494A JP H0851267 A JPH0851267 A JP H0851267A
Authority
JP
Japan
Prior art keywords
conductor layer
substrate
substrate material
circuit board
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20811494A
Other languages
Japanese (ja)
Inventor
Hiroshi Sakashita
広志 坂下
Atsushi Yamashita
淳 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nidec Sankyo Corp
Original Assignee
Nidec Sankyo Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nidec Sankyo Corp filed Critical Nidec Sankyo Corp
Priority to JP20811494A priority Critical patent/JPH0851267A/en
Publication of JPH0851267A publication Critical patent/JPH0851267A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/05Insulated conductive substrates, e.g. insulated metal substrate

Abstract

PURPOSE:To obtain a thin circuit board without sagging by presswork, consisting of a substrate material where a conductor layer is formed on the surface of a conductive substrate via an insulation layer by providing a protruding part formed by half punching of the conductor layer of the substrate material and by forming a wiring pattern with the protruding part. CONSTITUTION:A substrate material 4 is constituted of three layers of a substrate 1 consisting of a conductive material such as metal, an insulation layer 2 consisting of thermosetting resin formed on one side of the substrate 1, and a conductor layer 3 consisting of a copper plate formed on the insulation layer 2. A half punching is performed to a surface where the substrate 1 is exposed at the lower side of the substrate material 4 and a protruding part 5 is formed at the side of the conductor layer 3. The conductor layer 3 lifted upward by the protruding part 5 becomes a wiring pattern in a proper shape, thus eliminating sagging at the time of half punching.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子部品等が搭載され
る回路基板及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board on which electronic parts and the like are mounted and a method for manufacturing the same.

【0002】[0002]

【従来の技術】本出願人は電子部品等が搭載される回路
基板及びその製造方法として、図5、図6に示すような
回路基板及びその製造方法を先に出願した。特願平5−
329553号にかかる発明がそれである。図5におい
て基板材24は、金属等の導電性の材料からなる基体2
1、熱硬化性樹脂等からなる絶縁層22、銅板等からな
る導体層23の三層から構成されている。基板材24
の、導体層23側の面にはプレス加工が施されて凹状の
半抜き部28が形成されており、この凹状の半抜き部2
8により、基板材24の基体21側の面には突出部25
が生じている。基板材24上の導体層23の一部は、半
抜き部28によって下方に沈み込んで分離され、この半
抜き部28内に沈み込んだ部分が適宜の形状の配線パタ
ーンとなっている。このように、基板材24に対して半
抜き部を28を形成して導体層23から配線パターンを
形成することにより、基板材24が回路基板となってい
る。
2. Description of the Related Art The present applicant has previously applied for a circuit board on which electronic parts and the like are mounted and a method for manufacturing the circuit board, as shown in FIGS. 5 and 6. Japanese Patent Application 5-
That is the invention relating to No. 329553. In FIG. 5, the substrate material 24 is a base 2 made of a conductive material such as metal.
1, an insulating layer 22 made of a thermosetting resin or the like, and a conductor layer 23 made of a copper plate or the like. Board material 24
The surface of the conductor layer 23 side is subjected to press working to form a concave half-cut portion 28. The concave half-cut portion 2
8 causes the protruding portion 25 to
Is occurring. A part of the conductor layer 23 on the substrate material 24 is sunk and separated downward by the half-cut portion 28, and the portion sunk in the half-cut portion 28 has a wiring pattern of an appropriate shape. As described above, the half blank portion 28 is formed on the substrate material 24 and the wiring pattern is formed from the conductor layer 23, whereby the substrate material 24 becomes a circuit board.

【0003】次に、以上のような回路基板の製造方法に
ついて説明する。まず、金属等の導電性の材料からなる
基体21と、銅板等からなる導体層23を熱硬化性樹脂
等からなる絶縁層22の介在のもとに貼り合わせて、基
板材24を形成する。次に、図6に示すように基板材2
4の基体21側の面をプレス金型のダイ26で支持す
る。次に、基板材24の導体層23側の面に対してパン
チ27を押しつけて半抜き部28を形成する。半抜き部
28を形成することにより、導体層23の一部が分離し
て半抜き部28内に沈み込み、この半抜き部28内に沈
み込まずに残った導体層23が適宜形状の配線パターン
となり、回路基板が形成される。
Next, a method of manufacturing the above circuit board will be described. First, a substrate 21 made of a conductive material such as metal and a conductor layer 23 made of a copper plate or the like are bonded together with an insulating layer 22 made of a thermosetting resin or the like interposed therebetween to form a substrate material 24. Next, as shown in FIG.
The surface of No. 4 on the side of the base 21 is supported by the die 26 of the press die. Next, the punch 27 is pressed against the surface of the substrate material 24 on the conductor layer 23 side to form the half-blanked portion 28. By forming the half-blanked portion 28, a part of the conductor layer 23 is separated and sunk into the half-blanked portion 28, and the conductor layer 23 remaining without being sunk into the half-blanked portion 28 has an appropriate shape. A pattern is formed to form a circuit board.

【0004】[0004]

【発明が解決しようとする課題】図6に示すように、基
板材24に対して半抜き加工を施す場合、プレス金型の
ダイ26で基板材24の基体21を保持し、絶縁層22
の介在のもとに導体層23と基体21とを半抜き加工す
ることとなる。絶縁層22には、導体層23と基体21
を貼り合わせるために弾性を有する熱硬化性樹脂が用い
られることが多い。従って、基板材24の導体層23側
にプレスを施して半抜き部28を形成すると、図7に示
すように、半抜き部28の周りの導体層23が絶縁層2
2の弾性に抗して下方に突出したプレスダレ23aが生
じてしまう。特に絶縁層22が薄い場合等には、プレス
ダレ23aが絶縁層22をまたいで導電性の基体21ま
で至り、導体層23と基体21がショートするなどの問
題が生じていた。
As shown in FIG. 6, when the substrate material 24 is subjected to half blanking, the die 21 of the press die holds the substrate 21 of the substrate material 24 and the insulating layer 22 is used.
Therefore, the conductor layer 23 and the base 21 are half-blanked. The insulating layer 22 includes a conductor layer 23 and a base 21.
In many cases, a thermosetting resin having elasticity is used to bond the two. Therefore, when the half-opened portion 28 is formed by pressing the conductor layer 23 side of the substrate material 24, the conductor layer 23 around the half-opened portion 28 becomes the insulating layer 2 as shown in FIG.
The press sag 23a protruding downward against the elasticity of No. 2 is generated. In particular, when the insulating layer 22 is thin, the press sag 23a reaches the conductive base 21 across the insulating layer 22, and the conductor layer 23 and the base 21 are short-circuited.

【0005】導体層23の一部であるプレスダレ23a
によって、導体層23と導電性の基体21がショートす
るのを防止するためには、絶縁層22の厚みや、半抜き
部28の深さ寸法を十分に大きく設定し、プレスダレ2
3aが基体21まで至らないようにする必要性がある
が、絶縁層22の厚みや、半抜き部28の深さ寸法を大
きく設定すると、回路基板の厚さ寸法が増大し、薄型化
が図れないといった問題点が生じてしまう。
Pressed sag 23a which is a part of the conductor layer 23
Therefore, in order to prevent the conductor layer 23 and the conductive substrate 21 from being short-circuited, the thickness of the insulating layer 22 and the depth dimension of the half-blanked portion 28 are set to be sufficiently large.
It is necessary to prevent 3a from reaching the base body 21, but if the thickness of the insulating layer 22 and the depth dimension of the half-blanked portion 28 are set to be large, the thickness dimension of the circuit board increases and the thickness can be reduced. There is a problem that it does not exist.

【0006】本発明は以上のような従来技術の問題点を
解消するためになされたもので、薄型で、しかも、プレ
スダレがない回路基板及びその製造方法を提供すること
を目的とする。
The present invention has been made in order to solve the above problems of the prior art, and an object of the present invention is to provide a thin circuit board which is free from press sag and a method for manufacturing the same.

【0007】[0007]

【課題を解決するための手段】請求1記載の発明は、導
電性の基体の面に絶縁層を介して導体層が形成された基
板材からなり、この基板材の導体層側の面には半抜きに
よって形成された突出部を有し、この突出部によって配
線パターンが形成されていることを特徴とする。
The invention according to claim 1 comprises a substrate material in which a conductor layer is formed on the surface of a conductive substrate through an insulating layer, and the surface of the substrate material on the conductor layer side is formed. It is characterized in that it has a protrusion formed by half blanking, and a wiring pattern is formed by this protrusion.

【0008】請求2記載の発明は、導電性の基体の両面
に絶縁層を介して導体層が形成された基板材からなり、
この基板材の一方の面には半抜き部を、他方の面には半
抜きによる突出部を有し、上記半抜き部と上記突出部に
よって上記基板材の両面に配線パターンが形成されてい
ることを特徴とする。
According to a second aspect of the present invention, there is provided a substrate material in which conductive layers are formed on both surfaces of a conductive substrate with insulating layers interposed therebetween.
The substrate material has a half-blanked portion on one surface and a half-blanked protrusion portion on the other surface, and wiring patterns are formed on both surfaces of the substrate material by the half-blanked portion and the protrusion portion. It is characterized by

【0009】請求項3記載の発明は、基体の面に導体層
を形成して基板材を得る工程と基板材の導体層側の面を
金型のダイで支持する工程と、基板材の基体側の面に適
宜のパターンに従って半抜き加工を施し導体層側の面に
突出部を形成して配線パターンを形成する工程を有する
ことを特徴とする。
According to a third aspect of the present invention, a step of forming a conductor layer on the surface of the substrate to obtain a substrate material, a step of supporting the surface of the substrate material on the conductor layer side with a die of a die, and a substrate of the substrate material. It is characterized by including a step of forming a wiring pattern by forming a protrusion on the surface on the conductor layer side by performing half blanking on the surface on the side according to an appropriate pattern.

【0010】[0010]

【作用】基板材に半抜きを施して導体層側に突出部を形
成することにより、突出部で押された導体層が分離され
配線パターンとなり、基板材が回路基板となる。
By forming a protrusion on the conductor layer side by half-cutting the substrate material, the conductor layer pressed by the protrusion is separated into a wiring pattern, and the substrate material becomes a circuit board.

【0011】[0011]

【実施例】以下、本発明にかかる回路基板及びその製造
方法について図面を参照しながら説明する。図1におい
て、基板材4は、金属等の導電性の材料からなる基体
1、基体1の一面側に形成された熱硬化性樹脂等からな
る絶縁層2、絶縁層2の上に形成された銅板等からなる
導体層3の三層から構成されている。基板材4の下側の
基体1が露出した面にはプレス加工によって半抜き加工
が施されており、この半抜き加工によって導体層3側に
は突出部5が形成されている。基板材4上の導体層3の
一部は、突出部5の端面によって上方に持ち上げられて
分離されている。この突出部5によって上方に持ち上げ
られた導体層3は適宜の形状の配線パターンとなってい
る。このように、基板材4に対して突出部5を形成して
導体層3を配線パターンとすることにより、基板材4は
回路基板となっている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A circuit board according to the present invention and a method of manufacturing the same will be described below with reference to the drawings. In FIG. 1, a substrate material 4 is formed on a base 1 made of a conductive material such as metal, an insulating layer 2 made of a thermosetting resin or the like formed on one surface of the base 1, and an insulating layer 2. The conductor layer 3 is composed of three layers, such as a copper plate. The surface of the lower side of the substrate material 4 on which the base body 1 is exposed is subjected to a half-pressing process by press working, and the protruding part 5 is formed on the conductor layer 3 side by this half-cutting process. A part of the conductor layer 3 on the substrate material 4 is lifted upward and separated by the end surface of the protruding portion 5. The conductor layer 3 lifted upward by the protrusion 5 has a wiring pattern of an appropriate shape. In this way, the board member 4 is a circuit board by forming the protrusions 5 on the board member 4 and forming the conductor layer 3 into a wiring pattern.

【0012】次に、以上のような回路基板の製造方法に
ついて説明する。まず、金属等の導電性の材料からなる
基体1と、銅板等からなる導体層3を、間に熱硬化性樹
脂等からなる絶縁層2を介在させて貼り合わせ、基板材
4を形成する。次に、図2に示すように基板材4の導体
層3側の面をプレス金型のダイ6で支持する。次に、基
体1側の面に対してパンチ7を押しつけて半抜きを施
し、プレス金型のダイ6で支持された導体層3側の面に
突出部5を形成する。突出部5が形成されることによ
り、導体層3の一部は突出部5の端面によって上方に押
し上げられると共に、導体層3から分離されて独立した
適宜の形状の配線パターンとなる。また、突出部5によ
って配線パターンが形成されることにより、基板材4は
回路基板となる。
Next, a method for manufacturing the above circuit board will be described. First, a substrate 1 made of a conductive material such as a metal and a conductor layer 3 made of a copper plate or the like are attached with an insulating layer 2 made of a thermosetting resin or the like interposed therebetween to form a substrate material 4. Next, as shown in FIG. 2, the surface of the substrate material 4 on the conductor layer 3 side is supported by the die 6 of the press die. Next, the punch 7 is pressed against the surface on the side of the base 1 to carry out half blanking, and the protrusion 5 is formed on the surface on the side of the conductor layer 3 supported by the die 6 of the press die. By forming the projecting portion 5, a part of the conductor layer 3 is pushed upward by the end surface of the projecting portion 5 and is separated from the conductor layer 3 to form an independent wiring pattern of an appropriate shape. Further, since the wiring pattern is formed by the projecting portions 5, the board material 4 becomes a circuit board.

【0013】以上のような回路基板及びその製造方法に
よれば、図3に示すように、突出部5の周りの導体層3
が直接、プレス金型のダイで支持されているため、導体
層3が基体1や絶縁層2の弾性変形の影響を受けプレス
ダレが生じるのを防止することができる。従って、絶縁
層2の厚みを最小限に設定しても差し支えなく、また、
半抜きによって形成される突出部の寸法も短くて済むの
で、回路基板を薄型化することができる。
According to the circuit board and the manufacturing method thereof as described above, as shown in FIG. 3, the conductor layer 3 around the protrusion 5 is formed.
However, since the conductor layer 3 is directly supported by the die of the pressing die, it is possible to prevent the conductor layer 3 from being affected by the elastic deformation of the base 1 and the insulating layer 2 and causing the press sag. Therefore, the thickness of the insulating layer 2 may be set to the minimum, and
Since the size of the protrusion formed by half blanking can be short, the circuit board can be thinned.

【0014】次に、図4に示す別の実施例について説明
する。図4において、基体1の両面に、絶縁層2、2’
と導体層3、3’が形成されてなる基板材9を用い、こ
の基板材9に対して半抜きによる突出部5を形成するこ
とによって配線パターンが形成されている。基板材9の
一方の面に形成された突出部5に存在して他の部分から
分離された導体層3と、基板材9の他方の面の半抜き部
8内に存在する導体層3’はそれぞれ配線パターンとし
て使用することができ、よって、基板材9は両面に配線
パターンを有する回路基板となる。なお、半抜きの際、
突出部5が形成される導体層3側の面はプレス金型のダ
イで支持されるため、プレスダレが生じることはない
が、導体層3’側の面には直接プレスが施されるため、
半抜き部8の周りの導体層3’の部分にプレスダレが生
じやすい。従って、導体層3’側で生ずるプレスダレが
基体1へ悪影響を及ぼすのを防止するため、絶縁層2’
の厚みは、比較的大きめに設定しておくのが好ましい。
Next, another embodiment shown in FIG. 4 will be described. In FIG. 4, insulating layers 2, 2 ′ are provided on both sides of the substrate 1.
The wiring pattern is formed by using the substrate material 9 on which the conductor layers 3 and 3'are formed, and forming the protruding portion 5 by half blanking on the substrate material 9. The conductor layer 3 existing on the projecting portion 5 formed on one surface of the substrate material 9 and separated from the other portion, and the conductor layer 3 ′ existing in the half-cut portion 8 on the other surface of the substrate material 9. Can be used as a wiring pattern, respectively. Therefore, the substrate material 9 is a circuit board having wiring patterns on both sides. In addition, when half-cutting,
Since the conductor layer 3 side surface on which the projecting portion 5 is formed is supported by the die of the press die, press sag does not occur, but the conductor layer 3 ′ side surface is directly pressed,
Press sag is likely to occur in the portion of the conductor layer 3 ′ around the half-blanked portion 8. Therefore, in order to prevent the press sag generated on the conductor layer 3 ′ side from adversely affecting the substrate 1, the insulating layer 2 ′ is
It is preferable to set a relatively large thickness.

【0015】[0015]

【発明の効果】本発明によれば、導電性の基体の面に絶
縁層を介して導体層が形成された基板材からなり、この
基板材の導体層側の面には半抜きによって形成された突
出部を有し、この突出部によって配線パターンを形成し
たため、半抜きの際のプレスダレを無くすことができ、
絶縁層の厚みや半抜き部の深さを大きく設定する必要が
なく、薄型化に寄与することが可能となる。
According to the present invention, it is made of a substrate material in which a conductor layer is formed on the surface of a conductive substrate through an insulating layer, and the surface of the substrate material on the conductor layer side is formed by half blanking. Since it has a protruding portion and the wiring pattern is formed by this protruding portion, press sag at the time of half blanking can be eliminated,
It is not necessary to set the thickness of the insulating layer or the depth of the half-blank portion to a large value, which can contribute to the reduction in thickness.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明にかかる回路基板の実施例を示す断面
図。
FIG. 1 is a sectional view showing an embodiment of a circuit board according to the present invention.

【図2】同上回路基板の製造方法の一工程を示す断面
図。
FIG. 2 is a cross-sectional view showing a step in the method of manufacturing the same circuit board.

【図3】同上実施例の要部を拡大して示す断面図。FIG. 3 is a cross-sectional view showing an enlarged main part of the above embodiment.

【図4】本発明にかかる回路基板のさらに別の実施例を
示す断面図。
FIG. 4 is a sectional view showing still another embodiment of the circuit board according to the present invention.

【図5】従来の回路基板の例を示す断面図。FIG. 5 is a cross-sectional view showing an example of a conventional circuit board.

【図6】同上回路基板の製造方法の一工程を示す断面
図。
FIG. 6 is a cross-sectional view showing a step of the method for manufacturing the same circuit board.

【図7】同上回路基板の例を要部を拡大して示す斜視
図。
FIG. 7 is a perspective view showing an enlarged main part of an example of the same circuit board.

【符号の説明】[Explanation of symbols]

1 基体 2 絶縁層 3 導体層 4 基板材 5 突出部 1 Base 2 Insulation Layer 3 Conductor Layer 4 Substrate Material 5 Projection

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 導電性の基体の面に絶縁層を介して導体
層が形成された基板材からなり、この基板材の導体層側
の面には半抜きによって形成された突出部を有し、この
突出部によって配線パターンが形成されていることを特
徴とする回路基板。
1. A substrate material comprising a conductive substrate and a conductor layer formed on the surface of the conductive substrate with an insulating layer interposed therebetween. The conductor layer side surface of the substrate material has a protrusion formed by half blanking. A circuit board having a wiring pattern formed by the protrusions.
【請求項2】 導電性の基体の両面に絶縁層を介して導
体層が形成された基板材からなり、この基板材の一方の
面には半抜き部を、他方の面には半抜きによる突出部を
有し、上記半抜き部と上記突出部によって上記基板材の
両面に配線パターンが形成されていることを特徴とする
回路基板。
2. A substrate material in which conductor layers are formed on both sides of a conductive substrate with an insulating layer interposed between the substrate materials. A circuit board having a protrusion, wherein a wiring pattern is formed on both surfaces of the substrate material by the half-blanked portion and the protrusion.
【請求項3】 基体の面に導体層を形成して基板材を得
る工程と、 基板材の導体層側の面を金型のダイで支持する工程と、 基板材の基体側の面に適宜のパターンに従って半抜き加
工を施し導体層側の面に突出部を形成して配線パターン
を形成する工程を有することを特徴とする回路基板の製
造方法。
3. A step of forming a conductor layer on the surface of a substrate to obtain a substrate material; a step of supporting the surface of the substrate material on the conductor layer side with a die of a mold; A method for manufacturing a circuit board, comprising the step of forming a wiring pattern by forming a protrusion on the surface on the conductor layer side by performing half blanking according to the pattern.
JP20811494A 1994-08-08 1994-08-08 Circuit board and its manufacture Pending JPH0851267A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20811494A JPH0851267A (en) 1994-08-08 1994-08-08 Circuit board and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20811494A JPH0851267A (en) 1994-08-08 1994-08-08 Circuit board and its manufacture

Publications (1)

Publication Number Publication Date
JPH0851267A true JPH0851267A (en) 1996-02-20

Family

ID=16550872

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20811494A Pending JPH0851267A (en) 1994-08-08 1994-08-08 Circuit board and its manufacture

Country Status (1)

Country Link
JP (1) JPH0851267A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1395100A1 (en) * 2002-08-29 2004-03-03 Ascom AG Process for treating and manufacturing of circuit boards and such a circuit board
WO2004027866A2 (en) * 2002-09-23 2004-04-01 Johnson Controls Technology Company Method for creating a link in an integrated metal substrate
JP2009154345A (en) * 2007-12-26 2009-07-16 Oshima Denki Seisakusho:Kk Film forming molding, method and apparatus for producing film forming molding
JP2018536976A (en) * 2015-12-08 2018-12-13 フィリップス ライティング ホールディング ビー ヴィ Assembly and lighting device having assembly

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1395100A1 (en) * 2002-08-29 2004-03-03 Ascom AG Process for treating and manufacturing of circuit boards and such a circuit board
WO2004027866A2 (en) * 2002-09-23 2004-04-01 Johnson Controls Technology Company Method for creating a link in an integrated metal substrate
WO2004027866A3 (en) * 2002-09-23 2004-08-19 Johnson Controls Tech Co Method for creating a link in an integrated metal substrate
JP2009154345A (en) * 2007-12-26 2009-07-16 Oshima Denki Seisakusho:Kk Film forming molding, method and apparatus for producing film forming molding
JP2018536976A (en) * 2015-12-08 2018-12-13 フィリップス ライティング ホールディング ビー ヴィ Assembly and lighting device having assembly
US10433418B2 (en) 2015-12-08 2019-10-01 Signify Holding B.V. Assembly and lighting device comprising the assembly

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