JPS5824240A - プログラム可能な集積回路 - Google Patents
プログラム可能な集積回路Info
- Publication number
- JPS5824240A JPS5824240A JP57125611A JP12561182A JPS5824240A JP S5824240 A JPS5824240 A JP S5824240A JP 57125611 A JP57125611 A JP 57125611A JP 12561182 A JP12561182 A JP 12561182A JP S5824240 A JPS5824240 A JP S5824240A
- Authority
- JP
- Japan
- Prior art keywords
- logic
- circuit
- integrated circuit
- data
- operations
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000872 buffer Substances 0.000 claims description 19
- 230000004913 activation Effects 0.000 claims description 2
- 230000003139 buffering effect Effects 0.000 claims description 2
- 230000004048 modification Effects 0.000 claims 1
- 238000012986 modification Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
- 238000007664 blowing Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 241001441724 Tetraodontidae Species 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/284,431 US4458163A (en) | 1981-07-20 | 1981-07-20 | Programmable architecture logic |
US284431 | 1981-07-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5824240A true JPS5824240A (ja) | 1983-02-14 |
JPS6364088B2 JPS6364088B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1988-12-09 |
Family
ID=23090202
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57125611A Granted JPS5824240A (ja) | 1981-07-20 | 1982-07-19 | プログラム可能な集積回路 |
Country Status (2)
Country | Link |
---|---|
US (1) | US4458163A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
JP (1) | JPS5824240A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63156414A (ja) * | 1986-12-05 | 1988-06-29 | モノリシック メモリーズ,インコーポレイテッド | プログラム可能論理回路 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USRE34363E (en) * | 1984-03-12 | 1993-08-31 | Xilinx, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
US4870302A (en) * | 1984-03-12 | 1989-09-26 | Xilinx, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
US4774421A (en) * | 1984-05-03 | 1988-09-27 | Altera Corporation | Programmable logic array device using EPROM technology |
US4684830A (en) * | 1985-03-22 | 1987-08-04 | Monolithic Memories, Inc. | Output circuit for a programmable logic array |
JP2565497B2 (ja) * | 1985-09-11 | 1996-12-18 | ピルキントン マイクロ−エレクトロニクス リミテツド | 半導体集積回路 |
US4771285A (en) * | 1985-11-05 | 1988-09-13 | Advanced Micro Devices, Inc. | Programmable logic cell with flexible clocking and flexible feedback |
US4701636A (en) * | 1986-05-29 | 1987-10-20 | National Semiconductor Corporation | Programming voltage control circuit for programmable array logic device |
US4730130A (en) * | 1987-01-05 | 1988-03-08 | Motorola, Inc. | Writable array logic |
US4783606A (en) * | 1987-04-14 | 1988-11-08 | Erich Goetting | Programming circuit for programmable logic array I/O cell |
US4839851A (en) * | 1987-07-13 | 1989-06-13 | Idaho Research Foundation, Inc. | Programmable data path device |
US4940909A (en) * | 1989-05-12 | 1990-07-10 | Plus Logic, Inc. | Configuration control circuit for programmable logic devices |
US5959466A (en) | 1997-01-31 | 1999-09-28 | Actel Corporation | Field programmable gate array with mask programmed input and output buffers |
US6150837A (en) * | 1997-02-28 | 2000-11-21 | Actel Corporation | Enhanced field programmable gate array |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4157480A (en) * | 1976-08-03 | 1979-06-05 | National Research Development Corporation | Inverters and logic gates employing inverters |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3987287A (en) * | 1974-12-30 | 1976-10-19 | International Business Machines Corporation | High density logic array |
IT1063025B (it) * | 1975-04-29 | 1985-02-11 | Siemens Ag | Disposizione circuitale logica integrata e programmabile |
US4207556A (en) * | 1976-12-14 | 1980-06-10 | Nippon Telegraph And Telephone Public Corporation | Programmable logic array arrangement |
US4240094A (en) * | 1978-03-20 | 1980-12-16 | Harris Corporation | Laser-configured logic array |
-
1981
- 1981-07-20 US US06/284,431 patent/US4458163A/en not_active Expired - Lifetime
-
1982
- 1982-07-19 JP JP57125611A patent/JPS5824240A/ja active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4157480A (en) * | 1976-08-03 | 1979-06-05 | National Research Development Corporation | Inverters and logic gates employing inverters |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63156414A (ja) * | 1986-12-05 | 1988-06-29 | モノリシック メモリーズ,インコーポレイテッド | プログラム可能論理回路 |
Also Published As
Publication number | Publication date |
---|---|
US4458163A (en) | 1984-07-03 |
JPS6364088B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1988-12-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0020608B1 (en) | Programmable storage/logic array | |
US6119181A (en) | I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures | |
US4631686A (en) | Semiconductor integrated circuit device | |
EP0840455B1 (en) | A microcontroller accessible macrocell | |
US5315178A (en) | IC which can be used as a programmable logic cell array or as a register file | |
US5321652A (en) | Microcomputer having a dual port memory of supplying write data directly to an output | |
JP3147432B2 (ja) | パイプライン処理装置 | |
JPS5824240A (ja) | プログラム可能な集積回路 | |
US5386155A (en) | Apparatus and method for selecting polarity and output type in a programmable logic device | |
JPH07504797A (ja) | 論理積項の縦続接続および改良したフリップフロップ利用を伴うマクロセル | |
JPS61198761A (ja) | 半導体集積回路 | |
Sidhu et al. | A self-reconfigurable gate array architecture | |
US5847450A (en) | Microcontroller having an n-bit data bus width with less than n I/O pins | |
KR100214195B1 (ko) | 필드 프로그램가능 게이트 어레이 및 그 방법 | |
US6020754A (en) | Look up table threshold gates | |
US6249149B1 (en) | Apparatus and method for centralized generation of an enabled clock signal for a logic array block of a programmable logic device | |
JPS60244111A (ja) | デイジタルフイルタ回路 | |
EP0289035B1 (en) | MOS Gate array device | |
JP2004040081A (ja) | プログラマブル・ゲートアレイ部を備えたマスクプログラマブル論理装置 | |
US6980025B1 (en) | Programmable function generator and method operating as combinational, sequential, and routing cells | |
CN100446421C (zh) | 可再程序化逻辑阵列 | |
US5039885A (en) | Single function programmable logic array circuit | |
JPS61198758A (ja) | 半導体集積回路の製造方法 | |
JPS61198762A (ja) | 半導体集積回路 | |
JP2552316B2 (ja) | Cmos半導体集積回路 |