JPS5822446A - ベクトル・マスク演算制御方式 - Google Patents

ベクトル・マスク演算制御方式

Info

Publication number
JPS5822446A
JPS5822446A JP56122024A JP12202481A JPS5822446A JP S5822446 A JPS5822446 A JP S5822446A JP 56122024 A JP56122024 A JP 56122024A JP 12202481 A JP12202481 A JP 12202481A JP S5822446 A JPS5822446 A JP S5822446A
Authority
JP
Japan
Prior art keywords
mask
register
arithmetic
bits
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56122024A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0241070B2 (enrdf_load_stackoverflow
Inventor
Hitoshi Abe
仁 阿部
Shigeo Nagashima
長島　重夫
Koichiro Omoda
面田　耕一郎
Hiroshi Murayama
浩 村山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56122024A priority Critical patent/JPS5822446A/ja
Publication of JPS5822446A publication Critical patent/JPS5822446A/ja
Publication of JPH0241070B2 publication Critical patent/JPH0241070B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
JP56122024A 1981-08-04 1981-08-04 ベクトル・マスク演算制御方式 Granted JPS5822446A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56122024A JPS5822446A (ja) 1981-08-04 1981-08-04 ベクトル・マスク演算制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56122024A JPS5822446A (ja) 1981-08-04 1981-08-04 ベクトル・マスク演算制御方式

Publications (2)

Publication Number Publication Date
JPS5822446A true JPS5822446A (ja) 1983-02-09
JPH0241070B2 JPH0241070B2 (enrdf_load_stackoverflow) 1990-09-14

Family

ID=14825693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56122024A Granted JPS5822446A (ja) 1981-08-04 1981-08-04 ベクトル・マスク演算制御方式

Country Status (1)

Country Link
JP (1) JPS5822446A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2585859A1 (fr) * 1985-07-31 1987-02-06 Nec Corp Unite de commande d'operations de masques vectoriels.
GB2476800A (en) * 2010-01-07 2011-07-13 Linear Algebra Technologies Ltd Sparse matrix vector multiplier using a bit map of non-zero elements to control scheduling of arithmetic operations

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5094841A (enrdf_load_stackoverflow) * 1973-12-22 1975-07-28
JPS5668864A (en) * 1979-11-09 1981-06-09 Fujitsu Ltd Instruction control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5094841A (enrdf_load_stackoverflow) * 1973-12-22 1975-07-28
JPS5668864A (en) * 1979-11-09 1981-06-09 Fujitsu Ltd Instruction control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2585859A1 (fr) * 1985-07-31 1987-02-06 Nec Corp Unite de commande d'operations de masques vectoriels.
GB2476800A (en) * 2010-01-07 2011-07-13 Linear Algebra Technologies Ltd Sparse matrix vector multiplier using a bit map of non-zero elements to control scheduling of arithmetic operations

Also Published As

Publication number Publication date
JPH0241070B2 (enrdf_load_stackoverflow) 1990-09-14

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