JPS58222643A - 通信制御装置 - Google Patents

通信制御装置

Info

Publication number
JPS58222643A
JPS58222643A JP57106380A JP10638082A JPS58222643A JP S58222643 A JPS58222643 A JP S58222643A JP 57106380 A JP57106380 A JP 57106380A JP 10638082 A JP10638082 A JP 10638082A JP S58222643 A JPS58222643 A JP S58222643A
Authority
JP
Japan
Prior art keywords
communication
line connection
line
register
display register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57106380A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6325736B2 (enExample
Inventor
Shigeru Takeuchi
滋 竹内
Toru Yabe
矢部　徹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57106380A priority Critical patent/JPS58222643A/ja
Publication of JPS58222643A publication Critical patent/JPS58222643A/ja
Publication of JPS6325736B2 publication Critical patent/JPS6325736B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)
JP57106380A 1982-06-21 1982-06-21 通信制御装置 Granted JPS58222643A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57106380A JPS58222643A (ja) 1982-06-21 1982-06-21 通信制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57106380A JPS58222643A (ja) 1982-06-21 1982-06-21 通信制御装置

Publications (2)

Publication Number Publication Date
JPS58222643A true JPS58222643A (ja) 1983-12-24
JPS6325736B2 JPS6325736B2 (enExample) 1988-05-26

Family

ID=14432099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57106380A Granted JPS58222643A (ja) 1982-06-21 1982-06-21 通信制御装置

Country Status (1)

Country Link
JP (1) JPS58222643A (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0395437U (enExample) * 1990-01-18 1991-09-30
JPH0395438U (enExample) * 1990-01-18 1991-09-30
JPH0635487U (ja) * 1991-04-10 1994-05-13 株式会社イノアックコーポレーション 二重床用床材
JPH0540480U (ja) * 1991-10-30 1993-06-01 俊彦 君島 配線用床材パネル

Also Published As

Publication number Publication date
JPS6325736B2 (enExample) 1988-05-26

Similar Documents

Publication Publication Date Title
US12119958B2 (en) Cross network bridging
US6715002B2 (en) Watermark for additional data burst into buffer memory
US7444459B2 (en) Methods and systems for load balancing of virtual machines in clustered processors using storage related load information
US8611368B2 (en) Controlling bandwidth reservations method and apparatus
US5317692A (en) Method and apparatus for buffer chaining in a communications controller
EP1779609B1 (en) Integrated circuit and method for packet switching control
JPS58222643A (ja) 通信制御装置
KR100333584B1 (ko) 데이터 전송 시스템
US20250181521A1 (en) Methods and apparatus to estimate consumed memory bandwidth
US7346725B2 (en) Method and apparatus for generating traffic in an electronic bridge via a local controller
US5764998A (en) Method and system for implementing a distributed interrupt controller
US7360007B2 (en) System including a segmentable, shared bus
JP2615127B2 (ja) 通信処理装置
JP2008502977A (ja) バス・コントローラのための割り込み方式
EP2042998B1 (en) Logic gateway circuit for bus that supports multiple interrupt request signals
JPS6049458A (ja) デ−タバッファ制御方式
US5838661A (en) Method and arrangement for shutting off a receive channel in a data communications system
JP2962767B2 (ja) Ｄｍａ装置のメモリアクセス方式
EP1110150B1 (en) Communicating the status of a peripheral device controller to a host processor
JPH0448843A (ja) パケット送受信制御方式
JPH058901B2 (enExample)
JPS5936456A (ja) 通信制御装置
JPS6325735B2 (enExample)
JPS62109452A (ja) デ−タ通信制御装置
JP3236973B2 (ja) デ−タ転送装置