JPS58222555A - Semiconductor device - Google Patents

Abstract

PURPOSE:To detect disconnection of load before or during the operation thereof without causing deterioration of load by providing a bipolar transistor which turns ON or OFF depending on the state that the drain-source voltage of MOS transistor is in the level of normal operation of load or 0 volt level during disconnection of load. CONSTITUTION:An input voltage Vin to be supplied to the input terminal 14 rises to H from L when the specified switching operation is carried out for operation of load 11 and thereby a MOS transistor 10 becomes ON. In case a load 11 is normally operating, a drain-source voltage Vd drops to ON voltage Von from the power supply voltage Vdd. This ON voltage Von is resulting from ON resistance of MOS transistor 10. Therefore, a voltage difference between the reference voltage Vb to be applied to the base B of bipolar transistor 12 and ON voltage Von to be applied to the emitter E is lower than a threshold voltage Vbe and therefore a base current Ib does not flow. The bipolar transistor 12 becomes OFF and a monitor output Vm at the disconnected monitor terminal 13 becomes H level.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device using a MOS l-transistor as a switching element, and more particularly, to a semiconductor device using a MOS l-transistor as a switching element. This relates to a semiconductor device built into an I board.

In recent years, the drive circuit has been simplified and integrated, and the power supply type L of the circuit has been simplified and integrated.
Barry MO8t-
There is a movement to apply transistors, especially vertical power MO31 transistors, which have low ON resistance and are suitable for power switching, to switches.

FIG. 1 is a diagram showing a switch circuit for switching a current flowing to a load using a normal vertical power MO3T transistor, and FIGS. 2 and 3 are diagrams showing its operation time chart 1.

As shown in FIG. 1, this switch circuit connects the drain D of a vertical power MOS l-transistor 1 whose source S is grounded to a load 2, and connects its MOS transistors 1 to 1G to a control input terminal 3. In addition, the monitor terminal 4 is drawn out from the drain D13.

In the switch circuit described in ``2'', if the pulse train Vin is supplied to the input terminal 3, the negative ? i! When i2 is normal, as shown in FIG. 2, the monitor output Vm is an inverted version of the input pulse train ViO, whereas f4?
When iii 2 is disconnected, the monitor output Vll+ is always '1~'' as shown in FIG. 3, and by monitoring this, it is possible to detect a disconnection in the load 2.

However, in such a switch circuit, a pulse train must be input to detect a load disconnection, so a multilayer oscillator circuit is required as an external component, which is disadvantageous when downsizing. Moreover, the repeated ON and OFF cycles may cause deterioration of the load.

The present invention was made in view of the above-mentioned circumstances [1], and its purpose is to provide a disconnection detection circuit that reliably detects disconnection of a load without causing deterioration of Mu, and a disconnection detection circuit for reliably detecting disconnection of a load without causing deterioration of Mu, and a busbar used as the switching element. It is an object of the present invention to provide a small-sized semiconductor device in which a 1NO MO8I transistor is integrated.

Hereinafter, one embodiment of the semiconductor device of the present invention will be described in detail with reference to FIG. 4 and subsequent drawings.

FIG. 3 is a circuit diagram showing an embodiment of the present invention, and this semiconductor element 100 has a source S grounded, and a drain D externally connected to a load 11 such as a pre-extinguishing heater. Vertical power M for switching the current flowing through 11
The OS transistor 10 (hereinafter simply referred to as MOS l-transistor 1) and the collector C are connected to the disconnection monitor output terminal 13.
an npn bipolar transistor 12 connected to the drain D of the MO8l-transistor 10, an input terminal 14 led out from the gate G of the MO3t-transistor 10, and
A resistor 1 connected between the collector C of the transistor 12
5, the input voltage \/in supplied to the input terminal 14 is divided by a resistor 1G and a resistor 17 connected in a tooth row between the input terminal 14 and the ground to form a reference voltage vb to be described later, It is comprised of a resistive voltage divider circuit 18 which supplies this reference voltage \/1) to the base of the bipolar transistor 12 by 11ξ.

Then, the reference voltage vb formed by the resistive voltage divider circuit 1B is the N junction forward threshold voltage Vl) between the base and earth mitter of the bipolar transistor 12.
e (hereinafter simply referred to as threshold voltage), and this threshold voltage V, be and the MO81-transistor 10
The voltage is set to be lower than the sum of the drain-source voltage Vd (hereinafter referred to as ON voltage Von) that occurs when the Von is turned on. In other words, using the sign of each voltage, the base t1
Expressing the relationship of 1 electric current [i' V d as a formula, VIIO < Vl] < VbO−+−Von−−−
---(1).

Semiconductor device i? configured as above? '? 100 (
) The operation of load disconnection detection is explained below.

By performing a predetermined switch operation to activate the trend 11, the input voltage Vi supplied to the input terminal 11!
n rises from 1'' to II HII, which causes MO
The S l-transistor 10 is turned on.

At this time, if the load 11 is operating normally, the train-source voltage Vd drops from the power supply voltage Vdd to the ON voltage Von, as shown in FIG. This O
The N voltage VOII is caused by the ON resistance of the MOS l-transistor 10.

Therefore, the potential difference (\/b-yon) between the reference voltage vb applied to the base B of the bipolar 1-disk 12 and the ON voltage vOn applied to the 1-mitter E is expressed by the equation (1) ), the threshold voltage Vb
The base current 11+, which is lower than e, does not flow.

Therefore, -C1 This bipolar transistor 12 is turned off, and the monitor output \/m at the disconnection monitor terminal 13 becomes ``1 degree''.

Next, if a disconnection accident has already occurred in the load 11 before the load 11 is operated, the input '
In juice Vin is it l-I II 1. 'r tsu'1
'When the MOS +- transistor 10 is turned on, the drain current 1d does not flow due to the disconnection of the load 11, and the train-source voltage Vd drops to GND (=0 volts).

Therefore, the base B of the bipolar transistor 12
The potential difference between Vb-0V and emitter E is higher than the threshold voltage Vl)B, as expressed by equation (1).

Therefore, the base current 1b flows, this bipolar transistor 12 is turned on, and the disconnection monitor terminal 7'13 (
), the monitor output Vm becomes ``[''''.

In addition, if a disconnection accident occurs in the load 11 while the load 11 is in operation, as shown by the broken line in FIG.
The drain-source interstitial ffVd of the Ranjimetal 10 drops to O volts, and the bipolar transistor 1 to the transistor 12 are turned on in the same way as when the disconnection occurred before the load 'fh operation.
The monitor output Vm becomes lI-11.

Nitsu-C1C1 "+4" of the above monitor voltage \/m.

It is possible to detect a pipe breakage based on the L' level, and also to reliably detect a breakage accident during load operation.

Next, FIG. 7 is a cross-sectional view showing the basic structure of the vertical power MO8l-transistor. A well region 22 and a source region 23 are formed on the surface of a drain region 21 made of a (N−) layer by double diffusion, and then electrodes 1 to 25 are formed via an St 02 film 24, and then an insulating layer is formed. 26 OJ,
A source electrode 27 is formed by vapor deposition of aluminum and aluminum.
'1.

In the semiconductor device of the present invention, each circuit element having the configuration shown in FIG. 4 is integrated and formed on the same semiconductor substrate as the vertical power MOS T-transistor in the manufacturing process of the vertical power MO8I-transistor. This enables integration by realizing separate formation of the vertical power M os transistor and each circuit element.

That is, as shown in FIG. 8, the resistive elements 15, 16, and 17 in FIG. By forming the circuit element 4 using the above method, it is possible to separate it from other circuit elements.

Further, as shown in the figure, the bipolar transistor 12 of FIG.
Since they are directly connected to the train D of the MOS l-transistor 10, integration is possible by adopting a reverse transistor structure.

4, the drain region of the MOS transistor 10 and 4
A bipolar transistor with a reverse transistor structure can be formed by sequentially forming and covering the base region 32 and the collector region 35 by referring to the N-type layer 31 as a transmitter region and sequentially forming and covering the N layer 31 and the collector region 35.

Here, the N-type layer 31 is the one layer E of the bipolar transistor 12 and the double MO8t transistor 10.
Since it also serves as the drain D of , special separation formation is invincible.

Therefore, as described above, the bipolar transistor 12 is
By overlapping with the transistor structure, all the circuit elements of one configuration shown in FIG. 4 can be integrated and formed on the same semiconductor substrate -F.

In addition, as shown in the process diagrams of FIGS. 9Δ and 9B, each of the circuit elements described above is formed. Since the culm is removed at the same time during the manufacturing process of the MOS transistor 10, a special work process is set up. This eliminates the need for additional work and improves work efficiency.

Hereinafter, for reference, an example of a method for manufacturing a semiconductor device according to the present invention shown in the process diagrams of FIGS. 9A and 9B will be briefly described.

First, as shown in FIG. 9A (a), after forming the 5i02 film 42 on the N-type W441 film by vapor phase growth, the MOS
l ~ transistor 10 and bipolar transistor 1
The Sr 0 2 film 42 in the portion where the transistor 2 is to be formed is removed by dipping to the first transistor 10.
The gate oxide film 43 is grown to a thickness of 1000 degrees.

Next, as shown in FIG. 9(b), the above sh.

Approximately 300% of poly-S i 44 is applied to the entire surfaces of the 2 film 42 and the goo 1 to oxide films 43 using a voltage vapor deposition apparatus or the like.
After approximately 0 ulC is grown, P+ is implanted by ion implantation. The dose of pt- at this time is set according to the resistance values of the hidden resistors 15, 16, and 17 as shown in FIG.

Next, as shown in Figure 9Δ(C''), the poly-8
Gate electrode 46 is formed by photoetching i411.
, J3J, and a resistor 47 are formed, and P+ ions are implanted while leaving Regimes 1 to 4 E).

Next, as shown in FIG. 9A(d), the resist 4 is
After removing 5, the above 1) is diffused at about 120° C. in nitrogen to form the base region 718 and 1] 1 region L@
Form 49.

The dose amount and diffusion conditions of P→ in this case are mainly UMO8.
It is set by the threshold voltage of the I-transistor 10 and the length.

Next, as shown in FIG. 9A (e), the base region 4B
A resist 1! is used to form a p-1 type region which will become a contact portion of the P well region 49. After masking and controlling P'- as shown in Fig. 9B(f), the above P+ is diffused shallowly in nitrogen at 1000'C:] to create a p-1-type region. Form and cover Vi50,51.

Next, as shown in FIG. 9B (g), the source region 52, the collector region 53 and the contact region 54 of the resistor 47 are connected.
7 skins with a resist value of ~45, and N+ ions are implanted.

Next, as shown in Figure 9B (h), the
1: N+ regions are formed in the registered contact regions 52, 53, and 54.

At this time, the above N+ diffusion is carried out by first annealing the C injection layer in nitrogen, and finally introducing oxygen lightly.
- forming a thin oxide film 55 on the surfaces of the groove electrode 46 and the resistor 47;

This oxide film 55 is for preventing the [ ] in the PSG from entering into the resistor 47 and the gate electrode 1ii46 during the heat treatment of the PSG (phosphorus glass) in the next step.

Next, as shown in FIG. 9B (+), PSG 56 was grown in a vapor phase and heat treated I! l! After etching (for example, 1050'C), the PSG 56 and the oxide film 55 in the portions that will become each contact region are removed by photoetching.

Next, as shown in FIG. 9B (j), a wiring pattern 557 is formed by vapor deposition of aluminum using photoetching.
form.

Although not shown, the semiconductor device according to the present invention is obtained by sintering (for example, immersion in hydrogen at 450° C.) following the step shown in FIG. 9B (j).

As explained above, in the semiconductor device of the present invention,
ON/OF depends on whether the drain-source voltage of the MOS transistor is at the 1L11 level i-" when the load is operating normally, or at the 0pol1 level when the load is disconnected.
By providing a bipolar transistor that performs F, it is possible to accurately detect not only load disconnection before load operation, but also load disconnection during load operation without causing deterioration of the load.

In addition, by adopting the reverse structure of the bipolar transistors 1 to 1 to transistors, it is possible to integrate them on the same semiconductor substrate as the vertical power MO3IP transistors without adding any special process, and it is possible to produce a large amount of R. It has the advantage of being useful and having low production costs.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a switching circuit using a power MO8)-transistor, Figs. 2 and 3 are time charts illustrating the disconnection detection operation of the switching circuit in Fig. 1, and Figs. Fig. 4 shows a circuit diagram showing the electrical configuration of the semiconductor device of the present invention, Fig. 5 shows a time chart for its operation during normal operation, and Fig. 6 shows its alarm operation when the load is disconnected. 7 is a sectional view showing the basic structure of a vertical power MOS +- transistor, FIG. 8 is a sectional view showing the structure of the semiconductor device of the present invention,
FIGS. 9(Δ) and 9(B) are process diagrams showing an example of a method for manufacturing the semiconductor device. 10... Vertical power M OS h run raster 1
2... Bipolar 1 - transistor 15, 1
6. 17... 1 person against 18...
・Resistance voltage divider circuit Vd...Drain-source voltage V11...
...Reference voltage ym...Monitor output voltage 30...Semiconductor substrate 31...Drain region, emitter/vine region 32...
...Base region 35...Contact region Patent applicant Figure 1 Figure 2 Figure 3 Figure 4 ++ Figure 5 -1 m Fig. 7 11 Fig. 8 Fig. 9 (Amendment of A procedure, July 22, 1980, Commissioner of the Japan Patent Office Mr. Wainu Wakasugi, 1, Indication of matter A'1, Patent Application No. 104748, 1987, 2)
, Name of the invention Semiconductor device 3, Relationship with the exercise for making amendments A'1 1''!i N'l Applicant (1 place)
2 Takaracho, Kanayō Ward, Yokohama City, Kanagawa Prefecture Name (39)
9) Kuchisan Jidoichi Co., Ltd. Representative: Shun Ishi, 4, Agent: 101-11 Address: 1-15-16 Uchikanda, Toshutochiyokorisu
Item (1) The scope of claims is amended as shown in the attached sheet. (2) The statement "1 base" on page 2, line 10 of the specification,
Corrected as "board". (3) On page 2, line 10 of the specification, [Front lights off 1 is corrected to read "headlights."(4> Mei 11I, page 8, line 6 to page 11, line 11)
[This vertical power MO8l transistor is...
・Goo 1 - After electrode 25 is formed and IS,"
``This vertical power MO8I-transistor has 5i02 film 2
After the electrode 25 is formed on the goo 1 through the electrode 4, a P region 22 and a source region 23 are formed on the surface of the train region 21 made of -1-pitaxytrue (N+) with high specific resistance on the semiconductor substrate 20. It is formed by heavy diffusion and corrected to 1. (5) Change rN-J on page 9, line 4 of the specification to “
"N-" he corrected. (6) On page 9, line 4 of the specification, “poly-siJ” has been corrected to rpoly-siJ. (7) On page 9, line 13, 14, and 18 of the specification, “ "N-" was corrected to IN-J. (8) Clear ml No. 10Bj Line 14 Ni'rN-J is corrected to "N-". (9) On page 10, line 15 of the specification, "vapor phase growth" is corrected to "thermal oxidation." (10) In the 2nd line of page 11 of the Meiji Illustrated Edition, the phrase ``voltage j'' has been corrected to ``reduced pressure.'' (11) "P-1" in the first and fifth lines of page 12 of the specification
(12) Page 10 of the specification, lines 15, 14, and 16.
In the 1st line, "P(" is corrected to "B+ (Boron)". (13) In the 11th page, 13th line of the specification, "120°C" is changed to I'1200°C. (14) The phrase "P+ type" in the first line of page 12 of the specification has been corrected to read "one type". (15) The statement in the second line of page 12 of the specification has been corrected. "P+" should be corrected to "B+ (Boron)". (16) "P+" should be corrected to "1B+ (Boron)" on the fourth line of page 12 of the specification. iF'Jru. (17) On page 12, line 4 of the specification, the phrase "r P + type" is corrected and reversed to "P type J". (18) Specification, page 12, line 9 [r N, i-J in 1
I corrected it to "P+ (phosphorus)". (19) "N0" on page 12, line 11 of the specification has been corrected to "P (phosphorus)." (20) Correct the 4th broken wire on page 9 of the specification as "N raw type". (21) In the specification, page 12, line 14, "1 to 1N to" is corrected to I'P (lin) 1. (22) The figure number “Figure 9 (△)” has been corrected to “Figure 9A” as shown in the attached drawing. (23) The figure number ``Figure 9 (B)'' has been corrected to ``Figure 98 J,'' as shown in the attached NJ drawing. (24) Figure 9 ('B) ([N-1 written in (1>)
is corrected to "P+" as shown in the attached drawings. (25) To page 14, No. 181) of the details, line 19 [
Figure 9 (A> and (B)
Figures 9B and 9B are corrected as ". 2. Special feature 6' [Claim (1) A MOS transistor which is connected to an external load and switches the current flowing through the load]
f) N junction forward threshold voltage J: between the bipolar transistor connected to the load side connection M of the 8t transistor and the base-emitter of the bipolar transistor 1 to the transistor; a reference potential generating circuit which converts a potential lower than the sum of the threshold voltage and the drain potential of the MO8I transistor when it is ON into a reference potential and supplies it to the bases of the pibo'71 transistors; 1. A semiconductor device comprising: an input terminal led out from the gate of the transistor; and a resistor connected between the input terminal and the collector of the transistor. A semiconductor device according to claim 1 of the Dozuru 11th edition. (3) The above-mentioned base Ill electric i'/zadezaki circuit (,4,1)
11. 1g is connected between the human-powered pane and the seat, and the hexagonal end - rt = the above-mentioned power supply 117 from the human-powered type 1i to be delivered.
(! Type 1 Hollow Resistance Valve L "Circuit (Characterized by 1 Jr ri'l Crystal Search Range 1 JfiiC Nog 1
') 9 limbs [awakening.

Claims (2)

[Claims] (1) A MOS t-transistor connected to an external load to switch the current flowing through the load, a collector connected to the disconnection monitor output terminal, and an emitter connected to the MO
8l- A bipolar transistor connected to the load side connection terminal of the transistor and the PN junction forward threshold voltage fffl between the base and emitter of the bipolar transistor.
a reference potential generation circuit that supplies the base of the bipolar transistor with a potential higher than E and lower than the sum of 1) the N-junction forward threshold voltage and the drain potential of the MO8l transistor when it is turned on as a reference potential; , a resistor connected between an input terminal led out from the gate of the MOS transistor and a collector of the bipolar transistor, and the bipolar transistor has a vertical inverted 1-transistor structure. semiconductor devices. (2) The reference potential generation circuit is a resistive voltage divider circuit connected between the input terminal and ground and forming the reference potential from the input voltage supplied to the input terminal. A semiconductor device according to scope 1.