JPS58219891A - Generating circuit of digital signal - Google Patents

Abstract

PURPOSE:To form a small-sized inexpensive digital signal generating circuit only by logical elements by delaying one control signal successively by plural shift registers to change values outputted from a logical circuit. CONSTITUTION:A synchronizing signal HV/Sync is inputted to a shift register 29 consisting of delay elements 311-314. The outputs (a)-(d) of the shift register 9 are inputted to the logical circuit 30 consisting of AND circuits 32-38 and OR circuis 39-42 and outputs S0-S7 are generated as digital synchronizing signals S from terminals TS0-TS7. When the input signal is ''0'', the S is ''4'' because only the S0 is ''1''. When the input signal is ''1'', the outputs (a)-(d) are turned to ''1'' successively, the S is changed from 4 to 16, 40, 58, and 60, and when the input signal is turned to ''0'', reverse change is generated. At the input of the input signal, digital pulse signal is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a novel digital signal generation circuit, and in particular to a novel digital signal generation circuit that can generate multi-bit digital signals whose digital values change in a complex manner with an extremely simple circuit configuration. The present invention attempts to provide a digital signal generation circuit.

Background Art With the development of digital signal processing technology, digital technology is becoming mainstream in various fields of electronic technology, and for example, there is a tendency for images to be processed using digital technology even in color video cameras. If processing is carried out by digital techniques, it is necessarily necessary to generate various digital signals.

Figure 1 shows the so-called black burst signal required in a color video camera, that is, the portion of the video signal consisting only of synchronization signals without video information. It is clear that there is a need to generate digital signals corresponding to analog signals whose amplitudes vary in a complex manner.

PRIOR ART There are the following techniques for generating such a digital signal, for example, a black burst signal. This was filed by the applicant (1982 patent application fltll 974).
No. 38), one black burst signal is decomposed into multiple signals, information regarding each pattern is stored in memory, and information regarding each pattern is read out in a predetermined order to generate one black burst signal. It is used to obtain signals. With this technology, even if a black burst signal with a complex pattern is divided into time units of, for example, 1/2H (H, water shell period), it is only a combination of signals with relatively few types of patterns. According to this technology, a relatively small capacity memory is provided, information on each pattern signal is stored in each area of the memory, and information on each pattern signal is read out in a fixed order. Thus, it is possible to obtain a blank burst signal and other digital signals whose digital values change in a complex manner.

However, providing a pattern signal storage memory and a program control circuit in a color video camera is not only possible when forming them on an independent integrated circuit (IC), but also on an IC on which a color encoder circuit, etc. is formed. Even if it is formed, it becomes a factor that suppresses the miniaturization and price reduction of cameras.

Means for Solving the Problems Therefore, the present invention seeks to provide a novel digital signal generation circuit that can generate multi-bit digital signals whose digital values change in a complex manner with an extremely simple circuit configuration. - a shift register consisting of a plurality of delay elements for shifting one control signal;
A logic circuit for forming a digital signal composed of a plurality of logic gates such as AND, OR, and/or NOT;
each input terminal of the logic circuit is connected to an output terminal of one of the plurality of delay elements constituting the shift I register, and the control signal is shifted through the shift register one bit at a time. The present invention is characterized in that the digital value of the plurality of bits of the digital output signal of the logic circuit changes as σ changes in a preset manner.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Below, the digital signal generation circuit of the present invention will be explained in detail according to embodiments shown in the accompanying drawings.

FIG. 2 is a block diagram showing the entire internal circuit of a color video camera using the digital signal generating circuit of the present invention as part of the black burst signal generating circuit, where l is R.
A solid-state image sensor for obtaining a signal component, 2 a solid-state image sensor for obtaining a G signal component, and 3 a solid-state image sensor for obtaining a B signal component, each of which is made of, for example, a COD. The numerical output signals R, G, and B of the solid-state image sensors 1 and 2.3 are appropriately amplified by a preamplifier 4.5.6, and a sampling hold circuit 7.8.9 has both a sampling function and a waveform shaping function. sampled at A/D
It is input to a converter 10.11.12 where it is converted into a digital signal. The signals R1G and B converted into digital signals are subjected to signal processing such as γ correction, pedestal level adjustment, clamping, and clipping in process circuits 13, 14, and 15, and are input to the matrix 16. And from the matrix 16, Y=0.3OR+0.59G+O, l IBI=Q
, 60R-'0.28G-0,32BQ=0.21R-
A luminance signal Y and chroma signals I and Q indicated by 0,52G-0,31B are output. Chroma signal 1. Q is level-adjusted for white balance in white balance circuits 17 and 18, and is then input to the NTSC color encoder 19 together with the luminance signal Y. The color encoder 19 has E=Y+Qs i
n (ωcsc* t+33°)+Icos (ωc
sc@t+33°) (where ωCSC is the angular velocity of the color subcarrier signal)
At the same time, by adding the signal from the black burst signal generation circuit 20 to the signal E, a desired pedestal level is given, and the horizontal and vertical synchronization signals H/V-S
It functions to add ync and burst signal Burst. Thus, the color encoder 19 outputs an NTSC composite signal, and this composite signal is converted into an analog signal by the D/A converter 21.

In FIG. 3, the black burst signal generation circuit 20
22 is a block diagram showing a digital synchronization pulse signal S of 8 pins from the synchronization pulse signal H/V-3ync; 23;
is a burst forming signal generating circuit which receives a burst flag signal BurstFLag and generates two digital signals BI and BQ for burst forming. The digital signal BI is a burst signal Burst having a predetermined level.
The digital signal BQ has a digital value of the magnitude when sampled on the I axis, and the digital signal BQ is also the burst signal Bur.
It has a digital value of the magnitude when st is sampled on the rotation axis. 24 is a digital signal B controlled by a switching circuit signal C5C' having a frequency 2fcsc which is twice the frequency fesc of the color subcarrier signal esc.
25 is a digital signal B output from the switching circuit 24;
This is an exclusive OR circuit that receives I and BQ and color subcarrier signal C5C, and color subcarrier signal Cs
, c is "0", the output signal of the switching circuit 24 is sent out as is, and the color subcarrier signal C8C is "0".
1'', it plays the role of inverting the output of the switching circuit 24 and sending it out. That is, the exclusive OR circuit 25 receives the digital signal BI, ``1'' from the switching circuit 24, and outputs the digital signal signals BI, BQ, and BQ when receiving the subcarrier signal esc. , "l" is inverted by creating its complement.This exclusive OR circuit is provided on eight sides corresponding to each bit of the digital signal B1. Each circuit receives a corresponding bit signal at one input terminal, and receives a color subcarrier signal esc at the other input terminal, but in the drawing, eight signals are received by one exclusive OR circuit 25. This is a representative example.In order to invert the digital signals BI and BQ by creating their two's complements, it is insufficient to simply invert each bit of the digital signals B1 and BQ using the exclusive OR circuit 25. Therefore, it is necessary to further add l to the digital signal, but in this embodiment, the output signal of the exclusive OR circuit 25 and the pedestal level of the digital value "60" generated from the pedestal level signal generation circuit 26 are used. The necessary addition of l is performed by applying the color subcarrier signal esc as a carry to the least significant bit portion of the adder circuit 27 that adds the signals. Here, the pedestal level signal with a digital value of "60" is added to the exclusive OR circuit 25 because the pedestal level is applied to the digital signals B■ and BQ, which are not given the pedestal level and are generated from the burst forming signal 23. However, if the burst forming signal generating circuit 23 outputs only the digital signal B to which the pedestal level is applied, it becomes unnecessary. 28 is a selector for forming a black burst signal from the digital synchronization signal S and the burst signal Burst, which uses the difference between the generation time of the digital synchronization signal S and the generation time of the burst signal Burst to generate a black burst signal by an appropriate switching signal. The digital synchronization signal generation circuit 22 and the addition circuit 27 are alternately selected to generate the black burst signal BLackBurst.
and convert it into the NTSC color encoder 1 in Figure 2.
Send to 9.

4 shows the digital synchronizing signal generating circuit 22 of the black burst signal generating circuit 20 in FIG. 3, and FIG. 5 shows the burst forming signal generating circuit 23. Digital synchronization signal generation circuit 22 shown in FIG.
The present invention is applied to the eight-stroke forming signal generation circuit 23.

First, the digital synchronization signal generation circuit 22 will be explained. This digital synchronization signal generation circuit 22 includes a 4-bit shift register 29 for shifting the synchronization signal H/V-SYNC input thereto, and a logic circuit 30 for forming the digital synchronization signal. Reference numerals 311 to 314 are delay elements constituting the shift register 29, and this shift register 29 receives a synchronization signal bit by bit at the same period as that of the color subcarrier signal esc by a signal having a frequency four times as high as the frequency fcsC of the color subcarrier signal esc. H/V-5
Shift ync.

The logic circuit 30 consists of seven AND circuits 32 to 38 and four OR circuits 39 to 42, and the signals 5O to S7 of each bit of the 8-bit digital synchronization signal S output from the logic circuit 30 are output terminals. It is output from TSO to TS7.

Beep) 0 signal s.

The output terminal TSO that outputs is grounded, and its signal SO is always kept at "0". A signal Sl of bit l outputted from the output terminal TSl is formed by AND circuits 32 and 33 and an OR circuit 39. The AND circuit 32 receives the inverted output signal d of the delay element 314 at one input terminal, receives the output terminal C of the delay element 313 as is at the other input terminal, and sends the output signal cod to one input terminal of the OR circuit 39. Send to. Moreover, the AND circuit 33 receives the output terminal of the delay element 312 at one input terminal, and receives the output terminal of the delay element 31. The output terminal baa is inverted and received, and the output terminal baa is sent to the other input terminal of the OR circuit 39. Therefore, the signal Sl output from the OR circuit 39 becomes cecl+a*b.

The bit 2 signal S2 outputted from the output terminal TS2 is formed by an AND circuit 34, 35 and an OR circuit 40. The AND circuit 34 receives the output signals a and d of the delay elements 311 and 314, and sends the output signals a and d to one input terminal of the OR circuit 40, and the AND circuit 35 receives the output signals a and d.
are inverted and received, and the output signal add is sent to the OR circuit 4.
0 to the other input terminal. However, OR circuit 4
The signal S2 output from 0 becomes a·d+τ·7.

The bit 3 signal S3 output from the output terminal TS3 and the bit 5 signal S5 output from the output terminal TS5 are as follows.
Since it is formed by an OR circuit 41 that receives output signals S and C output from delay elements 312 and 313, b
The bit 4 signal S4 outputted from the output terminal TS4 which becomes +c consists of AND circuits 36 to 38 and an OR circuit 42 that receives the output signals thereof. The AND circuit 38 receives the inverted signal C and receives the signal d as is, and the AND circuit 38 receives the inverted signal S and receives the signal a as is. Therefore, the signal S4 output from the OR circuit 42 is b−C+τ・d+
It becomes b.a.

In addition, both output terminals TS6 and TS7 are grounded,
Then, the signal S6 of bit 6 and the signal S7 of bit 7 that are output always keep "0".

Therefore, the signals SO to S7 of each bit of the digital synchronization signal S output from the digital synchronization signal generation circuit 22 shown in FIG. 4 are summarized as follows.

57=rOJ (always 0) S6=“0” (always 0) S5=b+c S4=asb+d@c+b*c S 3=b+c S2=lL@Ryo+a・d S l=a@b+c@d SO=rOJ ( Always O) Next, the burst forming signal generation circuit 23 shown in FIG. 5 will be explained. This burst forming signal generating circuit 23 includes a 9-bit shift register 43, a logic circuit 44 that generates digital signals BI and 2 for burst forming,
The shift register 43 consists of nine delay elements 451.
459 and has a frequency four times the frequency fC5C of the color subcarrier signal esc, the burst flag signal Bu
Shift r s t F' L a g by 1 bit.

The logic circuit 44 is a portion 44 that forms the digital signal BI.
I and a portion 44Q forming digital signal line 1, 44I is connected to AND circuits 46 to 51, and to input circuit 52.
and OR circuits 53 and 54, and the digital signal BI
The signals B10 to BI7 of each bit are output from T10 to T17.

The bit 0 signal BIO output from the output terminal TIO is formed by AND circuits 46, 47, 48 and OR circuit 53. The AND circuit 46 receives the inverted output signal i of the delay element 459 , receives the output signal g of the delay element 455 as it is, and sends the output signal T e g to the OR circuit 53 .

The AND circuit 47 receives the output signal g and receives the inverted output signal e of the delay element 451.

Further, the AND circuit 48 inverts and receives the output signals e and i, respectively. Thus, the output signals of the AND circuits 46 to 48 are received, and the signal BIO output from the OR circuit 53 is
becomes i・g+g@e+e@i. Pip) 1 and bit 3 signals BI output from output terminals TII and Tl3
I and BI3 become the signal i obtained by inverting the output signal g of the delay element 455 by the inverter 52.

The bit 2 signal BI2 outputted from the output signal TI2 is formed by AND circuits 49 to 51 and an OR circuit 54 receiving these output signals.

AND circuit 49 receives the output signal g of delay element 457 inverted and receives the output signal g of delay element 455 as is. The AND circuit 50 receives the signal g and inverts the output signal f of the delay element 453, and the AND circuit 51 receives the signals f and h, respectively, inverted.

Therefore, the signal BI2 output from the OR circuit 54 receiving the output signals of the AND circuits 49 to 51 is
+gΦh.

In addition, the output terminals TI4 to TI7 are each grounded, and the signals BI of beat 2 bit 4 to bit 7 output therefrom are grounded.
4 to BI7 are all always "0" ・Logic circuit 44Q is AND circuit 55 to 62 and OR circuit 6
3 to 65, and output from the logic circuit 44Q.
Digital signal of bit ■Signal of each bit of 1 “Page 1~
"Page 7 is output from output terminals TQO to TQ7. Signals of bit O and bit l output from output terminals TQO and TQl. Page 1 and 1] are output signals from AND circuits 55 and 56 and these. The AND circuit 55 receives the signal g inverted and receives the signal f as it is.AND circuit 5
6 receives the signal i and inverts the signal ri. Therefore, the signals BQO and BQI output from the OR circuit 63 receiving the output signals of the AND circuits 55 and 56 are i.
It becomes f + h meeting i.

Signal BQ2 output from output terminal TQ2 is formed by AND circuits 57 and 58 and an OR circuit 64 that receives this output signal. The AND circuit 57 inverts the signal g and receives the signal g as it is. Also, AND circuit 5
8 receives the signal and receives the inverted output signal f. Therefore, the signal BQ2 output from the OR circuit 64 receiving the output signals of the AND circuits 57 and 58 is hψg+h
・It is T. Also, the signal B output from the output terminal TQ3
Q3 is formed by AND circuits 59 to 61 and an OR circuit 65 that receives their output signals. AND circuit 59
receives signal g inverted and receives signal g as is. Conversely, the AND circuit 60 receives the signal g inverted and receives the signal g as is.

Further, the AND circuit 61 receives the signals f and i after inverting them. The OR circuit 65 receives the output signals from the AND circuits 59 to 51 and outputs the signals. Also, output terminal T
The signal Q4 output from Q4 is formed by the OR circuit 62 which receives inverted signals g and h, so the signal Q4 is
+h.

Further, the output terminals TQ5 to TQ7 are grounded, and the signals BQ5 to BQ7 of bits 5 to 7 outputted therefrom are grounded.
is always "0".

Here, the burst forming signal generation circuit 2 shown in FIG.
The burst forming signal BI output from 3 and the signals BIO to BI7 and BQO to BQ7 of each bit of 1 are summarized as follows.

BI7=“0” (always 0) BI6=rOJ (always 0) Bz5=rl (always 0) BI4=rOJ (always O) BI3=g BI2=f Skewer h+f-g+g*h BIl=g BIO=i* g+e*g+es 1 BQ7= r(N (always O) "Page 5=rOJ (always O)" BQ4=gh "Page 3=h・g+)1sg+f*i "W7=ball・g+h・T "tel= g*f+L*h 1teO=g-f+i φ1 The black burst signal generation circuit 20 shown in FIG. 3 below
The operation will be explained along the time chart shown in FIG.

Shift register 29 of digital synchronization signal generation circuit 22
When the synchronization signal H/V-5sync is input to the delay element 311.312.3 that constitutes the shift register 29,
A synchronizing signal S whose digital value changes in response to changes in the output signals a, b, c, and d of 13.314 is output from the logic circuit 30. The synchronization signal H/V-3ync is shown in Table 1 below.
, a, b, C, d and changes in the digital synchronization signal S.

Table 1 Also, when the burst flag signal Burstflag is input to the shift register 43 of the burst forming signal generation circuit 23, the output signal of the shift register 43 is 6. f
, g, h, and i, the digital signals Bl and ``page'' for forming a burst signal whose digital values change in response to changes in the output signals of the output signals 44I and 44Q are output from the logic circuits 44I and 44Q.

Table 2 below shows the burst flag signal BurstFLag.
, e, f, g,)1. 3 shows changes in i and digital signals BI and BQ for burst formation.

Table 2 By the way, digital signals B1 and BQ for burst formation
is the frequency of the color subcarrier signal esc
It is input to a select 24 controlled by a switching signal esc' having a frequency 2fcsc which is twice that of c. Therefore, from the select, the digital signal B1 . BQ is output alternately. And this select 24 colors B Q, B I, BQ, B 1. BQ
NLL: The digital signals that are alternately output are inverted when the color subcarrier signal esc is rlJ,
When it is "0", it is directly input from the exclusive OR circuit 25 to the addition circuit 27. Thus, the signals input to the addition W, #l path 27 are BQ, B1 . BQ, BI, BQ, BI,
BQ, B1. BQ... and forms a digital burst signal BursE. This digital value is 0, Olo, l, -4, -5, 12, 1O1-19,
-14,24,15,-24,-15,24,15,-
24, -15・Ki・-24, -15,24,15,-2
4,-15,24,14,-19,-1O112,5,
It changes like -4, -1, 0, 0, 0, 0... This digital burst signal B r st is added with "60" by the signal from the pedestal level signal generation circuit 26 in the adder circuit 27 and sent to the selector 28 .

The black burst signal Bur is sent to this selector 28.
A digital synchronization signal S from the digital synchronization signal generation circuit 22 is also input together with st, and a black burst signal Black as shown in FIG.
BurSt is output. Then, this black burst signal BLack Burst is transmitted to the NT shown in FIG.
It is input to the SC color encoder 19.

Note that 1, Q, I, and Q written in the part showing the signals esc' and esc in FIG. 6 are BI, Wl,
100], which indicates BQ, and B is simply omitted for convenience.

Further, although FIG. 7 shows a portion of the black burst signal that particularly corresponds to the horizontal synchronizing signal Hsync and a subsequent portion thereof, the portion corresponding to the vertical synchronizing signal Vsync also has the same pattern.

Incidentally, as shown in FIG. 8, the subcarrier signal esc(a) in one horizontal scanning period and the subcarrier signal esc(b) in the next horizontal scanning period are reversed in phase, so it is inevitable that As shown in FIG. 7, the /hast signal Burst(a) in one horizontal scanning period and the burst signal Burst(b) in the next horizontal scanning period are
) (indicated by a broken line) As described above, the black burst signal generation circuit 20 generates the black burst signal B L a c'kBurst.
can occur.

By the way, the black burst signal BLack B
As is clear from FIG. 7, urst has a digital value that changes in a very complicated manner.
The black burst signal generating circuit 20 itself that generates rst can be easily constructed by a combination of logic gates such as AND, OR, and NOT. That is, the digital synchronizing signal generating circuit 22 that generates the digital synchronizing signal S of the black burst signal Black Burst and the burst forming signal generating circuit 23 that generates the digital signals BI and 11 for forming the burst signal are each shifted as described above. Register 29.43 and logic circuit 30.44
As described above, the logic circuits 30 and 44 are constructed by a combination of a plurality of logic gates. Further, the delay elements 311 to 314 and 451 to 459 constituting the shift register 29.43 can also be formed by flip-flops made by combining a plurality of logic gates. Therefore, the digital synchronization signal generation circuit 22 and the burst forming signal generation circuit 23 can be formed by a combination of logic gates such as AND, OR, and NOT.

It is clear that the selector 24 can also be formed by a combination of a plurality of logic gates. That is, the selector 24 essentially outputs BI*Csc'+■1*Csc, and is therefore a logic circuit consisting of an AND circuit 66, 67, a NOT circuit (inverter) 68, and an OR circuit 69 as shown in FIG. It can be easily formed by providing eight according to the number of bits. This also applies to the selector 28.

Furthermore, the exclusive OR circuit 25 can also be formed by a combination of a plurality of logic gates without further explanation.

Moreover, since the pedestal level signal generation circuit 26 only needs to have a function of generating a 6-bit signal rllll100J with a digital value of 60+, for example, two grounded output terminals and an output terminal installed at the power supply voltage terminal are used. It can be constructed by providing four of them, and does not even require logic gates.

Since the adder circuit 27 can also be formed by providing the same number of adders as the number of bits, the adder circuit 27 can also be formed by a combination of logic gates.

Note that the signal Burs output from the exclusive OR circuit 25
Adding 60 to t is done by adding circuit 2 consisting of an adder.
This can be done without providing 7. That is, adding 60 to the 8-bit signal Burst means performing the following calculation on each bit from bit O' to bit 7.

Here, for convenience, B is assigned to each bit of the signal Burst.
Although it gives a code of O-87, it is a completely different signal from color signal B.

(1) ((B2+B3+B4+B5) ・B6) φB
7+ ((B2+B3+B4+B5)・B6) ・・Φ
Φ@ (bit 7) (2) (B2+B3+B4+B5) @B6+
(B2+B3+B4+B5) -B6- -
-...a (bit 6) (3) (B2+B3+B4)-B5+ (B2+
B3+B4) eB5e * * e *・
Φ・ (bit 5) (4) B2+83 dispute B4+ (B2+B3
) ・ B 4・−・ (Bit 4) (5) B2・D]+B2・B3 ・ (Bit 3) (
6) fr2'... (bit 2
)(7), Bl −@−・ (bit 1
) (8) BO... ｜ (bit 0) Each of the above-mentioned y4 calculations can be obtained by a logic circuit consisting of multiple basic logic gates such as AND, OR, NOT, etc. Therefore, this Such a logic circuit can be used in place of the adder circuit 27 and the pedestal level signal generating circuit 26.

Thus, the entire black burst signal generation circuit 20 can be constructed by a combination of basic logic gates of AND, OR, and NOT. Therefore, the black burst signal generation circuit 20 can be constructed from a commercially available programmable logic array (PLA) as shown in FIG. 10, for example. In a programmable logic array (PLA) like this, any logic circuit can be obtained by connecting appropriate intersections of a matrix made up of vertical and horizontal lines in FIG. 10, for example, by writing with a ROM writer. Therefore,
It is no longer necessary to design a special circuit to generate a black burst signal, and the price of the color video camera can be reduced. Of course 1. In order to obtain a black burst signal, the black burst signal is decomposed into multiple patterns of signals, information about each pattern of signals is stored in memory, and the information is read out in a predetermined order. things are no longer necessary,
Hence the memory for storing pattern signals.

Needless to say, a relatively complicated circuit such as a program control circuit for reading pattern signals in a predetermined order is not required.

As described above, the digital signal generation circuit of the present invention is composed of a shift register consisting of a plurality of delay elements that shift one control signal, and a plurality of logic gates such as AND, OR, and/or NOT. a logic circuit for forming a digital signal, each input terminal of the logic circuit is connected to an output terminal of one of the plurality of delay elements constituting the shift register, and the control signal controls the shift register. It is characterized in that the digital value of the digital output signal of a plurality of bits of the logic circuit changes as set in advance each time it is shifted one bit at a time, and therefore, it is controlled by a shift register. By shifting the signal, the digital value of the output signal of the logic circuit can be changed in a preset manner. Therefore, even digital signals whose digital values change in a very complex manner can be obtained using a simple circuit consisting of a shift register of several bits and a logic circuit formed by combining several logic gates. Can be done.

FIG. 11 shows the main part of another color video camera circuit to which the digital signal generating circuit of the present invention is applied. This color video camera circuit is designed to cause a delay in each digital signal input to the NTSC color encoder 19 such that the more significant the bit, the greater the amount of delay. This delay is caused so that the adder circuit within the NTSC color encoder 19 can be formed by low-speed logic elements.

That is, in digital color video camera circuits, including the color video camera circuits shown in FIGS. 2 to 5, very high-speed logic elements are generally used in addition circuits that add multiple bits of data, for example, 8 bits. For example, T
It is necessary to use TL or ECL. This is because when adding multiple bits of signals, the lowest bits are generally added together first, and after determining the presence or absence of a carry, the bits one higher than that are added together. After completing the addition, it is necessary to move on to addition of the upper bits, and it is not possible to add all bits at the same time. Of course, all bits can be added simultaneously by using an adder circuit with a carry lookahead circuit, but in this case, the carry lookahead circuit must be provided, which significantly increases the size of the adder circuit, and color video This is not preferable because it significantly restricts miniaturization of the camera circuit. Therefore, when using an adder circuit that performs addition in order from lower bits to upper bits, the addition of 8-bit data, for example, is performed in one period of a clock pulse having a frequency that is, for example, four times the frequency of the color subcarrier signal. It must be done inside. Therefore, the adder circuit needs to use high-speed logic elements such as TTL and ECL, which limits the ability to increase the integration and reduce the power consumption of the adder circuit. Therefore, the color video camera circuit shown in Fig. 11 operates at low speed as a logic element of the adder circuit.
This allows the use of CMO3, thereby achieving higher integration and lower power consumption.

In FIG. 11, 70, 71, 72 and 73 are delay circuits, and the delay circuit 70 is the NTSC color encoder 19.
The delay circuit 71 is provided in the transmission path of the chroma signal I input to the chroma signal I, and the delay circuit 71 is also provided in the transmission path of the chroma signal Q.
The delay circuit 72 is also provided on the transmission path of the luminance signal Y. The delay circuits 70, 71 and 72 are the twelfth delay circuits 70, 71 and 72, respectively.
As shown in the figure, it consists of a large number of delay elements 74 and 74 that delay the signal by one cycle of the clock pulse, and is configured so that the higher-order bits have a larger amount of delay. Specifically, bit 0 has a delay amount of O, bit 1 has a delay amount of one clock pulse period, bit 2 has a delay amount of two clock pulse periods, and so on. The period is set to correspond to one period of the clock pulse.

On the other hand, the delay circuit 73 connects the NTSC color encoder 19 and D
/A converter 21, and similarly to the delay circuits 70 to 72, a large number of delay elements 74, 74 . Consists of...

However, in this delay circuit 73, contrary to the delay circuits 70 to 72, the delay amount of the most significant bit is O, and the delay amount increases by one cycle of the clock pulse as the lower bits become lower.
The amount of delay for the least significant bit is seven times the period of the clock pulse.

In this way, the chroma signal, Q and luminance signals Y input to the NTSC color encoder 19 are transferred to the delay circuit 70.7.
1.72 is used to allow the NTSC color encoder to perform calculations at a processing speed of 1 bit per period of the clock pulse. That is, the chroma signal I
, Q, and luminance signal Y are input to the NTSC color encoder 19 via the delay circuits 70, 71, and 72, so that all the digital signals are input in one period of the clock pulse instead of all at the same time. NTS one bit at a time starting from the least significant bit at the same time interval.
It is input to the C color encoder 19. Therefore, the N.T.S.
It is sufficient that each bit section of the adder circuit in the C color encoder 19 can perform arithmetic processing for one bit within one cycle of the clock pulse. Therefore, NT3C
The calculation speed of the addition circuit in the color encoder 19 may be low. Therefore, C M 0.5, which is a low-speed logic element, can be used in the NTSC color encoder 19, and high integration and low power consumption can be achieved.

NTSC color encoder 19 and D/A controller-21
The delay circuit 73 inserted between the NTSC color encoder 19 and the NTSC color encoder 19 eliminates the above-mentioned delay between bits of the signal output from the NTSC color encoder 19. That is, as is clear from the above, the output signal of the NTSC color encoder 19 is output in order starting from the least significant bit, so the delay circuit 73 delays the least significant signal the most, and the higher the signal, the lower the delay. This allows all bits of one digital signal to be input to the D/A converter 21 at the same time. By the way, the black/hest signal Bla output from the black/hest signal generation circuit 20
ck Burst is Y+Qsin(ωc 5cet+33°)+I in the NTSC color encoder 19.
It is added to the signal E obtained by color encoding expressed as CO5 ((1)e 5c-t+33°).

Therefore, the black burst signal BLack Burs
t number also brightness signal Y, chroma signal 1. As with Q, a delay must be generated such that the more significant the bit, the greater the amount of delay. The black/<-st signal generating circuit 20a shown in FIG. 11 is designed to generate such a delayed black burst signal.

FIG. 14 shows a digital synchronizing signal generating circuit 22a of the black burst signal generating circuit 20a. The logic circuit 77 includes AND circuits 78-84 and OR circuits 85-
Consists of 89.

The least significant bit signal SO of the digital synchronization signal S output from this logic circuit 77 always maintains "0". Beep)l
The signal Sl is formed by AND circuits 78 and 79 and an OR circuit receiving their output signals. AND circuit 78 receives the inverted output signal d' of delay element 754 and also receives the output signal C' of delay element 753. AND circuit 7
9 receives the output signal b' of the delay element 752 and receives the inverted output signal a' of the delay element 751. Thus, the OR circuit 8 receives the output signals of the AND circuits 78 and 79.
The output signal Sl of No. 5 is d'*c'+b'·77. Bit 2 signal S2 is formed by AND circuits 80 and 81 and an OR circuit 86 that receives their output signals. AND circuit 80 receives inverted output signals b' and e' of delay elements 752 and 755, respectively, and AND circuit 81 receives the signals b' and e' as they are, respectively.

Therefore, the output signal S2 of the OR circuit 86 receiving the output signals of the AND circuits 80 and 81 is b'·e'+b'
'is. Signal S3 of bit 3 is transmitted through delay elements 763 and 7
The output Q of 64 is formed by the OR circuit 87 receiving J+c' and d', so it becomes C'+d'. Bit 4 signal S4 is formed by AND circuits 82-84 and an OR circuit 88 receiving the output signal therefrom. The AND circuit 82 receives the signal C' and inverts the signal d', and the AND circuit 83 receives the output signal f of the delay element 766.
' and receives an inverted output signal e' of delay element 755, and AND circuit 84 receives output signals d' and e' of delay elements 754 and 765. Thus, the OR circuit 88 receives the output signals of the AND circuits 82 to 84.
The signal S4 output from is c'*d'+f'*e'+d
It becomes '*e'. Further, the signal S5 of bit 5 is transmitted to the delay element 7.
The signal S5 is output from the OR circuit 89 which receives the output signals d' and e' of the output signals 54 and 755, so that S5 is d'+e'. In addition, the 4n signal S6 of bit 6 and the signal S7 of bit 7
is always kept at "0".

The signals SO to S7 of each bit of the signal S output from the digital synchronization signal generation circuit 20a are summarized as follows. Mouth 57=rOJ (always "O") S6=rOJ (always "0") S5=d'+e'54=c'*d'+e'*f'+d'ae'53=c'
Φd'52=b'se'+e'*b'51=d'*c'+a'*b' 5O=rOJ FIG. 15 shows the input signal of the digital synchronization signal generation circuit 20a, that is, the synchronization signal H/V- SYNC and signals 5o-37 of each bit of the output signal S. In the same figure, the broken lines indicate signals 30-37 that are required when the above-described delay between bits is not applied to the signal input to the NTSC color encoder 19 as in the embodiments shown in FIGS. 2 to 10. It is something.

In the embodiment shown in FIG. vjl1, it is necessary to cause the burst signal Burst to have a delay that varies depending on the bit, similarly to the digital synchronization signal S.
Therefore, although the burst forming signal generating circuit 23a is also designed to cause such a delay in the output signal, illustration and explanation of the circuit configuration will be omitted.

The digital synchronizing signal generating circuit 22, 22a and the burst forming signal generating circuit 23 described above are merely examples of the present invention, and various embodiments of the present invention can be considered.
The invention is not limited to what has been described above.

[Brief explanation of the drawing]

FIG. 1 is a time chart showing a part of a black burst signal, FIGS. 2 to 10 are for explaining an example of implementation of the digital signal generation circuit of the present invention, and FIG. 2 is a diagram showing the entire color video camera circuit. FIG. 3 is a block diagram showing a black burst signal generation circuit which forms part of the circuit shown in FIG. 2 and to which the present invention is applied, and FIG. 5 is a circuit diagram showing a burst forming signal generation circuit implemented by an uninvented digital signal generation circuit, and FIG. 6 is a circuit diagram showing the operation of the black burst signal generation circuit. Time chart for explanation, No. 7
The figure is a time chart showing the black burst signal output from the black burst signal generation circuit, Figure 8 is a time chart for explaining the principle of generating burst signals whose phases are opposite to each other, and Figure 9 is an example of a selector. FIG. 1O is a circuit diagram showing an example of a programmable logic array that can be used to implement the digital signal generation circuit of the present invention, and FIGS. 11 to 15 are circuit diagrams showing other implementations of the digital signal generation circuit of the present invention. For explaining an example, FIG. 11 is a block diagram showing the main parts of a video camera circuit, FIGS. 12 and 13 are block diagrams showing a delay circuit, and FIG. 14 is a digital signal generation circuit of the present invention. FIG. 15 is a circuit diagram showing a digital synchronizing signal generating circuit implemented by the digital synchronizing signal generating circuit, and FIG. 15 is a time chart showing changes in the signals of each bit of the digital signal generated from the digital synchronizing signal generating circuit. Explanation of symbols 22.22a, 23...Digital signal generation circuit, 2
9.43.76...Shift register, 30.44.7
7. Contention logic circuit, 31.45.75. ...Delay element, 32-38.46-51.55-62.78-8
4 fists...and circuit, 39~41.53.54.85~
89/Φ/OR circuit, 52...NOT circuit Patent applicant Sony Corporation Tower I diagram (Tacycle) Procedural amendment (voluntary) April 30, 1981 Patent Application No. 101681 2, Title of the invention: Digital signal generation circuit 3, relationship with the person making the amendment Patent applicant's address: 6-7-35, Kitashina, Tokyo Parts Co., Ltd. Name (21
8) Sony Corporation 4, Agent 5, AI Masa's full text of the subject specification, drawing 6, and content of amendments (1) The entire text of the specification will be corrected as per the attached correction specification. (2) Insert the drawings 1, 5, 6, and 15 with the attached corrected drawings 1, 5, 6, and 15.
'-6・77＼7、Inventory of attached documents or attached objects (1) Amended statement 1 copy (2
) Corrected drawings (Fig. 1, Fig. 5, Fig. 6, and Fig. 15)
1 correction details
Document 10 Title of the Invention Digital Signal Generation Circuit 2, Claims (1) A shift register consisting of a plurality of delay elements that shift one control signal, and a plurality of logic gates such as RITO, AND, OR, and/or NOT. a logic circuit for digital signal formation, each input terminal of the logic circuit is connected to an output terminal of one of the plurality of delay elements constituting the shift register, and the control signal is A digital signal generating circuit (2) characterized in that the digital value of a plurality of bits of the digital output signal of the logic circuit changes as preset every time the shift register is shifted one bit at a time. ) The burst flag signal is shifted by a shift register as a control signal, and the logic circuit outputs two digital signals for forming a digital burst signal. Field of the Invention The present invention relates to a new digital signal generation circuit, and in particular, the present invention relates to a new digital signal generation circuit, and in particular, it is possible to generate a multi-bit digital signal whose digital value changes in a complex manner with an extremely simple circuit configuration. The present invention aims to provide a new digital signal generation circuit that can generate digital signals by using the following method. BACKGROUND ART With the development of digital signal processing technology, digital technology is becoming mainstream in various fields of electronic technology.For example, there is a tendency to process images in color video cameras using digital technology. By the way, when image processing is performed using digital technology, for example, it is inevitably necessary to generate various digital signals. Figure ff11 shows a part of the so-called black burst signal required in a color video camera, that is, a video signal consisting only of a synchronization signal without video information. It is clear that there is a need to generate digital signals that correspond to analog signals that vary in a complex manner. BACKGROUND OF THE INVENTION The following techniques are available for generating such digital signals, for example, black burst signals. This was filed by the applicant of the present application (Patent Application No. 197438 of 1981), and it is one black east (I3 is divided into multiple four
f, and information regarding each pattern is stored in a memory, and information regarding each pattern is read out in a predetermined order to obtain one black burst signal. This technology can also be applied to blank burst signals that have complex patterns; for example, when divided into time units of 1/2H (H; water/F period), signals with relatively few types of patterns are combined. According to this technology, a relatively small capacity memory is provided, information for each pattern signal is stored in each area of the memory, and the information for each pattern signal is stored in a certain order. By reading, it is possible to obtain a black burst signal and other digital signals whose digital values change in a complicated manner. However, providing a pattern signal storage memory and a program control circuit in a color video camera is not only necessary when forming them into an independent integrated circuit (IC), but also when an IC in which a color encoder circuit, etc. is formed. Even if it is formed in a large size, it becomes a factor that suppresses the miniaturization and price reduction of cameras.・Means for solving the problem Therefore, the present invention seeks to provide a novel digital signal generation circuit that can generate a multi-bit digital signal whose digital value changes in a complicated manner with an extremely simple circuit configuration. It consists of a shift register consisting of a plurality of delay elements that shift one control signal, and a logic circuit for forming a digital signal consisting of a plurality of logic gates such as AND, OR, and/or NOT. , each input terminal of the logic circuit is connected to an output terminal of one of the plurality of I-type elements constituting the shift register, and each time the control signal is shifted through the shift register by l bidat, the logic circuit It is characterized in that the digital value of the digital output signal of a plurality of bits of the circuit is changed in a preset manner. DESCRIPTION OF THE PREFERRED EMBODIMENTS Below, the digital signal generation circuit of the present invention will be explained in detail according to embodiments shown in the accompanying drawings. FIG. 2 is a block diagram showing the entire internal circuit of a color video canora using the digital signal generation circuit of the present invention as a section of a blank burst signal generation circuit, and l is a solid-state image sensor for obtaining the R signal component. , 2 is a solid-state image pickup device for obtaining the G signal component, and 3 is a solid-state image pickup device for obtaining the B signal component, and these are made of, for example, a CCD. The discrete output signals R, G, and B of the solid-state image sensor 1.2.3 are appropriately amplified by preamplifiers 4 and 5.6, and then processed in a sampling hold circuit 7.8.9 having both a sampling function and a waveform shaping function. Sampled A/
It is input to a D converter 10.11.12 where it is converted into a digital signal. The signals R1G and B converted into digital signals are subjected to signal processing such as γ correction, pedestal level adjustment, clamping, and clipping in process circuits 13, 14, and 15, and are input to the matrix 16. From the matrix 16, Y=0.3CIR+0.59G+0.11BI=0.
6OR-0, 28G-0, 32BQ=0.21R-0,
A luminance signal Y, chroma signals ■ and Q indicated by 52G-0 and 31B are output. Chroma signal ■
, Q are limited to a predetermined band by band limiting circuits 17 and 18, and then input to the NTSC color encoder 19 together with the luminance signal Y. The color encoder 19 is. E=Y+Qsin (ωcsc*t+33°)+Ico
s (ωcsca t+33°) (however, ωCS
C is the angular velocity of the color subcarrier signal) Color encoding is performed to obtain the signal E, and the black burst signal generation circuit 20 applies the color encoding to the signal E.
The desired bedscale level is given by adding the signals from
c and a burst signal Burst. Thus, the color encoder 19 outputs an NTSC composite signal, and this composite signal is converted into an analog signal in the D/A converter 2J. FIG. 3 is a block diagram showing the black burst signal generation circuit 20, in which 22 is a synchronization pulse number 744).
(Digital synchronization signal generation circuit that obtains an 8-bit digital synchronization pulse signal S from 7'V-3ync, 23 is a burst formation signal that receives the burst flag signal BurstFLag and generates two digital signals B1 and BQ for burst formation. This is a generation circuit whose digital signal BI is a burst signal Burst I having a predetermined level.
It has a digital value of the magnitude when the component is sampled, and the digital signal 1 is also the burst signal Burs.
It has a digital value of the magnitude when the mutual component of t is sampled. 24 is a digital signal B controlled by a switching circuit signal C5C' having a frequency 2fcsc which is twice the frequency fcsc of the color subcarrier signal C5c.
A switching circuit alternately outputs I and 1, and 25 is a digital signal B output from the switching circuit 24.
It is an exclusive OR circuit that receives I and BQ and color subcarrier signal CsC, and receives color subcarrier signal es
When c is "0", the output signal of the switching circuit 24 is sent out as is, and the color subcarrier signal C8c is "1".
At this time, it plays the role of inverting the output of the switching circuit 24 and sending it out. That is, the exclusive OR circuit 25 receives digital signals BI and BQ from the switching circuit 24 and outputs digital signals B1 . BQ, B1. When receiving subcarrier signal Csc to output digital signal B1. This is for inverting BQ by creating its complement. Note that eight exclusive OR circuits are provided corresponding to each bit of the diggle signal BI and the first base.
Each exclusive OR circuit receives a bit signal corresponding to one input terminal, and receives a color subcarrier signal Csc at the other input terminal. It was decided that circuit 25 would represent eight circuits. Note that digital signal B1. In order to invert BQ by creating its 2's complement, it is insufficient to invert each bit of the digital signals BT and BQ by the exclusive OR circuit 25, and it is necessary to further add l to the digital signal. However, in this embodiment, the output signal of the exclusive OR circuit 25 and the digital value "6" generated from the bedefthal level signal generation circuit 26 are used.
0'' beddeskle level signal.
The necessary addition of l is performed by applying the color subcarrier signal esc as a carry to the most significant hit portion of the signal. Here, the pedestal level signal with a digital value of "60" is added to the exclusive OR circuit 25 to the digital signals B and BQ, which are generated from the burst forming signal 23 and which are not given the level. This is to provide a pedestal level, but since the digital signal S to which the pedestal level has been applied is output in the digital synchronization signal generation circuit 22, it is unnecessary if 28 is used as an adder. 28 is a selector for forming a blank burst signal from the digital synchronization signal S and the burst signal Burst, and uses the difference between the generation time of the digital synchronization signal S and the generation time of the burst signal BursE to select an appropriate switching signal. The digital synchronization signal generation circuit 22 and addition circuit 27
Select the black/heist signal BLack alternately with
Burstfl type I#1° This is sent to the NTSC color encoder 19 in FIG. Figure 4 shows the blank burst signal generation circuit 20 of Figure 3.
FIG. 5 shows a signal generating circuit 23 for forming eight bursts. The present invention is applied to the forming signal generation circuit 23. First, the digital synchronization signal generation circuit 22 will be explained. This digital synchronization signal generation circuit 22 is comprised of a 4-bit shift register 29 for shifting the synchronization signal H/V-3ync input thereto, and a logic circuit 30 for forming a digital cycle symbol. 311 to 314 are delay elements constituting the shift register 29, and this shift register 29 has a frequency fC of the color subcarrier signal esc.
A signal with a frequency four times that of 5C generates a synchronizing signal H/V-Syn, one bit at a time, with the same period as this signal.
Shift c. The logic circuit 30 consists of seven AND circuits 32 to 38 and four OR circuits 39 to 42, and the i;l1il logic circuit 3
Signals 5o-37 of each bit of the 8-bit digital synchronization signal S outputted from 0 are outputted from output terminals TSO to TS7. Output terminal T that outputs the signal SO of (pi) O
SO is grounded and its signal SO is always kept at "0". 4 of bit 1 output from output terminal TSI.
'(No. S1 is formed by AND circuits 32, 33 and OR circuit 39. The AND circuit 32 receives the inverted output signal d of the delay element 1' 314 at one input terminal, and receives the inverted output signal d of the delay element 1' 314 at the other input terminal. The AND circuit 33 receives the output terminal C of the delay element 312 as it is, and sends the output signal C to one input terminal of the OR circuit 39. , receives the inverted output signal a of the delay element 31. at the other input terminal, and sends the output terminal boa to the other input terminal of the OR circuit 39.The signal S1 output from the OR circuit 39 is thus: co
It becomes d+aφb. Bit 2 signal S2 input from output terminal TS2
is formed by AND circuits 34, 35 and OR circuit 40. The AND circuit 34 receives the output signals a and d of the eight-fold elements 311 and 314, and sends the output signals and to the OR circuit 40.
The AND circuit 35 inverts and receives the signals a and d, respectively, and sends the output i-7 to the other input terminal ☆ and V4 of the OR circuit 40. 17, and No. 18 S2 output from the OR circuit 40 is aed
+a-7. No. 48 S3 of bit 3 output from output terminal TS3 and (No. M S5 of bit 5 output from output terminal TS5)
are delay elements 312. Since the OR circuit 41 receives the output signals S and C output from the AND circuits 313 and 313, the bit 4 signal S4 output from the output terminal T S-4, which becomes b+c, is generated by the AND circuits 36 to 38 and their output signals. The AND circuit 36 consists of an OR circuit 42 that receives
The AND circuit 37 receives the signal C inverted and receives the signal d as it is, and the AND circuit 38
Invert No. 14 and receive receiver -41-1'i4 a as is. Therefore, the signal S4 output from the OR circuit 42 becomes b.C+.tau..d+bsa. Moreover, both output terminals TS6 and TS7 are grounded,
Then output bit 6, No. 48 S6 and bit 7
The signal S7 always maintains "0". Therefore, the signals SO to S7 of each bit of the digital synchronization signal S output from the digital synchronization value generation circuit 22 shown in FIG. 4 are arranged as shown in r. 57=rO" (always 0) S6=rOJ (always 0) S5=b+c S4=a・b+dec+b*c S3=b+c S2=a-d+a*d S1=a@b+c*d so=ro", (always O ) Next, the burst forming signal generating circuit 23 shown in FIG. 5 will be explained. This 8-stret formation signal generation circuit 23 includes a 9-bit shift register 43, a logic circuit 44 that generates digital signals BI and IQ for burst formation,
Consisting of The shift register 43 consists of 9 (IIJ) delay elements 45. to 459, and receives the color subcarrier signal es.
burst flag signal B with the same period as this signal by a signal having a frequency four times the frequency fesc of c.
Shift urstFLag by 1 bit. The logic circuit 44 is a portion 44 that forms the digital signal BI.
I and a portion 44Q that forms the digital signal BQ, 44I is an AND circuit 46 to 51, an impark 52
and OR circuits 53 and 54, and the digital signal BI
The respective bi-soto signals BIO to BI7 are output from Tl0 to Tl7. The bit 0 signal BIO output from the output ☆iM-f-T I O is formed by the ant circuits 46, 47, 48 and the OR circuit 53. AND circuit 46 is delay element 4
The output signal i of the delay element 455 is received inverted and the output signal g of the delay element 455 is received as is.
is sent to the OR circuit 53. The AND circuit 47 receives the output signal g and inverts the output signal e of the delay element 451, and the AND circuit 48 receives the output signals e and i, respectively. Therefore, the signal BIO output from the OR circuit 53 receiving the output signals of the AND circuits 46 to 48 is i-g+g.
a e+e *i. Output terminals Tll and Tl3
The pin l-1 and bit 3 signals BII and BI3 output from the delay element 455 output signal g from the inverter 5.
2, it becomes No. 48 g, which is inverted. The bit 2 signal BI2 outputted from the output signal TI2 is formed by AND circuits 49 to 51 and an OR circuit 54 receiving these output signals. AND circuit 49 receives the output signal g of delay element 457 inverted and receives the output signal g of delay element 455 as is. The AND circuit 50 receives the signal g and inverts the output signal f of the delay element 453, and the AND circuit 51 receives the signals f and h, respectively. Therefore, the signal BI2 output from the OR circuit 54 receiving the output signals of the AND circuits 49 to 51 is h.f+f.g.
+g・h. In addition, the output terminals TI4 to TI7 are each grounded, and the signals BI4 of bits 4 to 7 outputted therefrom are grounded.
~BI7 are all always "0". Logic circuit 44Q includes AND circuits 55 to 62 and OR circuit 6
3 to 65, and output from the logic circuit 44Q.
Bit digital signal W[Each bit signal BQO~
BQ7 is output from output terminals TQO to TQ7. Bit 0 and bit 1 signals YQO and BQI output from output terminals TQO and TQl are formed by AND circuits 55 and 56 and an OR circuit 63 that receives output signals from these. The AND circuit 55 inverts the signal g and receives the signal f as it is. The AND circuit 56 receives the signal i and inverts the signal r. Therefore, the signals BQO and BQI output from the OR circuit 63 receiving the output signals of the AND circuits 55 and 56 are g·f
+h・i. Signal BQ2 output from output terminal TQ2 is formed by AND circuits 57 and 58 and an OR circuit 64 that receives this output signal. The AND circuit 57 receives the signal i inverted and receives the signal g as is. Also, AND circuit 5
8 receives the signal and receives the inverted output signal f. Therefore, the signal "isg+h" output from the OR circuit 64 which receives the output signals of the AND circuits 57 and 58 is
・It is f. Also, the signal B output from the output terminal TQ3
Q3 is formed by AND circuits 59 to 61 and an OR circuit 65 that receives their output signals. AND circuit 59
receives signal g inverted and receives signal g as is. Conversely, the AND circuit 60 receives the signal -g inverted and receives the signal -g as is. Further, the AND circuit 61 receives the signals f and i after inverting them. The OR circuit 65 receives the output signals from the AND circuits 59 to 61 and outputs the signals. Also, output terminal T
The signal "Silkworm i" output from Q4 is formed by the AND circuit 62 which inverts and receives the signals g and h, so it becomes g.h. Also, the output terminals TQ5 to TQ7 are grounded, and the output terminals are Signals BQ5 to BQ7 of bits 5 to 7
is always "0". Here, the burst forming signal generation circuit 23 shown in FIG.
A burst forming signal Bl is output from the burst forming signal Bl. BI7=rOJ (always 0) BI6=rOJ (always 0) BI5=rOJ (always 0) BI4=rOJ' (always 0) BI3=g BI2=f@h+f11g0gφh BIl=g B10=shig+e * g+e a 1BQ7 = r(
N (always 0) BQ6=r-OJ (always 0) BQ5=rO' (always O) Figure 3 below shows the Brayak burst signal generation circuit 20
The operation will be explained along the time chart shown in FIG. Shift register 29 of digital synchronization signal generation circuit 22
When the synchronization signal H/V-3ync is input to the delay element 31. which constitutes the shift register 29. ．． 312,3
A synchronizing signal S whose digital value changes in response to changes in the output signals a, b, C, and d of 13.314 is output from the logic circuit 30. The synchronization signal H/V-3ync is shown in Table 1 below.
, a, b, C, d and changes in the digital synchronization signal S. Table 1 Furthermore, when the burst flag signal Burstf Lag is input to the shift register 43 of the burst forming signal generation circuit 23, the output signals e and f of the shift register 43 are
, g, h, and i output signals are outputted from logic circuits 441 and 44Q. Burst Flag No. 46 BurstFLag is shown in Table 2 below.
, e, f, g, h, i, and changes in digital signals Bl and BQ for burst formation. Table 2 By the way, digital signal B1 for burst formation. BQ
is 2 of the frequency fcsc of the color subcarrier signal esc
Switching signal esc with double frequency 2fcsc
The selector 24 is controlled by the selector 24 . Therefore, the selector outputs the digital signal B1. for burst signal formation. BQ is output alternately. When the color subcarrier signal Csc is rl, the digital signals alternately output from this selector 24 are inverted and output as follows.
0'', the signal is directly input from the exclusive OR circuit 25 to the Kaga circuit 27. Therefore, the signals input to the Kaga circuit 27 are 1 page, BI, BQ, 100 I, BQ, BI, BQ,
The signal changes as follows: BI, ■, etc., forming the digital burst signal BursE. This digital value is 0
．． 0.0, l, -4, -5, 12, 10, -19, -1
4, 24, 15, -24, -15, 24, 15, -24
, -15...-24, -15,24,15,-24,
-15,24,14, -19, -1O112,5, -4
, -1, o, o, o, o---. This digital burst signal Burst is sent to the adder circuit 27.
60 is added to the signal from the petestal level signal generating circuit 26 and sent to the selector 28. The black burst signal Bur is sent to this selector 28.
A digital synchronizing signal S from the digital period A8 generation circuit 22 is also input together with st, and the black burst signal Black as shown in FIG.
Burst is output. Then, this black burst signal B'L IL Ck BurSt is the second
The signal is input to the NTSC color encoder 19 shown in the figure. Note that 1, Q, D, Q written in the portion showing signals Csc' and C5c in FIG. 6 are B1. BQ,B
It indicates I and BQ, and B is simply omitted for convenience. Further, although FIG. 7 particularly shows a portion of the black burst signal corresponding to the horizontal synchronizing signal Hsync and a portion following it, the portion corresponding to the vertical synchronizing signal Vsync also has a predetermined pattern. As shown in FIG. 8, the subcarrier signal esc(a) in one horizontal scanning period and the subcarrier signal esc(b) in the next horizontal scanning period are reversed in phase, so it is inevitable that As shown in FIG. 7, the burst signal Burst(a) in one horizontal scanning period and the burst signal Burst(b) in the next horizontal scanning period are shown in FIG.
) (indicated by the dashed line) What is the phase relationship between the two? 7- It can be reversed! Ru. As described above, the black burst signal BlackBurst can be generated by the black burst signal generation circuit 20. By the way, the black burst signal BLack B
As is clear from FIG. 7, urst is a black burst signal whose digital value changes in a very complicated manner.
The black burst signal generating circuit 2o itself that generates st can be constructed in a cylinder by a combination of logic gates such as AND, OR, and NOT. That is, the digital synchronizing signal generating circuit 22 that generates the digital synchronizing signal S of the black burst signal Black Burst and the burst forming signal generating circuit 23 that generates the digital signals BI and ROCK for forming the /HAST signal are as described above. It consists of a shift register 29.43 and a logic circuit 30.44, and as described above, the logic circuits 30 and 44 are constructed by a combination of a plurality of logic gates. Also, the delay element 31 constituting the shift register 29.43
1 to 314 and 451 to 459 can also be formed by flip-flops that are a combination of a plurality of logic gates. Therefore, the digital synchronizing signal generating circuit 22 and the burst forming signal generating circuit 23 can be formed by a combination of logic gates such as AND, OR, and NOT. It is clear that the selector 24 can also be formed by a combination of a plurality of logic gates. That is, the selector 24 essentially outputs BI・Csc'+BQeCsc', and therefore, as shown in FIG. It can be easily formed by providing eight pieces depending on the situation. This also applies to the selector 28. Furthermore, the exclusive OR circuit 25 can also be formed by a combination of a plurality of logic gates without further explanation. In addition, since the pedestal level signal generation circuit 26 only needs to have a function of generating a 6-bit signal rl 11100 with a digital value of 60, for example, two grounded output terminals may be installed at the power supply voltage terminal. It can be constructed by providing four output terminals, and does not even require logic gates. Since the adder circuit 27 can also be formed by providing the same number of adders as the number of bits, the adder circuit 27 can also be formed by a combination of logic gates. Thus, the entire black burst signal generation circuit 20 can be constructed by a combination of basic logic gates of AND, OR, and NOT. Therefore, the black burst signal generating circuit 2.degree. can be constructed from a commercially available programmable logic array (PLA) as shown in FIG. 1O, for example. That is, in such a programmable logic array (PLA), an arbitrary logic circuit can be obtained by connecting appropriate intersection points of a matrix made up of vertical and horizontal lines in FIG. 10 by writing with a ROM writer, for example. Therefore,
It is no longer necessary to design a special circuit to generate a black burst signal, and the price of the color video camera can be reduced. Of course, in order to obtain a black burst signal, it is necessary to decompose the black burst signal into multiple pattern signals, store information regarding each pattern signal in memory, and read out the information in a predetermined order. Needless to say, relatively complicated circuits such as a memory for storing pattern signals and a program control circuit for reading pattern signals in a predetermined order are no longer required. As described above, the digital signal generation circuit of the present invention is composed of a shift register consisting of a plurality of delay elements that shift one control signal, and a plurality of logic gates such as AND, OR, and/or NOT. a logic circuit for forming a digital signal, each input terminal of the logic circuit is connected to an output terminal of one of the plurality of delay elements constituting the shift register, and the control signal controls the shift register. It is characterized in that the digital value of the digital output signal of a plurality of bits of the logic circuit changes as set in advance each time it is shifted one bit at a time, and therefore, it is controlled by a shift register. By shifting the signal, the digital value of the output of the logic circuit (g) can be changed as preset. Therefore, even if the digital signal whose digital value changes in a very complicated manner can be converted into a shift register of several bits. and a logic circuit formed by combining several logic gates. Fig. 11 shows another color video camera circuit to which the digital signal generation circuit of the present invention is applied. This color video camera circuit is designed to cause a delay in each digital signal input to the NTSC color encoder 19 such that the higher the bit, the greater the delay amount. This delay is caused by the fact that the adder circuit in the NTSC color encoder 19 can be formed by low-speed logic elements. In digital color video camera circuits, an adder circuit that adds multiple bits of data, such as 8-bit data, generally uses a very high-speed logic element such as TT.
It is necessary to use L or ECL. This is because when adding multiple bits of signals, the lowest bits are generally added together first, and the presence or absence of a carry is determined, and then the bits one higher than that are added together. After completing the addition, it is necessary to move on to addition of the upper bits, and it is not possible to add all bits at the same time. Of course, if you use an adder circuit with a carry-lookahead circuit, you can add all bits at the same time, but in this case, you have to provide a carry-lookahead circuit, which makes the adder circuit significantly larger, and color This is undesirable because it severely limits the miniaturization of the video camera circuit. Therefore, when using an adder circuit that performs addition from the lower bit to the upper bit, for example, the 8th bit data is added to the color subcarrier. This must be done within one period of a clock pulse having a frequency that is, for example, four times the frequency of the signal. Therefore, the adder circuit needs to use high-speed logic elements such as TTL and ECL, which limits the ability to increase the integration and reduce the power consumption of the adder circuit. Therefore, the color video camera circuit shown in FIG. 11 uses a low-speed operating CMOS as the logic element of the adder circuit.
This enables high integration and low power consumption. 811, 70, 71, 72 and 73 are delay circuits, and the delay circuit 70 is the NTSC color encoder 1.
The delay circuit 71 is also provided on the transmission path of the chroma signal Q, and the delay circuit 72 is provided on the transmission path of the luminance value 4y. The delay circuits 70, 71 and 72 are the first
As shown in FIG. 2, it is composed of a large number of delay elements 74 and 74 that delay the value signal by one period of the clock pulse, and is configured such that the upper bit has a larger delay amount. Specifically, bit 0 has a delay amount of O, bit l has a delay amount of one clock pulse period, and pint 2 has a delay amount of two clock pulse periods. The delay amount increases by one cycle of the clock pulse as the bit becomes more significant. On the other hand, the delay circuit 73 is inserted between the NTSC color encoder 19 and the D/A converter 21, and similarly to the delay circuits 70 to 72, it has a large number of delays that delay the value signal by one period of the clock pulse. Element 74. Consists of 74, . However, in this delay circuit 73, contrary to the delay circuits 70 to 72, the delay amount of the lowest bit is 0, and the delay amount increases by one cycle of the clock pulse as the lower bits become lower bits. The amount of delay is seven times the period of the clock pulse. In this way, the chroma signal generator, Q, and luminance signal Y input manually to the NTSC color encoder 19 are transmitted to the delay circuit 70.7.
1.72 is used to allow the NTSC color encoder to perform calculations at a processing speed of 1 bit per period of the clock pulse. That is, chroma signal 1
．． Since the Q and luminance signals Y are input to the NTSC color encoder 19 via delay circuits 70, 71 and 72, all bits of each of the above digital signals are not transmitted simultaneously but at a time interval equal to one cycle of the clock pulse. Then, the bits are sequentially input to the NTSC color encoder 19 starting from the least significant bit. Therefore, it is sufficient that each bit section of the adder circuit in the NTSC color encoder 19 can perform arithmetic processing for l bits within one cycle of the clock pulse. Therefore, the calculation speed of the addition circuit in the NTSC color encoder 19 may be low. Therefore, the low-speed logic element 0MO5 can be used in the NTSC color encoder 19, and high integration and low power consumption can be achieved6.・In particular, the relationship is not limited to one focus, and there are various cases possible. A delay circuit 73 interposed between the NTSC color encoder 19 and the D/A comparator 21 eliminates the above-described delay between bits of the signal output from the NTSC color encoder 19. That is, as is clear from the above, since the output signal of the NTSC color encoder 19 is output in order from the least significant bit, the delay circuit 7
3, the lowest signal is delayed the most, and the higher the bits, the smaller the amount of delay, so that all bits of one digital signal are input to the D/A converter 21 at the same time. By the way, the black part 7 signal Bl output from the blackverse I/4A generation circuit 20
ack Burst is NTSC color encoder 19
Y+Qsin(ωc sc*t+33°)+
It is added to the signal E obtained by color encoding represented by IC05 (ωcsCItt+33°). Therefore, the black burst signal Black Burst
Also # degree A,) No. Y, chroma signal 1. 1 just like Q
The blank burst signal generating circuit 20a shown in FIG. 11, which must generate a delay such that the amount of delay becomes larger for the 6th bit, is designed to generate a black burst signal with such a delay. FIG. 14 shows the digital synchronization signal generation circuit 22a of the black burst signal generation circuit 20a, and the difference in delay amount depending on bits as shown in FIGS. 12 and 13 is 1 delay amount per 2 bits. This is the case for ratios. This circuit 22a includes a 6-bin shift register 76 made up of delay elements 751-756, and a logic circuit 77 made up of AND circuits 78-84 and OR circuits 85-89. The least significant bit signal SO of the digital synchronization signal S output from this logic circuit 77 always maintains "0". bit l
The signal Sl is formed by AND circuits 78 and 79 and an OR circuit 85 receiving their output signals. AND circuit 7
8 receives the inverted output signal d' of the delay element 754, and also receives the output signal C' of the delay element 753. AND circuit 79 receives output signal b' of delay element 752 and inverts output signal a' of delay element 751. Therefore, the output signal S1 of the OR circuit 85 receiving the output signals of the AND circuits 78 and 79 is d'·C'+b'-a'. Bit 2 signal S2 is formed by AND circuits 80 and 81 and an OR circuit 86 that receives their output signals. AND circuit 80 receives inverted output signals b' and e' of delay elements 752 and 755, respectively, and AND circuit 81 receives the signals b' and e' as they are, respectively. Therefore, the output signal S2 of the OR circuit 86 which receives the output signals of the AND circuits 80 and 81 is b'·e'+b'
・It is e′. Signal S3 of bit 3 is sent to OR circuit 87 which receives output signals C' and d' of delay elements 763 and 764.
It is formed by c'+d'. bit 4
The signal S4 is formed by AND circuits 82-84 and an OR circuit 88 receiving the output signal therefrom. The AND circuit 82 receives the signal C' and inverts the signal d', and the AND circuit 83 receives the output signal f' of the delay element 766 and receives the inverted output signal e' of the delay element 755. The circuit 84 includes delay elements 754'' and 7
65 output signals d' and e' are received. Therefore, the signal S4 output from the OR circuit 88 receiving the output signals of the AND circuits 82 to 84 is c'*d'+f'*e'+d'e
becomes e'. Further, the signal S5 of bit 5 is transmitted to the delay element 754.
and an OR circuit 8 receiving output signals d' and e' of 755.
9 and therefore its 55 is d'+e'. Note that the signal S6 of bit 6 and the signal S7 of bit 7 are always kept at "0". The signals 30-37 of each bit of the signal S output from the digital synchronization signal generation circuit 20a are summarized as follows. 57=rOJ (always "0") S6=rOJ (always "0") 55=d'+e'54=c'sd'+e'++f'+d' *
e'53=c'+d'52=b'e'+e'eb'51=d'・C'+a'*b'5O=rO'' FIG. , a synchronizing signal H/V-3sync, and signals SO to S7 of each bit of the output signal S. In the same figure, the broken line indicates N as in the embodiments shown in FIGS. 2 to 8.
This shows signals 5o-57 that are required when the above-described inter-bit delay is not applied to the signal input to the TSC color encoder 19. In the embodiment shown in FIG. 11, it is necessary to cause the burst signal Burst to have a delay 111 that varies depending on the bits, similarly to the digital synchronization signal S. Therefore, the burst forming signal generation circuit 23a also outputs a signal. Although such a delay is caused, illustration and explanation of the circuit configuration will be omitted. The digital synchronizing signal generating circuit 22, 22a and the burst forming signal generating circuit 23 described above are merely examples of the present invention, and the present invention can be implemented in various ways.
The invention is not limited to what has been described above. 4. Brief description of the drawings FIG. 1 is a time chart showing a part of a black burst signal, and FIGS. 2 to 1O are for explaining an example of implementation of the digital signal generation circuit of the present invention. 3 is a block diagram showing the entire color video camera circuit, FIG. 3 is a block diagram showing a black burst signal generation circuit which forms part of the circuit shown in FIG. 2 and to which the present invention is applied, and FIG. A circuit diagram showing a digital synchronization signal generation circuit implemented with a digital signal generation circuit, FIG. 5 is a circuit diagram showing a burst forming signal generation circuit implemented with the digital signal generation circuit of the present invention, and FIG. 6 is a black circuit diagram. Time chart for explaining the operation of the burst signal generation circuit, No. 7
The figure is a time chart showing the black/crust signal output from the black burst signal generation circuit, Figure 8 is a time chart for explaining the principle of generating burst signals whose phases are opposite to each other, and Figure 9 is a time chart showing the selector. FIG. 10 is a circuit diagram showing an example of a programmable logic array that can be used to implement the digital signal generation circuit of the present invention, and FIGS. 11 is a block diagram showing the main parts of the video camera circuit, FIGS. 12 and 13 are block diagrams showing the delay circuit, and FIG. A circuit diagram showing a digital synchronization signal generation circuit formed by implementing the circuit,
FIG. 15 is a time chart showing changes in each bit of the digital signal generated from the digital synchronization signal generation circuit. Explanation of symbols 22.22a, 23... Digital signal generation circuit, 2
9.43.76...Shift register, 30.44.7
7.--Logic circuit, 31.45.75,...Delay element, 32-38, 46-51.55-62.78-84.
...AND circuit, 39-41.53.54.63-65
．． 85-89・@φoff circuit, 52・life・not circuit

Claims (1)

[Claims] (■) A plurality of delays for shifting one control signal; (a digital value composed of a shift register consisting of six elements and a plurality of logic gates such as AND, OR, knob and/or NOT); ), each input terminal of the logic circuit is connected to an output terminal of one of the plurality of delay elements constituting the soft register, and the control signal is connected to the shift register. A digital signal generating circuit (2) characterized in that the digital output of a plurality of bits of the logic circuit is shifted to 4+j by 1 pin, and the digital value of No. 1 changes as preset. ) The burst flag signal is shifted by a shift register as a control signal, and the logic circuit outputs two digital signals for forming a digital burst signal.
Digital signal generation circuit