JPS5989091A - Color camera device - Google Patents

Abstract

PURPOSE:To improve the system reliability with minaturization, conversion into a non-control circuit, etc., by having digital detecting parts for both video and color signals which constitute a video signal processor of a camera device. CONSTITUTION:An image pickup device 1 is controlled by a driving circuit 6, and output picture element signals 9 and 10 are converted into digital signals by an A/D converter 2. This signal 12 is applied to a digital video signal processor 3, and a digital video signal 13 is supplied to a standard color TV signal synthesizer 5. Furthermore the signal 12 is applied to a digital color signal processor 4, and the 1st and 2nd digital color difference signals 14 and 15 are sent to the synthesizer 5. These signals 13-15 are synthesized by the synthesizer 5, and a standard color TV signal s delivered.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to television studio cameras, industrial viewing cameras,
This relates to a color camera device that can be used as a camera for industrial robots, a camera for home video tape recorders, etc. 0 Conventional configurations and their problems In recent years, home video tape recorders have become rapidly popular. Anyway, I can do docking with this videotape recorder6.
Color cameras that are lightweight, compact, low-priced, and easy to operate are being developed.

However, conventionally, the signal processing section of a color camera has mostly adopted an analog signal processing method, but color camera devices using this analog signal processing method have the following problems.

(1) Since the analog electrical signal detected from the received light signal is processed, the signal-to-noise (S) ratio deteriorates in principle each time it passes through each signal processing block.

In order to correct this, various correction or adjustment circuits are required, resulting in a very complicated system configuration, which increases the performance fluctuations of the resulting product (color camera device). This is a contributing factor.

(2) In a commercially available color camera device that uses an image pickup tube as an imaging device, there are as many as 30 or more adjustment points during manufacturing, which increases the number of parts and results in high product costs.

(3) Current analog signal processing type color cameras always have signal processing filters and ultrasonic waves for one horizontal period (1H).
Delay lines and the like are required, but these are composed of L-C-R parts9, and it would be impossible to convert the entire analog signal processing section into a monolithic IC. In other words, there is a limit to the miniaturization of analog signal processing circuits.

(4) In color cameras using analog signal processing method,
Complex additional circuits are required to control white balance adjustment, gamma (gamma) correction, etc. in conjunction with a microcomputer. This also increases the cost of the product and complicates operation.

In summary, color camera devices that use current analog signal processing methods are highly reliable.

There are limits to the pursuit of lower prices, no-adjustment circuits, ultra-miniaturization of the entire two-circuit system that requires no adjustment, and easy imaging operability.

Purpose of the Invention The purpose of the present invention is to configure the signal processing section of a color camera device with a digital circuit, and to improve the reliability, lower cost, and eliminate adjustment of the color camera device, which had limitations with conventional analog signal processing methods. An object of the present invention is to provide a color camera device that is ultra-compact, lightweight, and allows easy imaging operation.

Structure of the Invention The color camera device of the present invention receives an optical signal and, during the horizontal readout scanning period, synchronizes with the readout clock frequency and performs a first scan consisting of repeating alternately different color signals for each pixel. a second pixel that outputs a pixel signal, is synchronized with the readout clock frequency in the next horizontal readout period, is different from the information of the first pixel signal, and is composed of repeating color signals that are alternately different for each pixel; an imaging device configured to output a signal; an analog-to-digital conversion device that converts first and second pixel signals output from the imaging device into digital signals; and an output from the AnaP-G digital conversion device. a digital color signal processing device that receives a digital pixel signal as an input and outputs independent first and second digital color difference signals; and a digital video signal processor that receives the digital pixel signal as an input and outputs a digital video signal. a standard color television signal combining device that receives the first and second digital color difference signals and the digital video signal and outputs a standard color television signal; a drive circuit device that drives the imaging device; The digital color signal processing device includes a control circuit device for generating timing pulses for driving an analog-to-digital conversion device, a digital video signal processing device, a digital color signal processing device, and a standard color television signal synthesis device; a white balance circuit, a digital one horizontal scanning period memory circuit, first and second digital color difference signal processing circuits, and a digital color difference signal switching circuit; a digital color difference signal processing circuit and the digital one horizontal scanning period memory circuit; an output signal of the digital one horizontal scanning period memory circuit is fed to the second digital color difference signal processing circuit; The output signal of the digital color difference signal processing circuit is applied to the digital color difference signal switching circuit, and the first and second digital color difference signals are obtained from the digital color difference signal switching circuit, and the analog-to-digital conversion A signal transmission path from the device to the first digital color difference signal processing circuit and the digital one horizontal scanning period memory circuit, and a signal transmission path from the digital color difference signal switching circuit to the standard color television signal synthesis device. The digital white balance circuit is inserted into one of the signal transmission paths, and thereby the color camera device can easily convert the signal processing section, which is essential to the basic configuration of the color camera device, to digital signal processing. It can be achieved.

DESCRIPTION OF EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of a color camera device according to the present invention. This includes a solid-state imaging device 1, an analog to digital (hereinafter abbreviated as A/D) conversion device,
A digital video signal processing device 3, a digital color signal processing device 4, a standard television signal combining device 6, a drive circuit device 6, and a control circuit device 7 are used.

The basic operation of the color camera device configured as described above will be explained below. The solid-state imaging device 1 that has received the optical signal 8 has a readout clock frequency f during a certain horizontal readout scanning period. The first pixel signal 9 consisting of repetitions of different color signals is outputted for each adjacent pixel in synchronization with the reading clock frequency f in the next horizontal readout scanning period. A second pixel signal 1o is output in synchronization with the information of the first pixel signal 9, which is composed of a repetition of color signals that are different from the information of the first pixel signal 9 and alternately different for each adjacent pixel.

The operation of the solid-state imaging device 1 as described above is performed by the drive circuit device e.
It is controlled by a control signal 11 from.

Said 1st. The second pixel signal 9.10 is an analog signal. The pixel signals 9 and 10 are converted from analog to digital by the A/D converter 2, resulting in a digital pixel signal 12.
becomes. The digital pixel signal 12 is applied to a digital video signal processing device 3, which converts the digital pixel signal 12 into a digital video signal 13.
becomes. Furthermore, the digital pixel signal 12 is applied to a digital color signal processing device 4, resulting in a first digital color difference signal 14 and a second digital color difference signal 16.

The digital video signal 13 and the first . The second digital color difference signal 14 , 15 is converted into a standard color television signal 16 by a standard color television signal synthesis device 6 . Two independent color difference signals and one video signal are essential elements for standard color television signal synthesis.

Note that the A/D conversion device and the digital video signal processing device 3. The digital color signal processing device 4 includes a drive circuit device 6
The standard color television signal synthesis device 6 is controlled by the control pulse signals 18, 19, 20 generated by the control circuit device 7, which operates in response to the control signal 17, and the control pulse signal 21 generated by the drive circuit device 6, respectively. It is configured so that

As described above, a completely new color camera device has been realized by digitizing the video signal and color signal detection sections, which are the main signal processing sections of the color camera device.

FIG. 2 is a block diagram of a color camera device according to an embodiment of the present invention, in which the digital color signal processing device 4
and the digital video signal processing device 3 are shown in more detail. In the figure, the digital color signal processing device 4 includes a digital white balance circuit 22 . It consists of a digital one horizontal scanning period (1H) memory circuit 23, a first digital color difference signal processing circuit 24, a second digital color difference signal processing circuit 26, and a digital color difference signal switching circuit 26. The digital pixel signal 12 A/D converted by the A/D converter 12 passes through the digital white balance circuit 22 to become a digital pixel signal 27 whose white balance has been corrected. This digital pixel signal 27 is transmitted during one digital horizontal scanning period (
1H) By passing through the memory circuit 23, the digital pixel signal 28 is delayed by one horizontal period. Therefore, the digital pixel signals 2 and 28 in a certain horizontal scanning period
When compared, if the digital pixel signal 27 is composed of the information of the first pixel signal 9, the digital pixel signal 28 is composed of more information than the second pixel signal 10. , the above relationship will be reversed in the next horizontal scanning period.

In this way, the two systems of digital pixel signals 27°28 are
This is essential for realizing independent first and second digital color difference signals 14.15. By passing through a first digital color difference signal processing circuit, the digital pixel signal 27 repeats the information of the first pixel signal 9 and the second pixel signal 10 for each horizontal scan. A digital color difference signal 29 is obtained. Similarly, the digital pixel signal 28 passes through the second digital color difference signal processing circuit 25, so that the information of the second pixel signal 10 and the first pixel signal 9 is repeated for every horizontal scan. The digital color difference signal 3o and the signal are delayed by one horizontal scanning period, probably due to the overall time relationship. For each horizontal scanning period, a digital color difference signal consisting of the first pixel signal 9 included in the digital color difference signal 29 and a digital color difference signal consisting of the first pixel signal 9 included in the digital color difference signal 3o, By selecting and switching with the digital color difference signal switching circuit 2θ, a first independent digital color difference signal 14 having the first pixel signal information 9 in all horizontal scanning periods can be generated.

Similarly, the digital color difference signal output from the second pixel signal 10 included in the digital color difference signal 29 and the second pixel signal 10 included in the digital color difference signal 30 are transferred to the digital color difference signal switching circuit. 2
By selecting and switching with o, a second independent digital color difference signal 16 having the second pixel signal information 10 in all horizontal scanning periods can be generated.

As described above, the digital white balance circuit 2
2. Digital 1 horizontal scanning period memory circuit 23. A digital color signal processing device 4 can be realized by the first and second digital color difference signal processing circuits 24 and 25 and the digital color difference signal switching circuit 26.

The digital video signal processing device 3 includes a digital video signal processing circuit 31 and a digital gamma (γ) correction circuit 32.
and a digital delay circuit 33. The digital pixel signal 27 is supplied to a digital video signal processing circuit 31 and becomes a digital video signal 34. It should also be noted that when improving the image quality of a video signal (monochrome image) in the vertical direction, the digital pixel signal 28 is supplied to the digital video signal processing circuit 31.

The digital pixel signal 34 is sent to the digital delay circuit 3.
By passing through the digital gamma correction circuit 32, the signal becomes a gamma-corrected video signal output, that is, the digital video signal 13. Note that the digital delay circuit 33 is configured to output the digital video signal 13 and the first . This is to correct the relative time delay between the second digital color difference signals 14, 15, and this time delay is the difference between the digital video signal 13 and the first . Second digital color difference signal 14.1
5 is generated when the digital pixel signal 27 is derived and passed through different time processing systems. Therefore,
It should be noted that in some cases, it may be necessary to use a delay circuit that delays the digital color difference signal 14.15. From this point of view, the delay circuit 33 is not included in the basic components of the digital video signal processing device 3.

As described above, the digital video signal processing circuit 31, the digital gamma correction circuit 32, and the digital delay circuit 33 constitute the digital video signal processing device 3. If it is improved and gamma correction is no longer necessary,
A digital video signal processing device 3 may be used in which the digital gamma correction circuit 32 is removed.

FIG. 3 is a block diagram of a color camera device according to another embodiment of the present invention, showing another example of the configuration of the digital color difference signal processing device 4. In FIG. Therefore, in FIG. 3, the configuration other than the internal configuration of the digital color difference signal processing device 4 is the same as the configuration example shown in FIG. 2.

In FIG. 3, the digital color difference signal processing device 4 includes a digital first horizontal scanning memory circuit 23, a first digital color difference signal processing circuit 24, a second digital color difference signal processing circuit 26, and a digital color difference signal switching circuit. 26 and a digital white balance circuit 40. The configuration differs from that of the digital color difference signal processing circuit 4 shown in FIG. 2 in that the digital white balance circuit 40 is placed next to the digital color difference signal switching circuit 26. Therefore, one digital horizontal scanning period memory circuit 23
The digital pixel signal 37, which is the output of The digital color difference signal 39 which is the output of the circuit 26 is combined with the digital color difference signal 30 and the first . Second digital color difference signal 4
2.43 are respectively the above-mentioned No. 1. A second digital signal 14.16 and basically "except that no white balance correction has been made."

It is clear that they each have the same signal configuration.

The first digital color difference signal 42 without white balance correction has the first pixel information 9 in all horizontal scanning periods, and the second digital color difference signal 42 without white balance correction has the first pixel information 9 in all horizontal scanning periods. 43 has the second pixel information 10 in all horizontal scanning periods. These first and second digital color difference signals 42.
43 passes through the digital white balance circuit 40,
Said 1st. The second digital color difference signal becomes 14.15.

As described above, the digital white balance circuit 4
It is possible to realize a digital color signal processing device 4 in which 0 is arranged at the next stage of the digital color difference signal switching circuit 26.

FIG. 4 is a schematic configuration diagram of main parts showing an example of a solid-state imaging device used in the color camera device of the present invention.

In this example, as an example of the light-receiving surface of the solid-state imaging device 1, an optical filter of magenta (goods), green (q), cyan (c'l), or yellow (7) is attached as shown in FIG. MOS (Metal Oxygen)
An array of pixels 44 to 79 consisting of photodiodes having a deSemiaonductor structure is presented. The arrangement of pixels 44 to Y9 in FIG. 4 is abbreviated and is actually a two-dimensional arrangement consisting of several hundred pixels in the horizontal direction and several hundred in the vertical direction. When a row of pixels 44 to 49 is selected by the control signal 11 from the drive circuit N6 at the start of one horizontal scanning period H1, magenta (hereinafter referred to as M
Pixels 44, 46, 48, etc. having signal information (hereinafter abbreviated as G) are transferred in parallel to a first horizontal readout CCP (charge capsid device) shift register 82, and a green (hereinafter abbreviated as G) signal Pixels 45, 47, 49, etc. that have information are read out in the second horizontal direction C.
The data are transferred in parallel to the OD shift register 83 and sequentially over the one horizontal scanning period H1.

Each signal is output from terminals 84 and 85 at a repetition period of 1/fc. At the start of the next horizontal scanning period H2, 9 pixels 6
Since rows o to 660 are selected, pixels 60, 62, 54, etc. having cyan (hereinafter abbreviated as C) signal information are stored in the first horizontal readout COD shift register 82.
Yellow (hereinafter abbreviated as Y) signal information etc. are transferred in parallel to the second horizontal reading COD shift register 83, and during this one horizontal scanning period H2
The signals are sequentially output from terminals 84 and 85 at a repetition period of 1/fo. Below, sequentially, for each horizontal scan,
Arrangement groups of pixels 66-611, pixels 62-67, pixels 68-732 and pixels 74-79 are repeated, and this repetition constitutes one field period. One frame period is
This one field period may be repeated, or the pixel column may be interlaced scanned every other row.

As is clear from the above explanation, a certain horizontal scanning period H4
, the M signal information is output to the terminal 84 and the C signal information is output to the terminal 86. In the next horizontal scanning period H2, the C signal information is output to the terminal 84.
C signal information is outputted to the terminal 86, and these are alternately repeated every horizontal scanning period to realize the functions of the solid-state imaging device 10. Still, the output mode of the first horizontal readout COD shift register 82 and the output mode of the second horizontal readout COD shift register 83 are maintained in an antiphase relationship within the repetition period 1/fc. . In this way, it is possible to realize the alternating repetition of M signal information and C signal information, and the alternating repetition of C signal information and Y signal information.In one horizontal period H1, M,
A first pixel signal 9 consisting of repetitions of different color signals alternately G, M, G, −° −° is obtained, and the next 91 horizontal periods H
2, No. 10 is obtained in the second one-plane element 4 consisting of repeating different color signals alternately as C1Y, C, Y, . . . .

FIG. 6 shows the output terminal 84 of the solid-state imaging device 1 shown in FIG.
A portion of the first horizontal scanning period H1 with the first pixel signal 9 outputted, and the second pixel signal outputted from the output terminal 86.
Output waveforms of analog discrete values each showing an enlarged portion of one horizontal scanning period rtU H2 of the pixel signal 10 of
This figure shows the operating waveforms of the A/D converter 2 which performs analog-to-digital conversion on these pixel signals 9°1o and generates digital pixel signals 12a and 12b.

FIGS. 6(-) and 6(b) show two different embodiments of the A/D converter 2. FIG. Below, Figure 6 and 6
A specific configuration example and operation of the A/D conversion device will be described with reference to the drawings.

In the case of the solid-state imaging device 1 shown in FIG. 4, since it has two output terminals 84 and 85, it is necessary to combine these two systems of pixel signals 9 and 10 into one system.

Therefore, as an example of the configuration of an A/D converter, the one shown in FIG. 6 (
-) and the one shown in Fig. 6('b).

First, in FIG. 6 (-), the A/D converter 2 is.

It consists of an A/D conversion circuit 96 and a two-manufacturer, one-output type analog switch circuit 95. Since the solid-state imaging device B1 outputs the first pixel signal 9 within one horizontal scanning period H1,
9M signal information columns 86a to 869 appear on the terminal 84,
A column 87 of C signal information with a 180° phase shift at the terminal 86
a to 87e appear. Timing period 9 shown in FIG.
At 8a to 98e, if the pulse train 91 is applied to the terminal 93 and the analog switch circuit 95 is made conductive to the terminal 84 side, the Mig number information sequences 86a to 86e are input as the conversion input to the A/D transformation circuit 96. If the pulse train 9o is added to the conversion timing pulse input terminal 97 of the A/D conversion circuit 96 at the same time, the timing period 98a-98e (
i.e. within 1/fo).

The M signal information strings 86a to 88s are A/D converted.

Next, during timing periods 99a-99e, pulse train 92 is applied to terminal 94, and analog switch circuit 96
If conductive to the fill of the terminal 86, the A/D conversion circuit 9
If a pulse train 90 is simultaneously applied to the conversion timing pulse input terminal 97 of the A/D conversion circuit 96, the C signal information will be converted within the timing period 99a to 99e. Column 87a-
87e is A/D converted.

In this way, within one horizontal scanning period H1,
The analog switch circuit 96 has a repetition period of 2/f.
c, the A/D conversion circuit is opened and closed so as to alternately conduct one of the two input terminals 93 and 94, and at a repetition period 1/fo that is % times synchronized with this opening and closing period. 96, the 9M signal information strings 86a to 86e and the C signal information strings 87a to 87e can be time-series synthesized and analog-to-digital converted at the same time.
A digital pixel signal 12a is output to an output terminal 100a of the D conversion circuit 96.

Within the next horizontal scanning period H2, the solid-state imaging device 1
Since the pixel signal 10 of
The signal information strings 89a to 89e are synthesized in time series to create an analog signal.
Can be converted digitally.

A digital polishing signal 12b is output to the digital output terminal 100a.

In addition, in FIG. 6, signals 101, 102°, 103.
104 are respectively digitized M signal, C signal,
Assume that the signals represent C and Y signals.

As described above, the analog switch circuit 96 and the digital conversion circuit 96 can realize the A/D conversion device 1-2. Further, the control pulse signal 18a of the A/D converter @2 shown in FIGS. 1 to 3 corresponds to the pulse train 90 in the above embodiment.

In FIG. 6(b) which is a second embodiment, the A/D converter 2 includes a first A/D converter circuit 104 and a second A/D converter circuit 104.
Conversion circuit 106. First digital latch circuit 106.
The output terminal of the first A/D conversion circuit 104 is connected to the first digital latch circuit 106, and the output terminal of the second A/D conversion circuit 106 is connected to the second digital latch circuit 107. The output terminals of the first and second digital latch circuits 1o6゜107 are connected in common to the latch circuit 107, and the operation timing of the first A/D conversion circuit 104 and the first digital latch circuit 106 is connected to the latch circuit 107. The operation timings of the second A/D conversion circuit 106 and the second digital latch circuit 107 are configured to be opposite to each other.

The operation will be explained below. Within one horizontal scanning period H1, the solid-state imaging device 1 outputs the pixel signal 9, so the M signal information columns 86a to 86e appear at the terminal 84, and the C signal information with a 180° phase shift appears at the terminal 86. row 8
7a to 87e appear. Timing period 98a-98
At e, when the pulse train 91 is applied to the terminal 108,
M signal information columns 86a to 86e are A/D conversion circuits 10
Analog → digital conversion is performed at 4, timing period 9
Minute time td from 8a to 98e (however, 1/fo>>
td), the first digital latch circuit 106
The signal is latched up and output to the digital output terminal 100b. At this time, there is a second one.

Next, in the timing period 99a to 99e, when the pulse train 92 is applied to the terminal 109, the C signal information train 87a
-87e is converted from analog to digital by the A/D conversion circuit 105, and after being delayed by a minute time (td) from the timing period 99a to 99e, the second digital latch circuit 10
7 and is output to the digital output terminal 1oob.

At this time, the output of the first digital latch circuit 106 is open. In this way, the outputs of the first digital latch circuit '#51o6 and the second digital latch circuit 107 are connected in common, and the outputs of the first digital latch circuit '#51o6 and the second digital latch circuit 107 are connected together.
08 and the second digital linear force, the M signal information columns 86a to 86e and the C signal information columns 87a to 87e, which are the constituent elements of the pixel signal 9, can be synthesized in time series and converted from analog to digital. Said 1st. The common output terminal of the second digital latch circuits 106 and 107
During the horizontal scanning period H2, the solid-state imaging device 1 outputs the second pixel signal 10, and if the same operating principle as described above is applied to this, the C signal information strings 88a to 88e and the Y signal information strings 89a to 89e are output. can be time-series synthesized and converted from analog to digital, and a digital pixel signal 12b can be output to the digital output terminal 1oob.

As described above, the functions of the A/D conversion device 2 can be realized by the two A/D conversion circuits and the two digital latch circuits. In the above embodiment, the pulse train 91 and the pulse train 92 correspond to the A/D converter 20 control pulse signal 18 shown in FIGS. 1 to 3.

To summarize the advantages and disadvantages of the two embodiments shown in FIGS. 6(a) and (b), in the embodiment shown in FIGS. 6(,),
Only one A/D conversion circuit is required, but the A/D conversion cycle is 1/1.
It is fc. On the other hand, in the embodiment shown in FIG. 6(b), the A/D
Two conversion circuits are required, but the conversion period is twice 2/f.
c, and can be implemented using an A/D conversion circuit with half the conversion speed as compared to the embodiment shown in FIG. 6(,).

Here, if fc=14.4 horses is selected, the conversion speed of the A/D converter is 7.211 in the embodiment shown in FIG. 6(b).
Furthermore, if fo=7.2Hb is selected, the conversion speed becomes 3.5811. Effectively reducing the conversion speed of A/D conversion circuits is a very important issue from the viewpoint of reducing power consumption of color camera devices and integrating A/D conversion circuits and signal processing circuits. In this sense, the embodiment shown in FIG. 6 is considered to be particularly effective.

FIG. 7 shows a block configuration diagram of the digital color difference signal processing circuit 24, 25, FIG. 8 is a specific circuit configuration diagram of the main part thereof, and FIG. 9 is a diagram for explaining the operation of the embodiment. This figure shows a time chart of signals and an example of the configuration of input/output digital data.

The configuration and operation of the digital color difference signal processing circuits 24 and 25 will be described below with reference to FIGS. 7, 8, and 9.

In FIG. 7, the digital color difference signal processing circuit 24.2
5 is a 1-pixel shift circuit 110 and a 1-pixel inversion circuit 11
1, the input signal 113 from the digital addition circuit 112, the input signal 113 of the 1 pixel shift circuit 110, and the 1 pixel inversion circuit 111.
The output signal 116 is applied to the digital adder circuit 112. The purpose of operation of the digital color difference signal processing circuits 24 and 25 is as follows: - When using the solid-state imaging device 1 shown in FIG.
, M, G, ... or c, y, c, y.

...) digital pixel signals 12, 27 consisting of
゜28 or 37 is the human input signal 113, and the color difference signal time series (MG, MG, MG,... or C-Y, C-Y, C-Y... ) is converted into a digital color difference signal 29, 30, 38 or 39 and output.

The one-pixel shift circuit 110 discriminates between the digital M signal and the digital C signal, and shifts only the digital C signal by one pit time. In this way, the shifted digital C signal is inverted by the 9th one-pixel inverting circuit 111 to become a digital-G signal. When the digital M signal and the digital -G signal are added to the digital adder circuit 112, the M
-G.

It can be converted into a digital color difference signal consisting of M-G... If the digital M signal is regarded as a digital C signal and the digital C signal is regarded as a digital Y signal, digital color difference signals consisting of cy, cy, cy, . . . can be similarly obtained. Also, the relationship between the digital M signal and the digital C signal or the relationship between the digital C signal and the Y signal is reversed, and G-M, G-M...
. . . or Y-C, Y-C, . . . It is of course possible to use a digital color difference signal. The digital color difference signal processing circuits 24 and 25 can be configured as described above.

In FIG. 8, the one-pixel shift circuit 110 includes a first digital latch circuit 117. Second digital latch circuit 118. Third digital latch circuit 119 and D
The one-pixel inversion circuit 111 is composed of a flip 70 tube circuit 120, and the one-pixel inversion circuit 111 is not a digital inverter circuit 121.A digital pixel signal 12, 27, 28 or 38 is applied to the input section of the first digital latch circuit 117, and the repetition period is 1/fc, and this latch-up output is selectively distributed to the second and third digital latch circuits 118 and 119 according to the timing of the D flip-flop, and the third latch circuit 119 is applied to a digital inverter circuit 121, and the output of the digital inverter circuit 121 and the output of the second digital latch circuit 118 are applied to a digital adder circuit 112.

Next, the operation of the circuit shown in FIG. 8 will be explained in detail with reference to FIG. 9. Digital pixel signals 12δ, that is, M and G in one horizontal scanning period H1.

A digital pixel signal consisting of M, G,...
A pulse train 12 with a repetition period of 1/fo is applied to the input part of the first digital latch circuit 117 and is applied to the terminal 122.
3, the output section of the first digital latch circuit 117 has a repetition period of 1/f.

The digital M signal information 1o1. Digital G signal information 102. Digital M signal information... is launched. At the same time, the D7 lip-flop circuit 12
A pulse train 126 is generated at the Q output terminal of 0, and a pulse train 127 is generated at the Q output terminal. The pulse train 126 connects the second digital latch-up circuit 118 at the timing 12 indicated by the arrow.
8a to 128e, it is possible to selectively latch up only this digital latch-up digital M signal information 130.

On the other hand, since the pulse train 12 latches up the third digital latch-up circuit 119 at the timings 129a to 129d indicated by the arrows, the digital G signal information 131 of this latch can be selectively latched up. Furthermore, digital M signal information 130 and digital G signal information 13
1 has a relative phase shift of 1/fo corresponding to one pixel period. This is a one-pixel shift operation. The digital G signal information 131 is latch-up outputted to the third digital latch-up circuit 119, and is inverted by the digital inverter circuit 121 to generate the digital-G signal information.
The signal information 132 is output. When the digital M signal information 130 and the digital-G signal information 132 are added in the digital adder circuit 112 in this way, a digital color difference signal output 116 consisting of a (MG) pulse train is obtained at its output section. This output signal 116 corresponds to the digital color difference signal 29, 30, 38 or 39. Similarly, the input signals 113 of the first digital latch circuit 117 are c, y, c.

By adding the digital pixel signal 12b consisting of Y..., a digital color difference signal output consisting of a (cy) pulse train can be obtained at the output section of the digital addition circuit 112. In FIG. 8, a pulse train 123 with a repetition period of 1/fo is applied to the terminal 122, and a pulse train 123 is applied to the terminal 113 repeatedly in one horizontal scanning period to reset the entire digital color difference signal processing circuit system of FIG. The returned synchronization pulse train corresponds to the control pulse signals 20b and 20c shown in FIGS. 1-3. Also, the first
゜Second. In the third digital latch circuits 117, 118 and 119, the signal CK indicates a clock input terminal for controlling latch-up. Furthermore, in FIG. 8, the digital inverter circuit 121 and the digital adder circuit 11
2 can be regarded as one digital subtraction circuit.

FIG. 1o shows an example of the configuration of the memory circuit 23 for one digital horizontal scanning period, and FIG. 11 shows a time chart and input/output digital data for explaining its operation. The structure and operation of the digital one horizontal scanning period memory circuit 23 will be described below with reference to FIGS. 10 and 11.

In FIG. 10, the digital 1 horizontal scanning period memory circuit 23 includes a second digital latch circuit 134 and a third digital latch circuit 134.
It consists of a digital latch circuit 136, a random access memory circuit 136, an address counter circuit 137, and a timing pulse generation circuit 144. Furthermore, in this embodiment, the timing pulse generation circuit 144 includes two D
The circuit includes flip-flop circuits 138 and 139 and four NOR circuits 140 to 143. The first digital latch circuit 146 and the fourth digital latch circuit 146 are connected to the memory circuit 2 for one horizontal scanning period, respectively.
This is the input/output interface circuit of No. 3. In addition,
In the following explanation, digital pixel signals are treated as parallel input/output data.

In Figure 1Q, the repetition frequency is 2f at terminal 147.
o timing clock pulse is applied to terminal 148.
The D flip-flop circuits 138 and 139 and the address counter circuit 13 are activated every horizontal period (1H).
When a synchronization pulse is applied to reset 7, the Q i'Q child of the first D flip-flop circuit 138 receives a timing 162 at which the repetition period is reset to 1H.
Starting from a, a pulse train 163 with an mO return period of 1/fc is generated, and the pulse train 163 with the mO return period of 1/fc is generated. , a pulse train 164 with a repetition period of 1/fo is generated, and is applied to the Qil terminal of the second D flip-flop circuit 139 with a repetition period of 1/fo.
A pulse train 166 with a repetition period of 1/f is generated starting from timing 162c reset at H. Further, the pulse train 163 and the pulse train 155 are connected to NOR circuits 142 and 143 via terminals 149 and 150.
When passed, a write control pulse train 167 for the random access memory circuit 136 is generated at the terminal 166.

Next, the above pulse trains 153, 154 and pulse train 1
Writing and reading to and from the random access memory circuit 136 will be explained using 67. Timing 162a, I
Pal at E52b, 162d, <column 153° 154.15
7 is reset, and at the same time, address counter circuit 137 is also reset via terminal 148. At timing 168a, the address counter circuit 137 receives the first valid address data 169 by the pulse train 163.
Set a. This address data 169a is applied to the addressing circuit of the random access memory circuit 136 via the parallel data boat 16o, so that when the pulse train 167 is at the same logic high level, the data state of the random access memory circuit 136 is the valid read data 16.
1, when the pulser Ij 157 is at the logic zero (1,) level, the data d of the random access memory circuit 136
, becomes valid write data 162.

On the other hand, at the timing 163a of the valve train 164.

A third digital latch circuit Ffj 134 is latched up and is coupled to the output of the random access memory circuit 136. Over the period 164, this latch-up period 166 and the period of existence of the valid read data 161 overlap, so that the valid read data 161 that has existed since before the first address IfC1 horizontal scanning period of the random access memory circuit 136 is As shown by the arrow 167, the third digital latch circuit 136 is supplied with 1 for one period.
Valid output data 170 as held for 66
It becomes a. Similarly, the timing 163a of the pulse train 164
Then, the second digital latch circuit 134 becomes latch-up, and the input data 171a held in the first digital latch circuit 146 becomes as shown by the arrow 172.
The data is transferred to the second digital latch circuit 134 and held as valid input data 169a. Since the holding period 166 of this valid input data overlaps with the period of existence of the valid write data 162 during the period 166, this valid input data 169a is stored in the first memory of the random access memory circuit 136 as shown by an arrow 168. The data is stored as write data 162 at the th address. This new write data 162 is stored as read data until the next horizontal scanning period arrives and the first address is designated again.

As is clear from the above description of each operation regarding the first address, the second address data 169b of the random access memory circuit 136 can be specified at the button timing 168b, and at the timing 1esb.

Valid output data 170b can be output to the third digital latch circuit 136 and valid input data 169b can be input to the random access memory circuit 136. below,
1 of the digital pixel signal 12 or 27 by sequentially updating the address at a timing repeated at a period of 1/fc during the pulse trains 153, 154, 157.
Pixel information over a horizontal scan period can be simultaneously read and written via the random access memory circuit 136.

As described above, the random access memory circuit 136
The digital one horizontal scanning period memory circuit 23 can be realized from the address counter circuit 137, the second and third digital latch circuits 134 and 135, and the timing pulse generation circuit 144. Note that the first digital latch circuit 146 and the fourth digital latch circuit 146 are driven by the pulse train 163, whereas the second digital latch circuit 134 and the third digital latch circuit 136 are driven by the pulse train 154. , respectively configured as input and output interface circuits.

In particular, the fourth digital latch circuit 146 can share the function of the first digital circuit 117 of the digital color difference signal processing circuit 24 or 26 shown in FIG. Also,
In the configuration of the color camera device shown in FIG. 2, the first digital latch circuit 146 may be regarded as a digital buffer latch circuit that connects the digital white balance circuit 22 and the digital 1 horizontal scanning period memory circuit 23. Furthermore, in the configuration of the color camera device shown in FIG. 3, it may be regarded as a digital buffer latch circuit that connects the A/D converter 2 and the digital 1 horizontal scanning period memory circuit 23.

As an example of the memory capacity of the random access memory circuit 136, if the repetition frequency fC of pixel information is selected to be 7.21M (color burst signal modulation frequency), the memory capacity of the random access memory circuit 136 is approximately 400M.
The memory capacity is approximately address x 8 bits. Note that, for convenience of explanation, the number of bits of digital data for one pixel is assumed to be 8 here, but it is not necessarily limited to this value.

The timing pulse generation circuit 144 shown in FIG.
In this embodiment, two D flipflop circuits 138, 1
39 and four (7) NOR circuits 140 to 143, but since the timing pulse train shown in FIG. isn't it. Also, in the diagram 1o, terminal 1
47 with a repetition frequency of 2fc and a repetition period of 1 applied to a terminal 148.
The H synchronization pulse corresponds to the control pulse signal 20a shown in FIGS. 2 and 3.

FIG. 12 shows another embodiment of the digital one horizontal scanning period memory circuit 23. This digital 1 horizontal scanning period memory circuit 23 stores digital pixel signals 12.2
7 as an input signal consisting of N bits in parallel, it can be constituted by a parallel digital shift register with M transfer stages of N-bit parallel type.

Hereinafter, the explanation will be developed assuming that N=a bits. Taking the case of an NTSC television signal as an example, one horizontal scanning period (
IH) and color burst signal conversion frequency fb 3.58
What is the relationship between the 11 degrees?

It is determined by. On the other hand, the 8-bit parallel digital shift registers 173 to 180 have a frequency fc per pixel.
If the data is transferred in parallel digital shift registers 173 to 180, the number of stages M required for each bit of parallel digital shift registers 173 to 180 is as follows.

becomes. Therefore, if f-7.2%llB is selected, M-455 bits will be obtained, and if fc=14.41Ilb is selected, M-g will be 10 bits. If an integer multiple of fb is selected as fc in this manner, M becomes an integer, and actual parallel digital shift registers 173 to 180 can be constructed. To summarize, in the case of fc-7-2t4&, number of stages M = 455 stages x 8 bits parallel, fo = 14.4
In the case of 11+, parallel digital shift registers 173 to 180 may be configured to have the number of stages M=910×8 bits in parallel. In FIG. 12, parallel digital shift registers 173 to 18o perform parallel transfer at a common transfer lock pulse frequency fC. This clock pulse frequency f. is Figure 2.

This corresponds to the control pulse signal 20a shown in FIG. Furthermore, the first digital latch circuit 146 and the fourth digital latch circuit 146 shown in FIG. may be connected.

As described above, the repetition frequency f is continuously applied. The memory circuit 23 for one horizontal scanning period can be realized by using a plurality of digital shift registers arranged in parallel with the transfer lock pulse consisting of the following.

FIG. 13 shows an embodiment of the digital color difference signal switching circuit 26, in which the first digital latch circuit 181.
Second digital latch circuit 182. Third digital latch circuit 183. Fourth digital latch circuit 184
The input parts of the first digital latch circuit 181 and the second digital latch circuit 182 are connected in common, and the input parts of the third digital latch circuit 183 and the fourth digital latch circuit 184 are connected in common. The output parts of the first digital latch circuit 181 and the third digital latch circuit 183 are connected in common, and the output parts of the second digital latch circuit 182 and the fourth digital latch circuit 184 are connected in common. and the output gate switching timing of the first and fourth digital latch circuits 181 and 184 and the second and third digital latch circuits 182.
, 183 are configured to be opposite to each other in synchronization with the horizontal scanning period.

FIG. 14 shows the digital color difference signal processing circuits 24 and 2.
6, and the digital color difference signal switching circuit 2
A digital color difference signal of 29.30, which becomes the big sword signal of 6,
The relationship between the digital color difference signals 14°16, which are the output signals of the digital color difference signal processing circuit 26, is expressed as follows:
It is expressed by repeating 1H). Below, the 14th
The operation of the digital color difference signal switching circuit 26 shown in FIG. 13 will be explained with reference to the drawings. From FIG. 14, the digital color difference signals 29 and 30 are digital (M-
G) A color difference signal train and a digital (C-Y) color difference signal train are repeated, and the information contents (M-Q) information or (C-Y) information are mutually inverted.

These digital color difference signals 29.30 and υ, a digital color difference signal 14 having only a digital (MG) color difference signal train in all horizontal scanning periods, and a digital (C-y)
The purpose of the digital color difference signal is to create a digital color difference signal 16 having only a color difference signal sequence in all horizontal scanning periods. A digital color difference signal 29 is applied to the inputs of the first digital latch circuit 181 and the second digital latch circuit 182, and a digital color difference signal 3o is applied to the inputs of the third digital latch circuit 183 and the fourth digital latch circuit 184. When a switching timing pulse 186 with a repetition period of 2H is applied via a terminal 186, a timing pulse 187 is applied to the output gate CG of the first digital latch circuit 181 in one horizontal period 188a. The timing pulse 186 is applied to the output gate CG of the third digital latch circuit 183 to turn it into a conductive state, so that the digital (MG) information 29a is transferred between the first digital latch circuit 181 and the third digital latch circuit 183. It is output to the common output terminal 189 of the digital latch circuit 183 of 3, and simultaneously 1 horizontal scanning period 18
8a, a timing pulse 186 is applied to the output gate CG of the second digital latch circuit 182 to bring it into a cutoff state, and a timing pulse 187 is applied to the output gate CG of the fourth digital latch circuit 184 to bring it into a conductive state. Therefore, digital (C-Y) information 30
a is output to the common output terminal 190 of the second digital latch circuit 182 and the fourth digital latch circuit 184. Similarly, the output gate CG of each f digital latch circuit 181 to 184 of the timing pulses 186 and 187
Considering the application state to 188b, the next horizontal scanning period 188b
In this case, the output gate (CG) of the first digital latch circuit 181 is cut off, and the output gate (CG) of the third digital latch circuit 183 becomes conductive.
-G) Information 30b is output to the common output terminal 189, -
At 1:00, the output gate CG of the second digital latch circuit 182 is conductive, and the output gate CG of the fourth digital latch circuit 184 is in the disconnected state.
Y) Information 29b is output to the common output terminal 190. Hereinafter, as shown by the dotted line 195 in FIG. 14, the digital M-G information @ 29 a, 30 b, 29
c, 30d... are selected and common output terminal 1
89, the digital color difference signal 14 and the digital (C-Y) information 30 are output as shown by the one-point W string 19e.
a.

29b, 30c, 29d, . . . are selected and output to the common output terminal 190, and become the digital color difference signal 15. Further, the digital color difference signal 29.30 has a repetition period of 1/fo within one horizontal scanning period.
Since the pixel information is 1. 2nd゜3rd. The fourth digital latch circuits 181 to 184 perform a latch-up operation when a clock pulse with a repetition period of 1/fo is supplied from the terminal 197 to CK of each clock gate, and the digital color difference signal processing circuits 24. It is configured to synchronize with 26. Here, the timing pulse train 18 with a repetition period of 2H is applied to the terminal 186.
6 and the above clock pulse applied to terminal 197 correspond to control pulse signal 20d in FIG.

In FIG. 14, the digital color difference signal 29 is a digital color difference signal 38, the digital color difference signal 30 is a digital color difference signal 39, the digital color difference signal 14 is a digital color difference signal 42, and the digital color difference signal 16 is a digital color difference signal 43. In other words, in exactly the same way, a thirteenth embodiment of the digital color difference signal switching circuit 26 constituting the color camera device shown in FIG.
The configuration shown in the figure can be applied in the same way.

As described above, the digital color difference signal switching circuit 2e shown in FIGS. 2 and 3 can be realized using a digital latch circuit.

FIGS. 16(-) and 16(b) are block diagrams showing configuration examples of the digital video signal processing device 31, respectively.

In the present invention, as shown in FIG. 4 as an embodiment of the solid-state imaging device 1, the color filters include magenta M,
By selecting a filter array consisting of green G, cyan C, and yellow Y, M.

Although a means for generating a digital pixel signal 12a consisting of G, M, G, . . . and a digital pixel signal 12a consisting of C, Y, C, Y, . The reason is that the sum of the magenta M signal and the green G signal (M + G) and the sum of the cyan C signal and the yellow signal (CRT) can be made equal to the video (white) signal yK. That is, y = M 10G ...... (3) 7-
CRT: The optical sensitivity of the color filter is selected so that (4). Therefore, the digital pixel signal 12 and the digital image (white)
The operating functions forming the signal 34 are M, G, M,
G or C, Y.

A digital signal string consisting of C, Y p M 4- G,
M+G, M+G or C+ Y, C+ Y, C4
If the video signal correction circuit 198 executes the inactive function of forming a digital signal string consisting of -Y, the function of the video signal processing circuit 31 can basically be achieved. This configuration example is the 16th
The figure is (-).

Further, the digital video signal processing circuit 31Vi illustrated in FIG. 16(b), the first video signal correction circuit 199 and the second
It consists of a video signal correction circuit 200 and an averaging circuit 203. The digital pixel signal 12 or 2a is applied to the first video signal correction circuit 199, and the above equation (3), (
Digital addition as shown in 4) is performed. Sweet,
The digital pixel signal 28 or 37 delayed by one horizontal scanning period by the memory circuit 23 for one horizontal scanning period is applied to the second video signal correction circuit 200, and the equation (3), (4)
) is performed. Then, the digital video signals 201 and 202 from the video signal correction circuits 199 and 200 are added and divided by 2 in an averaging circuit 203 to obtain a digital video signal 34 as an output. As is clear from the above configuration, the digital video signal 34 in this case is an image signal in a form in which image information in one horizontal scanning direction is correlated with an image in the next horizontal scanning direction. It can achieve the effect of smoothing the vertical resolution of
You can expect an improvement in image quality. Furthermore, by including a function of varying the addition/q ratio of the digital video signal 201 and the digital signal 202 in the averaging circuit 203, it is also possible to adjust the optimum image quality in the vertical direction.

As described above, the digital video signal processing circuit 31 shown in FIG. 16(b) has the effect of improving image quality in the vertical direction. In Figure 4, M, G, C, and Y colors were selected as the four different color filter configurations, but even if these are replaced with other color filter systems, equations (3) and (4) will still be satisfied. If you want to do it, you can do it in the same way.

FIG. 16 shows the video signal correction circuit 198, 199° 20
FIG. 2 is a block diagram showing a configuration example of 0. This consists of a 1 pixel shift circuit 204 and a digital addition circuit 206.
The functions of 06 are the digital color difference signal processing circuit 2.
The functions are the same as those of the one-pixel shift circuit 110 and digital adder circuit 112, which are the components of 4.25. Therefore, the purpose of the 1 pixel shift circuit 1100 is M, G,
M.

This is to selectively shift only the digital G signal or digital Y signal by one bit time from the column of digital pixel signals 12 consisting of G or C, Y, C, Y. The digital C signal or digital Y signal shifted in this way.

Unshifted digital M signal or digital C
If the signal is added with the digital addition circuit 206, M +
Digital video signal consisting of G, M + G, M + G, ... or C-1-Y, C + Y
, C+Y, . . . to obtain a digital video signal.

As described above, the digital video signal correction circuits 198, 199, and 200 can be configured by the one-pixel shift circuit 204 and the digital addition circuit 206.

Figure 17 shows the video signal correction circuit 198.199°20.
FIG. 18 shows a time chart and input/output digital data for explaining the operation of this embodiment. 1st
As is clear from a comparison between FIG. 7 and FIG. 8, the circuit shown in FIG. 17 is the circuit in FIG. 8 from which the digital inverter circuit 121 is removed. Therefore, the first digital latch circuit 206 in FIG. Second digital latch circuit 20'7. The operations of the third digital latch circuit 20B and the D flip-flop circuit 209 are similar to those of the first digital latch circuit 117 in FIG.
．． Second digital latch circuit 118. The operation of the third digital latch circuit 119 is the same as that of the 70° D flip circuit 120. That is, when a pulse train 123 with a repetition period of 1/f0 is applied to the terminal 210, a pulse train 126 is generated at the Q terminal of the D7 listen log circuit 209, a pulse train 127 is generated at the ◇ terminal, and the first If the digital pixel signal 12a is input to the digital latch circuit 20 (5), the second digital digital M signal information 1
30 can be selectively latch-up, and the third digital latch circuit 208 has a digital C
Signal information 2f.

131 can be selectively latch-up, and furthermore, it is possible to selectively latch up the digital M signal information 130 and the digital
1 has a relative phase shift of 1/fc corresponding to one pixel period.

In this way, if the digital M signal information 130 and the digital C signal information 131 are added by the digital addition circuit 206, the desired M+G, M+G, M+G are obtained.
, . . . , a digital video signal 214 consisting of columns can be obtained. In addition, a synchronized pulse train (force 11) which repeats in one horizontal scanning period is supplied to the terminal 211, and this pulse train is applied to reset the entire system.This pulse train and the pulse train 123 corresponds to the control noculus 19 & shown in FIGS. 2 and 3. As described above, the video signal correction circuits 1ea, 1'e9,
200 is realized.

From a comparison between FIG. 17, which is an embodiment of the video signal correction circuit, and FIG. 8, which is an embodiment of the digital color difference signal processing circuit, it is clear that, as discussed above, the circuit means constituting the one-pixel shift circuit consists of three components. They are composed of digital latch circuits and have exactly the same operating mode.Moreover, both circuits have digital pixel signals 12, 27, 28, or 37 at their inputs.
is input, the digital color difference signal processing circuit 2
4.25 and the video signal correction circuit 198. 1 that makes up 199.200
Parts of the pixel shift circuit 206 can also be shared as one circuit.

Such sharing is particularly important when the digital video signal processing device #3 and the digital color signal processing device 4 are configured as an integrated digital integrated circuit.

FIG. 19 shows the digital gamma correction circuit 32.

This example shows that it can be constructed from a programmable read-only memory (ROM) table integrated circuit 216 (eg, 5N74S471). In this example, parallel 8
The case of pit digital input/output is shown. Digital video signal 3 is input to the parallel 8-bit digital input terminal 216.
6 is added to the parallel 8-bit digital output terminal 217.
A digital video signal 36 is output. An example of the gamma characteristic 218 shown in No. 20 is a value E1 obtained by converting a digit signal applied to the parallel 8-pit digital input terminal 216 into analog, and a value E1 obtained by converting the digit signal applied to the parallel 8-pit digital input terminal 216 to the parallel 8-pit digital output terminal 217.
The value E2 obtained by converting the digit signal output to analog
This shows the relationship between This gamma characteristic 218 can be changed by rewriting the contents of the ROM table.

As described above, the digital gamma correction circuit 32
This can be realized with read-only memory (ROM), and this RO
If M is a rewritable programmable ROM, the gamma characteristics can be changed using information 19b from an external terminal.

FIG. 21 shows an embodiment of the digital white balance circuit 22 in the color camera device shown in FIG. This digital white balance circuit 22
consists of a digital multiplier circuit 221, first to fourth digital latch circuits 222 to 226, and a digital latch switching circuit 226, and the output terminals of the four digital latch circuits 222 to 226 are connected as a common output bus 233. A digital latch switching circuit 226 is connected to a digital multiplication term input terminal of a digital multiplication circuit, and is configured to control latch-up timing of the four digital latch circuits 222 to 226. The operation will be explained below when the solid-state imaging device 1 shown in FIG. 4 is used and the digital pixel signal 12 output from the A/D converter 2 is added as an input signal to the digital multiplication circuit 221. Let's do it.

As shown in FIG. 22 (-), in a certain horizontal scanning period H4, the digital pixel signal 12 is magenta M.

This becomes a green G repeating signal. The digital switching circuit 226 latches up the first digital latch circuit 222 at timing 227a and outputs the magenta M signal multiplication term 229 to the common output bus 233, so the digital M signal 284 is multiplied by the digital multiplication circuit 221. A digital M signal 236 is obtained after receiving the multiplication term 229. Similarly, at timing 227b, the second digital latch circuit 22) is latched up and outputs the green G signal multiplication term 230 to the common output bus 233.

The digital C signal 236 is sent to the digital multiplication circuit 221
Digital C signal 2 multiplied by and subjected to 9 multiplication terms 230
It becomes 37.

Hereinafter, the digital pixel signal that repeats M, G, M, G, etc. is as follows within the horizontal scanning period H1.
Since the digital latch switching circuit 226 sequentially latches up the first and second digital latch circuits 222 and 223, as shown in FIG. 22 0))f.

M, G, M, G,... after a certain multiplication operation.
The digital pixel signal 27 consists of . In the next horizontal scanning period H2, as shown in FIG. It will be uploaded, so Sian C
Signal multiplication term 231 is output to common output bus 233 and digital C signal 238 is output.

A digital C signal 239 is obtained by being multiplied by a digital multiplication circuit 221 and subjected to 9 multiplication terms 230.

Similarly, at timing 228b, the fourth digital latch circuit 226 is latched up and outputs the yellow Y signal multiplication term 232 to the common output fitting 233, and the digital Y signal 240 is multiplied by the digital multiplication circuit 221 and multiplied by A digital Y signal 241 is obtained by receiving the term 232. Thereafter, the digital pixel signal that is repeated as C9y, c, y, . Therefore, as shown in FIG. 22(b), a certain multiplication term 23
C, Y, C, Y, who received 1,232...
A digital pixel signal 27 consisting of

As described above, the four digital latch circuits 222 to 2
26 is selected according to the four different digital pixel signals that enter the digital multiplier circuit as an input, and by adding independent multiplication a terms 229 to 232, four types of digital pixel signals 2 with Zeit balance correction are generated.
7 can be output to the output of the digital multiplier circuit 221. In addition, in FIG. 2, the control signal 3e applied to the digital white balance circuit 22 is the multiplication term 22.
It consists of digital data 9.230, 231, and 232, signal information with a repetition period of 2H for controlling the digital latch switching circuit 226, and pulse information with a period of 1/f.

FIG. 23 shows an embodiment of the digital white balance circuit 4o in the color camera device shown in FIG. This digital white balance circuit 4o
is composed of a first digital multiplication circuit 242 and a second digital multiplication circuit 243, and digital multiplication terms 244 and 246, which are white balance control signals, are supplied to the multiplication term input terminals of the digital multiplication circuits 242 and 243. It is configured to Hereinafter, when the solid-state imaging device 1 shown in FIG. Digital power of q: Regarding the case where it is input to the circuit 243.

Let's explain its operation.

As shown in FIG. 24(a), in one horizontal scanning period, the digital color difference signal 42 has a repetition period of 1/f.
It is a digital pulse train consisting of c''''CM-G, MG,..., and the digital color difference signal 43 is the 24th pulse train.
As shown in Figure 0)), the repetition period is jig.

This is a digital pulse train consisting of c-y, c-y, . These digital color difference signals 42°43
are applied to the first digital multiplication circuit 242 and the second digital multiplication circuit 243, respectively, and are calculated to add a certain digital multiplication term 244 and a digital multiplication term 246, respectively, the digital multiplication circuits 242 and 2
At the output section of 43, digital color difference signals 14 and 16 as shown in FIGS. 24(a) and 24(b) can be obtained.

The above digital color difference/signal 14 is a digital multiplication term 24
The digital color difference signal 16 has a digital multiplication term 246 added thereto.

As described above, the digital multiplication circuits 242 and 243
Additionally, since the two independent digital color difference signals can be varied, it is possible to obtain digital color difference signals 14 and 15 with white balance correction.

In FIG. 3, the control signal 41 applied to the digital white balance circuit 4o is the digital multiplication term 244, 24 made of constant digital data.
5, and as a control method, the digital multiplication terms 244, 245 are controlled by a microcomputer.
It is possible to control the value of .

FIG. 26 shows an embodiment of the standard color television signal synthesis device 6 shown in FIGS. 1 to 3, which includes:
First digital-to-analog (D/A) conversion circuit 246
, a second digital-analog ('D/A) conversion circuit 247, a color difference coefficient modulation circuit 248, a third digital-analog (D/A) conversion circuit and synchronization pulse addition circuit 249, and a synthesis circuit. It consists of 260. The operation will be explained below.

The digital color difference signal 14 is input to the first D/A conversion circuit 246.
is applied to generate an analog color difference signal 260. Further, the digital color difference signal 16 is applied to the second D/A conversion circuit 247, and an analog color difference signal 261 is generated.

At this time, the terminal 264 is connected to the D/A conversion circuit 246.
A control pulse signal with a repetition period of 1/f is applied to drive 247. Also, 1st. The second D/A conversion circuits 246 and 247 receive blanking pulses and burst periods that define the vertical and horizontal blanking periods of the television signal from the drive circuit device 6 via terminals 262 and 253, respectively. A prescribed burst flag pulse is applied to maintain the analog color difference signals 260, 261, which are the outputs of the first and second D/A conversion circuits 24.6, 247, at a constant level over these periods. Next, the analog color difference signals 260 and 261 are applied to the color difference signal modulation circuit 248, resulting in a color signal 2θ3 modulated with two independent phase modulation axes. Burst flag pulses that define the vertical and horizontal blanking periods of the television signal are applied to the color difference signal modulation circuit 248 via terminals 252 and 253, and the burst flag pulses that define the vertical and horizontal blanking periods of the television signal are applied. Defines the blanking period and burst signal addition period of the color signal 263.Terminal 264
A burst carrier pulse with a repetition frequency of 3.68Nih is applied to. On the other hand, in the third D/A conversion circuit and synchronization pulse addition circuit 249, a white level reference signal that specifies the black and white level of the video signal is sent to a terminal 266, and a blanking signal that specifies vertical and horizontal blanking periods is sent to a terminal 267. Vertical and horizontal synchronizing pulses are applied to a terminal 258, and a control pulse signal with a repetition period of 1/f is applied to a terminal 269, respectively, receiving the digital video signal 13 as an input and a black and white standard television signal 262 as an output. occurs. The color signal 263 and the monochrome standard television signal 262 are converted into a standard color television signal 16 by a combining circuit 260. Note that the repetition period applied to terminals 264 and 269 is 1/f.
control pulse signals applied to terminals 262 and 267, blanking pulses defining vertical and horizontal blanking periods, burst flag pulses applied to terminal 253, and repetition frequency applied to terminal 264.
The burst carrier pulse 581) and the vertical and horizontal synchronization pulses applied to terminal 268 correspond to the control pulse signal 21 shown in FIGS. 1-3.

As described above, the first step. Second D/A conversion circuit 246
．． 247, a third D/A conversion circuit and a synchronization pulse addition circuit 249, a color difference signal modulation circuit 248, and a synthesis circuit 2
50, a standard color television signal synthesis device 6 can be constructed, and the first and second digital color difference signals 1
4.15 and digital video signal 13 as input,
The dust means of the standard color television signal synthesis device 6 for obtaining the standard color television signal 16 is not limited to the configuration shown in FIG. 26.

In the embodiment of the digital signal processing unit of the present invention, the data bit a of the digital data has been explained as 8, but the present invention is not limited to this value, and is based on the design concept of the entire color camera system. Of course, you can choose an appropriate value, such as 6 pits or 10 bits, as well as the clock frequency f. fc-7,
2+4k or f. Although it is preferable to select =14.1h, in other systems, the effects of the present invention can be achieved even if other values are selected as appropriate.

Effects of the Invention As is clear from the above description, the present invention receives an optical signal and, in a certain horizontal readout scanning period, synchronizes with the readout clock frequency (fo) and alternately reads different color signals for each pixel. A first pixel signal consisting of repetition is output, and in synchronization with the readout clock frequency (fo) in the next horizontal readout scan amount, information different from the first pixel signal and alternately for each pixel is output. An A/D conversion device that converts the first and second pixel signals outputted from the imaging device into analog-to-digital format, such as an imaging device that outputs a second pixel signal consisting of repetitions of different color signals. , said A
a digital color signal processing device that receives a digital pixel signal output from the /D conversion circuit as an input and outputs two systems of independent first and second digital color difference signals; and a digital color signal processing device that receives the digital pixel signal as an input and outputs a digital video signal. a digital video signal processing device that outputs the first . Second
a standard color television signal synthesis device which inputs the digital color difference signal and digital video signal and outputs a standard color television signal, a drive circuit device which drives the imaging device, the A/D conversion device, and the digital video signal. It is equipped with a control circuit device that generates timing pulses for driving a processing device, a digital color signal processing device, and a standard color TV DI1 signal synthesis device, so it is the core of the signal processing section of a color camera device. The digital color signal processing device and the digital video signal processing device can be realized with a new digital circuit, which makes it possible to eliminate the need for adjustment and make the color camera device ultra-compact, which was a limitation in color camera devices using conventional analog signal processing circuits.・
This provides excellent effects such as weight reduction, high reliability, and low cost.

The present invention further provides the digital color signal processing device with a digital white balance circuit, a digital one horizontal scanning period memory circuit, a first . The digital video signal processing device is configured to include a second digital color difference signal processing circuit and a digital color difference signal switching circuit, and the digital video signal processing device is configured to include a digital video signal processing circuit and a digital gamma correction circuit. When the signal processing circuit and the digital video signal processing circuit are partially shared by a digital latch circuit, the digital wide balance and digital gamma correction circuits can be controlled immediately by the signal processing section of the color camera device of the present invention. Since it can be controlled by a microcomputer, it is possible to achieve more precise and stable control than conventional devices that use analog signal processing, resulting in a color camera device that can capture high-quality color images. can.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts showing the basic configuration of a Z color camera device of the present invention, FIG. 2 is a block diagram of main parts of a color camera device according to an embodiment of the present invention, and FIG. 3 is a block diagram of main parts of a color camera device according to an embodiment of the present invention. FIG. 4 is a block diagram of main parts of a color camera device according to an embodiment of the present invention, FIG. 4 is a schematic configuration diagram of an example of an imaging device used in the present invention, and FIG.
The figure shows the output and force waveforms output from the imaging device in Figure 4 and the operating waveforms of the NO converter that converts these waveforms from analog to digital. Figures 6 (a) and (b) are A
FIG. 7 is a block diagram showing an example of the configuration of a digital color difference signal processing circuit; FIG. 8 is a block diagram showing a specific example of the configuration of the main parts of the digital color difference signal processing circuit. A circuit configuration diagram, FIG. 9 is a signal time chart and a waveform diagram showing input/output digital switches to explain the operation of the digital color difference signal processing circuit, and FIG. 10 is a configuration example of a memory circuit for one horizontal scanning period. A block diagram, FIG. 11 is a signal time chart and a waveform diagram showing input/output digital data to explain the operation of the memory circuit for one horizontal scanning period, and FIG. 12 is another configuration example of the memory circuit for one horizontal scanning period. Figure 13 is a block diagram showing a configuration example of a digital color difference signal switching circuit.
Figure 14 is a signal waveform diagram for explaining the operation of the digital color difference signal switching circuit, and Figures 15 (a) and (b).
16 is a block diagram showing each configuration example of a digital video signal processing device, FIG. 16 is a block diagram showing a configuration example of a digital video signal correction circuit, and FIG. 17 is a block diagram showing a configuration example of a digital video signal correction circuit. Fig. 18 is a time chart of a signal and a waveform diagram showing input/output digital data to explain the operation of the digital video signal correction circuit, Fig. 19 is a diagram showing an example of the configuration of the digital gamma correction circuit, and Fig. 20 is its diagram. A gamma characteristic diagram, FIG. 21 is a block diagram showing a configuration example of a digital white balance circuit in the color camera device shown in FIG. 2, and FIG. 22(a)
, (b) is a waveform diagram explaining its operation, FIG. 23 is a block diagram showing a configuration example of the digital white balance circuit in the color camera device shown in FIG. 3, and FIG.
, (b) is a waveform diagram for explaining its operation, and FIG. 26 is a block diagram showing an example of the configuration of a standard color television signal synthesis device. 1... Solid-state imaging device, 2... Aρ conversion device, 3... Digital video signal processing device, 4
...Digital color signal processing device, 6...
・・Standard color television signal synthesizer, 6...
...Drive circuit device, 7...Control circuit device, 8...
...Optical signal, 9, 10... Pixel signal, 11
...Control signal, 12...Digital pixel signal, 13...Digital video signal, 14,1
5...Digital color difference signal, 16...
Standard color television signal, 17... Control signal, 18, 19° 20.21... Control pulse signal, 22... Digital white balance circuit, 23... ...Digital 1 horizontal scanning period memory circuit, 24, 25...Digital color difference signal processing circuit, 26...Digital color difference signal switching circuit, 2
7.2-8...Digital pixel signal, 29.3
0...Digital color difference signal, 31...
Digital video signal processing circuit, 32...Digital gamma correction circuit, 33...DiJ delay circuit, 34.35...Digimol video false code 0.36
...Control signal, 37...Digimol image signal, 38°39...Digital color difference signal,
40...Digital white balance circuit, 4
1...Control signal, 42°43...Digital color difference signal, 96.104,105...A
//D conversion circuit, j06, 107...Digital latch circuit, 110...1 pixel shift circuit,
111...1 pixel inversion circuit, 112...
・Digital addition circuit, 117-119, 134, 13
5,146゜146...Digital latch circuit, 136...Random access memory times M, 173
~180...Digital shift register, 18
1-184...Digital latch circuit, 198
~200... Mountain gorge image signal correction circuit, 203...
・Additional averaging circuit, 2o4...1 pixel shift circuit, 205...digital addition circuit, 206~
208...Digital latch circuit, 222-2
25...Digital latch circuit. 221.242.243...:...Digital multiplication circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 4
Figure 5 Figure 7 Figure 8 //θ Figure 16 Figure 18 Figure 23 Figure 40 (see) and 75 Figure 25

Claims (1)

[Claims] (1) During the horizontal readout scanning period after receiving the optical signal,
In synchronization with the readout clock frequency, a first pixel signal consisting of repeating alternately different color signals is output for each pixel, and in the next horizontal readout period, in synchronization with the readout clock frequency, the first pixel signal is outputted in synchronization with the readout clock frequency. Unlike signal information,
and an imaging device configured to output a second pixel signal consisting of repeating different color signals alternately for each pixel, and a digital signal that converts the first and second pixel signals output from the imaging device. an analog-to-digital converter for converting the pixel signal into a pixel signal; a digital color signal processing device for receiving the digital pixel signal output from the analog-to-digital converter and outputting independent first and second digital color difference signals; a digital video signal processing device that receives a pixel signal as input and outputs a digital video signal; and a standard color television signal synthesis device that receives the first and second digital color difference signals and the digital video signal as input and outputs a standard color television signal. a drive circuit device that drives the imaging device;
a control circuit device that generates a timing noise for driving the analog-to-digital converter, the digital video signal processing device, the digital color signal processing device, and the standard color television signal synthesis device; The device includes a digital white balance circuit, a digital one horizontal scanning period memory circuit, first and second digital color difference signal processing circuits, and a digital color difference signal switching circuit, and the output of the analog-to-digital conversion device is the first digital color difference signal processing circuit and the digital one horizontal scanning period memory circuit; the output signal of the digital one horizontal scanning period memory circuit is applied to the second digital color difference signal processing circuit; and the output signal of the second digital color difference signal processing circuit is applied to the digital color difference signal switching circuit, and the first and second digital color difference signals are obtained from the digital color difference signal switching circuit, and the a signal transmission path from the analog-digital conversion device to the first digital color difference signal processing circuit and the digital one horizontal scanning period memory circuit; and a signal transmission path from the digital color difference signal switching circuit to the standard color television signal synthesis device. A color camera device characterized in that the digital white balance circuit is inserted into one of the signal transmission paths. (2) The imaging device consists of color filters attached to its light-receiving surface, which are arranged repeatedly in one horizontal scanning direction in the order of magenta, green, magenta, etc. , yellow, cyan, yellow...
. . . The color camera device according to claim 1, wherein the color camera device is configured to be repeatedly arranged as follows, and these arrangements are alternately repeated in the vertical scanning direction. (3) The digital video signal processing device is an analog
A digital video signal processing circuit receives a delayed digital pixel signal obtained from the digital pixel signal given from the digital conversion device and the memory number of one digital horizontal scanning period, and performs gamma correction on the output signal of the digital video signal processing circuit. Claim No. 3 is characterized in that it is configured including a digital gamma correction circuit.
1) The color camera device described in item 1). (4) The digital video signal processing circuit selectively processes a specific digital pixel signal from the input digital pixel signal string.
a 1-pixel shift circuit for bit time shifting; and a digital addition circuit for adding digital pixel signals not shifted by the 1-pixel shift circuit in the input digital pixel signal string and output digital pixel signals of the 1-pixel shift circuit. The color camera device according to claim 1 is characterized in that it is configured with: The first
second and third digital latch circuits to which the output of the digital launch circuit is selectively distributed at predetermined timing, and the outputs of the second and third digital latch circuits are provided to the digital adder circuit. A color camera device according to claim (4), characterized in that: (6) The digital video signal processing circuit consists of a first video signal correction circuit that performs a digital addition operation on digital pixel signals, and a second video signal correction circuit that performs a digital addition operation on delayed digital pixel signals obtained from the digital 1 horizontal scanning period memory circuit. Claim (3) characterized in that the video signal correction circuit includes a video signal correction circuit and an averaging circuit that adds and averages the outputs of the first and second video signal correction circuits. The color camera device described above. A patent claim characterized in that the digital pixel signal includes a digital addition circuit that adds a digital pixel signal that is not shifted by the one-pixel shift circuit in the digital pixel signal string and an output digital pixel signal of the one-pixel shift circuit. The color camera device according to item (6) of the range.
second and third digital launch circuits to which the outputs of the digital latch circuits are selectively distributed at predetermined timing, and the outputs of the second and third digital latch circuits are provided to the digital adder circuit. A color camera device according to claim (7), characterized in that: (9) The digital white balance circuit is inserted into a signal transmission path from the analog-to-digital converter to the first digital color difference signal processing circuit and the digital one horizontal scanning period memory circuit, and is configured to output from the analog-to-digital converter. a digital multiplier circuit to which a digital pixel signal is input; Second. Third. It includes a fourth digital launch circuit and a digital latch switching circuit, and the first... Second. Third. A fourth digital latch circuit is configured to be sequentially activated by the digital latch switching circuit and to multiply the four types of digital pixel information by white balance multiplication terms corresponding to four different types of digital pixel information. A color camera device according to claim (1), characterized in that: (10) The digital white balance circuit is inserted into the signal transmission path from the digital color difference signal switching circuit to the standard color television signal synthesis device, and receives the digital color difference signals from the digital color difference signal switching circuit, respectively. The color camera device according to claim 1, further comprising first and second digital multiplication circuits each receiving a white balance control signal as a multiplicand. (11) The first and second digital color difference signal processing circuits include a 1-pixel shift circuit that selectively shifts a specific digital pixel signal by 1 bit time from an input digital pixel signal string, and an output of the 1-pixel shift circuit. a 1-pixel inversion circuit that inverts a digital pixel signal; and a digital addition circuit that adds the digital pixel signal that is not shifted by the 1-pixel shift circuit in the input digital pixel signal string and the output digital pixel signal of the 1-pixel inversion circuit. A color camera device according to claim 1, characterized in that the color camera device is configured to include the following. (12) The 1-pixel shift circuit includes a first digital latch circuit to which an input digital pixel signal string is input, and a second digital latch circuit to which the output of the first digital latch circuit is selectively distributed at a predetermined timing. A third digital latch circuit is included, and the output of the second digital latch circuit is directly given to a digital addition circuit, and the output of the third digital latch circuit is applied to a digital inverter constituting a one-pixel inversion circuit. 12. The color camera device according to claim 11, wherein the color camera device is configured to be applied to the digital adder circuit through the digital adder circuit. (13) The digital one horizontal scanning period memory circuit includes a plurality of digital latch circuits, a random access memory circuit, an address counter circuit, and a timing pulse generation circuit, and the plurality of digital latch circuits include the random access memory circuit. connected as an input/output interface of an access memory circuit, the address counter circuit determining a write/read address of the random access memory circuit, and the timing pulse generating circuit configured to control the address counter circuit. (14) The digital one horizontal scanning period memory circuit is constituted by a plurality of digital shift registers. The color camera device according to the range (1).
and a second digital latch circuit, and third and fourth digital latch circuits to which the outputs of the second digital color difference signal processing circuit are input, respectively, and the outputs of the first and third digital latch circuits. The output parts of the second and fourth digital latch circuits are connected in common, and the output gate switching timing of the first and fourth digital latch circuits and the second and fourth digital latch circuits are connected in common. 2. The color camera device according to claim 1, wherein the output gate switching timing of the third digital latch circuit is configured to be synchronized with and contradictory to the horizontal movement period. (16) The standard color television signal synthesis device includes first and second digital-to-analog conversion circuits that convert first and second digital color difference signals output from the digital color signal processing circuit into analog color difference signals, respectively. , a third digital-to-analog conversion circuit and a synchronization pulse addition circuit for converting the digital video signal output from the digital video signal processing device into a black and white standard television signal, and the first and second digital-to-analog conversion circuits. a color difference signal modulation circuit which takes as input an analog color difference signal and obtains a color signal modulated by two independent phase modulation axes; and receives the black and white standard television signal and the color signal as input to obtain a standard color television signal. A color camera device according to claim 1, characterized in that the color camera device includes a composition circuit.