JPS5986987A - Color camera device - Google Patents

Abstract

PURPOSE:To realize a titled device high in reliability, low in cost, requiring no-adjustment, to make it small in size and light, and to make its operability simple by constituting a signal processing part of a digital circuit. CONSTITUTION:A solid state image pickup device 1 which photodetectors an optical signal 8 outputs two kinds of picture element signals 9, 10 consisting of repetition of a color signal which is different in every adjacent picture element. The picture element signals 9, 10 become a digital picture element signal 12 by an A/D converter 2. The picture element signal 12 is converted to a digital video signal 13 by a digital video signal processing device 3, and is converted to the first and the second digital color difference signals 14, 15 by a digital color signal processing device. These converted signals 13, 14 and 15 become a standard color television signal 16 by a standard color television signal synthesizing device 5 and are outputted. In this regard, each device 2, 3, 4, 5 and 6 is controlled by pulse signals 18, 19, 20 and 21 from a controlling circuit device 7.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to television studio cameras, industrial viewing cameras,
This relates to a color camera device that can be used as a camera for industrial robots, a camera for home video tape recorders, etc. 0 Conventional configurations and their problems In recent years, home video tape recorders have become rapidly popular. Accordingly, color cameras that can be paired with video tape recorders, are lightweight, compact, low-priced, and easy to operate to capture images are being actively developed.

However, conventionally, the signal processing section of a color camera has mostly adopted an analog signal processing method, but color camera devices using this analog signal processing method have the following problems.

(1) Since the analog electrical signal detected from the received light signal is processed, the signal-to-noise (S/N) ratio theoretically deteriorates each time it passes through each signal processing block. In order to correct this, various correction or adjustment circuits are required, resulting in a very complicated system configuration, which is one of the factors that increases the variation in performance of the resulting product (color camera device). It has become.

(2) In a commercially available color camera device that uses an image pickup tube as an imaging device, there are as many as 30 or more adjustment points during manufacturing, which increases the number of parts and results in high product costs.

(3) Current analog signal processing type color cameras always have signal processing filters and ultrasonic waves for one and a half hours (1H).
Although delay lines and the like are required, these are constructed from L-C-R components, and it would be impossible to convert the entire analog signal processing section into a monolithic IC. In other words, there is a limit to the miniaturization of analog signal processing circuits.

(4) For color cameras that use analog signal processing.

It was linked to a microcomputer. Complex control circuits are required to control white balance adjustment, gamma (comma) correction, etc. This also increases the cost of the product and complicates operation.

In summary, color camera devices that use the current analog signal processing method have high reliability, low cost, no adjustment circuitry, ultra-miniaturization of the entire 9-circuit system that requires no adjustment, and easy operability for imaging. There are limits to what we can pursue.

OBJECT OF THE INVENTION The purpose of the present invention is to improve the reliability, reduce the cost, and eliminate the need for adjustment of a color camera device, which has limitations in the conventional analog signal processing method by constructing the signal processing section of the color camera device using a metal digital circuit. An object of the present invention is to provide a color camera device that is ultra-compact, lightweight, and allows easy imaging operation.

Structure of the Invention The color camera device of the present invention receives a light signal and, during a horizontal readout scanning period, generates a first pixel signal consisting of repeating alternately different color signals for each pixel in synchronization with a readout clock frequency. and in the next horizontal readout period, a second pixel signal synchronized with the readout clock frequency, different from the information of the first pixel signal, and consisting of repeating color signals that are different alternately for each pixel. an imaging device configured to output a digital signal; an analog-to-digital conversion device configured to convert first and second pixel signals output from the imaging device into digital signals;
a digital color signal processing device that receives a digital pixel signal output from a digital conversion device as an input and outputs independent first and second digital color difference signals; and a digital video device that receives a digital pixel signal as an input and outputs a digital video signal. a signal processing device; a standard color television signal synthesis device that receives the first and second digital color difference signals and the digital video signal and outputs a standard color television signal; a circuit device that drives the imaging device; It is equipped with a control circuit device that generates timing pulses for driving an analog-to-digital converter, a digital video signal processing device, a digital color signal processing device, and a standard color television signal synthesis device. It is possible to realize a color camera device in which the signal processing section, which is essential to the basic configuration of the device, can be easily converted into digital signal processing.

(The following is a blank space) Description of Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of a color camera device according to the present invention. This includes a solid-state imaging device 1, an analog to digital (hereinafter abbreviated as A/D) conversion device,
It consists of a digital video signal processing device 3, a digital color signal processing device 4, a standard television signal synthesis device 5, a drive circuit device 6, and a control circuit device 7.

The basic operation of the color camera device configured as described above will be explained below. The solid-state imaging device 1 that has received the optical signal 8 has a readout clock frequency f during a certain horizontal readout scanning period. A first pixel signal 9 consisting of repeating alternately different color signals is output for each adjacent pixel in synchronization with 11, and in the next horizontal readout scanning period, the readout clock frequency f is output. A second pixel signal 1o is output in synchronization with the information of the first pixel signal 9, which is composed of a repetition of color signals that are different from each other and alternately for each adjacent pixel.

The operation of the solid-state imaging device 1 as described above is performed by the drive circuit device 6.
It is controlled by a control signal 11 from.

Said 1st. The second pixel signals 9 and 10 are analog signals. Pixel signal 9. 1oil: An analog to digital conversion is performed by the A/D converter 2, and a digital pixel signal 12 is obtained. The digital pixel signal 12 is applied to a digital video signal processing device 3 and becomes a digital video signal 13. Furthermore, the digital pixel signal 12 is applied to a digital color signal processing device 4 to become a first digital color difference signal 14 and a second digital color difference signal 15.

The digital video signal 13 and the first . The second digital color difference signal 14 , 15 is converted into a standard color television signal 16 by a standard color television signal synthesis device 6 . Two independent color difference signals and one video signal are the essential elements of a standard color television signal synthesis system.

Note that the A/D conversion device 2. Digital video signal processing device 3. The digital color signal processing device 4 is activated by the control pulse signals 18, 19, and 20 generated by the control circuit device 7 which receives the control signal 17 from the drive circuit device 6. 6
The configuration is such that each control pulse signal 21 is controlled by a control pulse signal 21 that is generated.

As described above, a completely new color camera device has been realized by digitizing the video signal and color signal detection sections, which are the main signal processing sections of the color camera device.

FIG. 2 is a block diagram of a color camera device according to an embodiment of the present invention, in which the digital color signal processing device 4
and the digital video signal processing device 3 are shown in more detail. In the figure, the digital color signal processing device 4 includes a digital white balance circuit 22 . It consists of a digital one horizontal scanning period (1H) memory circuit 23, a first digital color difference signal processing circuit 24, a second digital color difference signal processing circuit 25, and a digital color difference signal switching circuit 26. The digital pixel signal 12 that has been A/D converted by the A/D converter 12 passes through the digital white balance circuit 22 to become a digital pixel signal 27 whose white balance has been corrected. This digital pixel signal 27 is transmitted during one digital horizontal scanning period (
1H) By passing through the memory circuit 23, the digital pixel signal 28 is delayed by one horizontal period. Therefore, the digital pixel signals 27 and 28 in a certain horizontal scanning period
When compared, if the digital pixel signal 27 is composed of the information of the first pixel signal 9, the digital pixel signal 28 is composed of the information of the second pixel signal 1o, and the following During the horizontal scanning period, the above relationship is reversed.

In this way, the two systems of digital pixel signals 27°28 are
This is essential for realizing independent first and second digital color difference signals 14.15. The digital pixel signal 27 passes through a first digital color difference signal processing circuit to generate a digital color difference signal 29 that repeats the information of the first pixel signal 9 and the second pixel signal 1o for each horizontal scan. becomes. Similarly, the digital pixel signal 28 passes through the second digital color difference signal processing circuit 25, so that the information of the second pixel signal 10 and the first pixel signal 9 is repeated for every horizontal scan. A digital color difference signal 3o is obtained, and the overall time relationship is delayed by one horizontal scanning period. For every horizontal scanning period,
A digital color difference signal consisting of the first pixel signal 9 included in the digital color difference signal 29 and a digital color difference signal 3
If the digital color difference signal consisting of the first pixel signal 9 included in o is selected and switched by the digital color difference signal switching circuit 26, the first pixel signal having the first pixel signal information 9 in all horizontal scanning periods can be selected and switched. independent digital color difference signals 14 can be generated.

Similarly, the digital color difference signal consisting of the second pixel signal 10 included in the digital color difference signal 29 and the digital color difference signal consisting of the second pixel signal 10 included in the digital color difference signal 3o are transferred to the digital color difference signal switching circuit 20.
If selected and switched, a second independent digital color difference signal 16 having the second pixel signal information 1o in all horizontal scanning periods can be generated.

As described above, the digital white balance circuit 2
2. Digital one water scanning period memory circuit 23. A digital color signal processing device 4 can be realized by the first and second digital color difference signal processing circuits 24 and 25 and the digital color difference signal switching circuit 26.

The digital video signal processing device 3 includes a digital video signal processing circuit 31 and a digital gamma (γ) correction circuit 32.
and a digital delay circuit 33. The digital pixel signal 27 is supplied to a digital video signal processing circuit 31 and becomes a digital video signal 34. It should also be noted that when improving the image quality of a video signal (monochrome image) in the vertical direction, the digital pixel signal 28 is supplied to the digital video signal processing circuit 31.

The digital pixel signal 34 is sent to the digital delay circuit 3.
The signal 35 delayed by 3 is further passed through the digital gamma correction circuit 32, that is, becomes the digital video signal 13. Note that the digital delay circuit 33 is configured to output the digital video signal 13 and the first . Second
The purpose is to correct the relative time delay between the digital color difference signals 14, 15 of the first . Second digital color difference signal 1
4.15 is generated because the digital pixel signal 27 is derived and passed through different time processing systems. Therefore, it should be noted that in some cases, it is necessary to use a delay circuit that delays the digital color difference signals 14 and 15. From this point of view, the delay circuit 33 is not included in the basic components of the digital video signal processing device 3.

As described above, the digital video signal processing circuit 31
The digital video signal processing device 3 is composed of a digital gamma correction circuit 32 and a digital delay circuit 33, but in the future, the optical signal versus electrical output signal characteristics of solid-state imaging devices will be improved and gamma correction will no longer be necessary. For example, a digital video signal processing device 3 from which the digital gamma correction circuit 32 is removed may be used.

FIG. 3 is a block diagram of a color camera device according to another embodiment of the present invention, showing another example of the configuration of the digital color difference signal processing device 4. In FIG. Therefore, in FIG. 3, the configuration other than the internal configuration of the digital color difference signal processing device 4 is the same as the configuration example shown in FIG. 2.

In FIG. 3, the digital color difference signal processing device 4 includes a digital 1 horizontal scanning memory circuit 23, a first digital color difference signal processing circuit 24, a second digital color difference signal processing circuit 25, and a digital color difference signal switching circuit 26. and,
It consists of a digital white balance circuit 4o. The configuration differs from that of the digital color difference signal processing circuit 4 shown in FIG. 2 in that the digital white balance circuit 40 is placed next to the digital color difference signal switching circuit 26. Therefore, the digital pixel signal 37 which is the output of the memory circuit 23 for one digital horizontal scanning period is the digital pixel signal 28 and the first digital color difference signal processing circuit 2.
The digital color difference signal 38 which is the output of the second digital color difference signal processing circuit 25 is combined with the digital color difference signal 29, and the digital color difference signal 39 which is the output of the second digital color difference signal processing circuit 25 is combined with the digital color difference signal 30 and the digital color difference signal switching circuit 26. The first output is the output of . Second digital color difference signal 42
．． 43 respectively represent the first. second digital signal 1
4.15, basically "except for the fact that white balance correction is not done."

It is clear that they each have the same signal configuration.

The first digital color difference signal 42 without white balance correction has the first pixel information 9 in all horizontal scanning periods, and the second digital color difference signal 43 without white balance correction also has the first pixel information 9 in all horizontal scanning periods. has the second pixel information 10 in all horizontal scanning periods. These first and second digital color difference signals 42.
43 passes through the digital white balance circuit 4o,
Said 1st. The second digital color difference signal becomes 14.15.

As described above, the digital white balance circuit 4
It is possible to realize a digital color signal processing device 4 in which 0 is arranged at the next stage of the digital color difference signal switching circuit 26.

FIG. 4 is a schematic configuration diagram of main parts showing an example of a solid-state imaging device used in a color camera device of the present invention. In this example, as an example of the light-receiving surface of the solid-state imaging device 1, magenta) 2 green 0. An optical filter of either Cyan (Cl) or Yellow (7) was attached as shown in FIG.

MOS (Metal Oxide Semi'co
An array of pixels 44 to 79 each consisting of a photodiode having a structure (inductor) is presented. The arrangement of pixels 44 to 79 in FIG. 4 is abbreviated and is actually a two-dimensional arrangement consisting of several hundred pixels in the horizontal direction and several hundred in the vertical direction. A certain 1 is determined by the control signal 11 from the drive circuit device 6.
When a row of pixels 44 to 49 is selected at the start of the horizontal scanning period H1, pixels 44, 46, 48, etc. having magenta (hereinafter abbreviated as M) signal information are read out in the first horizontal direction C0D. (Charge Capsid Device) Pixels 45, 47, .
49, etc. are transferred in parallel to the second horizontal reading COD shift register 83, and sequentially over the one horizontal scanning period H1.

, respectively with a repetition period of 1/f from terminals 84 and 85
.

is output. At the start of the next horizontal scanning period H2, the row of 2 pixels 5o to 65 is selected, so Sian (hereinafter referred to as
Pixels 50, 62, 54 having signal information (abbreviated as C)
etc. are transferred in parallel to the first horizontal readout COD shift register 82, and yellow (hereinafter abbreviated as Y) signal information etc. are transferred in parallel to the second horizontal readout COD shift register 83. The signals are sequentially outputted from terminals 84 and 85 at a repetition period of 1/fc over one horizontal scanning period H2. Thereafter, for each horizontal scan, pixels 66 to 619, pixels 62 to 67, pixels 68 to 73
．． The arrangement group of pixels 74-79 is repeated, and this repetition constitutes one field period. For one frame period, this one field period may be repeated, or the pixel column may be interlaced scanned every other row.

As is clear from the above explanation, a certain horizontal scanning period H1
, the M signal information is output to the terminal 84 and the C signal information is output to the terminal 85. In the next horizontal scanning period H2, the C signal information is output to the terminal 84.
C signal information is outputted to the terminal 85, and these signals are alternately repeated every horizontal scanning period to realize the functions of the solid-state imaging device 1. Further, the output mode of the first horizontal reading COD shift register 82 and the output mode of the second horizontal reading COD shift register 83 are maintained in an opposite phase relationship within the repetition period 1/fo. . In this way, it is possible to realize the alternating repetition of M signal information and C signal information, and the alternating repetition of C signal information and Y signal information.In one horizontal period H1, M,
A first pixel signal 9 consisting of repeating different color signals such as G, M, G, . . . is obtained, and the next pixel signal 9 is obtained.
In the horizontal period H2, a second pixel signal 1o is obtained, which consists of repeating different color signals alternately, such as C9Y, C, Y, . . . .

FIG. 6 shows the output terminal 84 of the solid-state imaging device 1 shown in FIG.
A portion of one horizontal scanning period H1 with the first pixel signal 9 outputted from the output terminal 85, and the second pixel signal outputted more than the output terminal 85.
The output waveforms of analog discrete values each showing an enlarged portion of one horizontal scanning period H2 of the pixel signal 1o, and these pixel signals 9°10 are analog-to-digital converted to become digital pixel signals 12a and 12b.A 3 shows operating waveforms of the /D converter 2.

6(=) and (b) show two different embodiments of the A/D converter 2. In FIG. Below, Figure 6 and 6
A specific configuration example and operation of the A/D conversion device will be described with reference to the drawings.

Since the solid-state imaging device 1 illustrated in FIG. 4 has two output terminals 84 and 85, it is first necessary to combine these two systems of pixel signals 9 and 1o into one system. Therefore, as an example of the configuration of an A/D converter, the configuration shown in FIG.
) and the one shown in FIG. 6(b).

First, in FIG. 6(a), the A/D converter 2.

It consists of an A/D conversion circuit 96 and a two-manufacturer, one-output type analog switch circuit 95. Since the solid-state imaging device 1 outputs the first pixel signal 9 within one horizontal scanning period H1,
9M signal information columns 86a to 86e appear at the terminal 84,
C signal information column 87 with 1800 phase shift to terminal 86
a to 87e appear. Timing period 9 shown in FIG.
At 8a to 98e, if the pulse train 91 is applied to the terminal 93 and the analog switch circuit 96 is made conductive to the terminal 84 side, the M signal information train 86a to 86e can be selected as the converted input of the A/D conversion circuit 96. , if the pulse train 90 is simultaneously applied to the conversion timing pulse input terminal 97 of the A/D conversion circuit 96, within the timing period 98a-98e (i.e., 1/fo).

The M signal information sequences 86a to 86e are A/D converted.

Next, during timing periods 99a-99e, pulse train 92 is applied to terminal 94, and analog switch circuit 96
If conductive to the terminal 86 side, the C signal information sequences 87a to 87e can be selected as the converted inputs of the A/D conversion circuit 96, and at the same time, the pulse sequence 90 can be connected to the conversion timing pulse input terminal 97 of the A/D conversion circuit 96. , the C signal information sequences 87a-87e are A/D converted within the timing periods 99a-99e.

In this way, within one horizontal scanning period H1,
The analog switch circuit 96 has a repetition period of 2/f.
o, the A/D conversion circuit 96 is opened and closed so as to alternately conduct one of the two input terminals 93 and 94, and the A/D conversion circuit 96 is connected at a repeating period 1/fc that is Z times synchronized with this opening and closing period. Since the 9M signal information strings 86a to 86e and the C signal information strings 87a to 87e can be synthesized in time series and analog-to-digital conversion can be performed at the same time, as a result, the above-mentioned A/
A digital pixel signal 12a is output to an output terminal 100a of the D conversion circuit 96.

Within the next horizontal scanning period H2, the solid-state imaging device 1
Since the pixel signal 10 is outputted, if the same operating principle as described above is applied to this, the C signal information strings 88a to 88e and the Y signal information strings 89a to 89e can be time-series synthesized and analog-digital converted.

A digital pixel signal 12b is output to the digital output terminal 100a.

In addition, in FIG. 5, signals 101, 102°, 103.
104 are digitized M signals, C signals,
Assume that the signals represent C and Y signals.

As described above, A/D converter color 2 can be realized by the analog switch circuit 96 and the digital converter circuit 96. Still, the control pulse signal 18 of the A/D converter 2 shown in FIGS. 1 to 3 corresponds to the pulse train 90 in the above embodiment.

In FIG. 6(b) which is the second embodiment, the A/D conversion device w2 includes a first A/D conversion circuit 104 and a second A/D conversion circuit 104.
Conversion circuit 106. First digital launch circuit 106.
The output terminal of the first A/D conversion circuit 104 is connected to the first digital latch circuit 106, and the output terminal of the second A/D conversion circuit 106 is connected to the second digital latch circuit 107. The output terminals of the first and second digital latch circuits 106 and 107 are connected in common to the latch circuit 107, and the operation timing of the first A/D conversion circuit 104 and the first digital latch circuit 106 is The operation timings of the second A/D conversion circuit 105 and the second digital latch circuit 107 are configured to be opposite to each other.

The operation will be explained below. Within one horizontal scanning period H1, the solid-state imaging device 1 outputs the pixel number η 9, so the M signal information columns 86a to 86e appear at the terminal 84, and the C signal information whose phase is shifted by 1800 appears at the terminal 85. Columns 87a-87e appear. Timing period 98a-9
8e, when the pulse train 91 is applied to the terminal 108, the M signal information trains 86a to 86e are transferred to the A/D converter circuit 108.
Analog → digital conversion is performed at 4, timing period 9
Minute time td from 8a to 98e (however, 1/fo>>
td), the first digital latch circuit 106
The signal is latched up and output to the digital output terminal 10ob. At this time, the second digital latch circuit 10
7 is output open.

Next, in the timing period 99a to 99e, when the pulse train 92 is applied to the terminal 109, the G signal information train 87a
-87e is analog-to-digital converted by the A/D conversion circuit 105, and after a minute time (td) delay from the timing period 99a to 99e, the second digital latch circuit 10
7 and is output to the digital output terminal 1oob.

At this time, the output of the first digital latch circuit 106 is open. In this way, the outputs of the first digital latch circuit 106 and the second digital latch circuit 107 are connected in common, and the outputs of the first digital latch circuit 106
and the second digital output terminal, so that the pixel signal 9
The M signal information columns 86a to 86e and the G signal information columns 87a to 87e, which are the constituent elements of the first . Common output terminal 100b of second digital latch circuits 106 and 107
A digital signal 12a can be outputted to.

Within the next horizontal scanning period H2, the solid-state imaging device 1
By outputting the pixel signal 1o and applying the same operating principle as above, the C signal information strings 88a to 88e and the Y signal information strings 89a to 89e can be time-series synthesized and analog-to-digital converted. A digital pixel signal 12b can be output to the output terminal 100b.

As described above, the functions of the A/D conversion device 2 can be realized by the two A/D conversion circuits and the two digital latch circuits. In the above embodiment, the pulse train 91 and the pulse train 92 correspond to the control pulse signal 18 of the A/D converter 2 shown in FIGS. 1 to 3.

To summarize the advantages and disadvantages of the two embodiments shown in FIGS. 6(a) and 6(b) above, in the embodiment of FIG. 6(a),
Only one A/D conversion circuit is required, but the A/D conversion cycle is 1/1.
It is fc. On the other hand, in the embodiment shown in FIG. 6(b), the A/D
Two conversion circuits are required, but the conversion period is twice 2/f.
o, and can be implemented using an A/D conversion circuit with half the conversion speed as compared to the embodiment shown in FIG. 6(-).

Here, if fC=14.4 is selected, in the embodiment of FIG. 6(b), the conversion speed of the A/D converter is 7.2 h
Furthermore, if fc=7.2hl&, the conversion speed becomes 3.581h. Effectively reducing the conversion speed of A/D conversion circuits is a very important issue from the viewpoint of reducing power consumption of color camera devices and integrating A/D conversion circuits and signal processing circuits. In this sense, the embodiment shown in FIG. 6(b) is considered to be particularly effective.

FIG. 7 shows a 24°260 block configuration diagram of the digital color difference signal processing circuit, FIG. 8 is a specific circuit configuration diagram of the main part thereof, and FIG. 9 is a diagram for explaining the operation of the embodiment. It shows an example of a signal time chart and a configuration of input/output digital data.

The configuration and operation of the digital color difference signal processing circuits 24 and 25 will be described below with reference to FIGS. 7, 8, and 9.

In FIG. 7, the digital color difference signal processing circuit 24.2
6 is a 1-pixel shift circuit 110 and a 1-pixel inversion circuit 11
1, a digital addition circuit 112, an input signal 113 of the 1-pixel shift circuit 110, and a 1-pixel inversion circuit 111.
The output signal 116 is applied to the digital adder circuit 112. The purpose of operation of the digital color difference signal processing circuits 24 and 26 is as follows: - When the circumferential imaging device 1 shown in FIG.
, M, G, ... or C, Y, C, Y.

...) digital pixel signals 12, 27 consisting of
゜28 or 37 is used as the input signal 113, and the color difference signal time series (MG, MG, MG,... or C-Y, C-Y, C-Y... ) is converted into a digital color difference signal 29, 30, 38 or 39 and output.

The 1-pixel shift circuit 110 discriminates between the digital M signal and the digital G signal, and shifts only the digital G signal by 1 bit time. In this way, the shifted digital G signal is inverted by the 9th one-pixel inverting circuit 111 to become a digital-G signal. When the digital M signal and the digital -〇 signal are added to the digital adder circuit 112, the M
-G.

It can be converted into a digital color difference signal consisting of M-G... If the digital M signal is regarded as a digital C signal and the digital C signal is regarded as a digital Y signal, digital color difference signals consisting of CY, CY, CY, old, etc. can be obtained in the same way. Still, digital M
The relationship between signals and digital C signals, or digital C signals
Reverse the relationship between the signal and Y signal, G-M, G-M...
. . , or Y-C, Y-C, . . . It is of course possible to use a digital color difference signal. The digital color difference signal processing circuits 24 and 26 can be configured as described above.

In FIG. 8, the one-pixel shift circuit 110 includes a first digital latch circuit 117. Second digital latch circuit 118. Third digital latch circuit 119 and D
It consists of a flip-flop circuit 120, the one-pixel inverting circuit 111 is not a digital inverter circuit 121, and the digital pixel signal 12, 27, 28 or 38 is applied to the input part of the first digital latch circuit 1170, and the repetition period is 1. /f0, and this latch-up output is sent to the second and third digital latch circuits 118, 119 and the D flip-flop circuit 120.
The third latch circuit 119 is selectively distributed and controlled based on the timing of the repetition period configured by the third latch circuit 119.
The output of is applied to the digital inverter circuit 121,
The output of the digital inverter circuit 121 and the second
The output of the digital latch circuit 118 is applied to the digital adder circuit 112.

Next, the operation of the circuit shown in FIG. 8 will be explained in detail with reference to FIG. 9. Digital pixel signals 12a, that is, M and G during one horizontal scanning period H1.

When a digital pixel signal consisting of M, G, . . . 1 digital latch circuit 11
7 outputs digital M signal information 1o1.7 sequentially with a repetition period of 1/fC. Digital G signal information 102.
Digital M signal information... is latched up. At the same time, the Q output terminal of the D flip 70 tube circuit 120 receives a pulse train 126, and the output terminal receives a pulse train 12.
7 occurs. The pulse train 126 moves the second digital latch-up circuit 118 at timings 128a to 128 as indicated by arrows.
Since latch-up occurs at e, only this digital latch-up digital M signal information 130 can be selectively latch-up.

On the other hand, since the pulse train 127 latches up the third digital latch-up circuit 119 at the timings 129a to 129d indicated by the arrows, this Lanocia digital C signal information 131 can be selectively latched up. Furthermore, digital M signal information 130 and digital C signal information 13
1 has a relative phase shift of 1/fo in one pixel period. This is a one-pixel shift operation. The digital C signal information 131 is latch-up outputted to the third digital latch-up circuit 119, inverted by the digital inverter circuit 121, and output to the digital C signal G.
The signal information 132 is output. When the digital M signal information 130 and the digital-G signal information 132 are added in the digital adder circuit 112 in this way, a digital color difference signal output 116 consisting of a (MG) pulse train is obtained at its output section. This output signal 116 corresponds to the digital color difference signal 29, 30, 38 or 39. Similarly, the input signals 113 of the first digital latch circuit 117 are C, Y, and C.

By adding the digital pixel signal 12b consisting of Y..., a digital color difference signal output consisting of a (cy) pulse train can be obtained at the output section of the digital addition circuit 112. In addition, in FIG. 8, a pulse train 123 with a repetition period of 1/fo applied to the terminal 122,
The synchronizing pulse train repeated in one horizontal scanning period, which is applied to the terminal 113 to reset the entire digital color difference signal processing circuit system in FIG. 8, corresponds to the control pulse signals 20b and 20c shown in FIGS. 1 to 3. . Also, 1st degree, 2nd degree. Third digital latch circuit 117, 118
At 119, signal C' indicates a clock input terminal for controlling latte-up. Furthermore, in Figure 8,
Digital inverter circuit 121 and digital addition circuit 112 can be considered as one digital subtraction circuit.

FIG. 10 shows an example of the configuration of the digital one horizontal scanning period memory circuit 23, and FIG. 11 shows a time chart and input/output digital data for explaining its operation. The structure and operation of the digital one horizontal scanning period memory circuit 23 will be described below with reference to FIGS. 10 and 11.

In FIG. 10, the digital 1 horizontal scanning period memory circuit 23 includes a second digital latch circuit 134 and a third digital latch circuit 134.
It consists of a digital latch circuit 136, a random access memory circuit 136, an address counter circuit 137, and a timing pulse generation circuit 144. Furthermore, in this embodiment, the timing pulse generation circuit 144 includes two D
The circuit includes one flip-flop circuit 138, 139 and four NOR circuits 140-143. The first digital latch circuit 146 and the fourth digital latch circuit 146 are connected to the memory circuit 23 for one horizontal scanning period, respectively.
This is an input/output interface circuit. Note that in the following explanation, digital pixel signals are treated as parallel input/output data.

In FIG. 10, the repetition frequency is 2f at terminal 147.
A timing clock pulse of o is applied to terminal 14.
8, for each 1 horizontal period (1H), D-n lip 70
Tube circuits 138, 139 and address counter circuit 1
When a synchronization pulse is applied that resets 37,
A pulse train 153 with a repetition period of 1/f is generated at the Q terminal of the first D flip-flop circuit 138, starting from timing 162a when the repetition period is reset at 1H.
The ◇ terminal of 8 has a repetition period of 1/1, starting at timing 162b when the repetition period is reset at 1H.
A pulse train 164 of fo is generated, and a pulse train 166 of a repetition period of 1/fo is generated at the Q terminal of the second D flip-flop circuit 139, starting at timing 162C when the repetition period is reset at 1H. . In addition, the pulse train 153 and the pulse train 166 are connected to terminals 149 and 1.
When NOR circuits 142 and 143 are passed through 50,
A write control pulse train 167 for the random access memory circuit 136 is generated at a terminal 166 .

Next, the above pulse trains 153, 164 and pulse train 1
Writing and reading to and from the random access memory circuit 136 will be explained using 67. Timing 152a, 1
At 52b and 152d, the pulse trains 163, 154, and 157 are reset, and at the same time, the address counter circuit 137 is also reset via the terminal 148. timing 15
At 8a, the pulse train 163 causes the address counter circuit 137 to set the first valid address data 169a. This address data 159a is sent to the random access memory circuit 1 via the parallel data port 160.
36 addressing circuits, so pulse train 1
When pulse train 167 is at a logic high level, the data state of the random access memory circuit 136 becomes valid read data 161, and when pulse train 167 is at a logic zero (L) level, the data state of the random access memory circuit 136 becomes valid write data 162. .

On the other hand, at timing 163a of pulse train 164.

A third digital latch circuit 134 latches up and is coupled to the output of the random access memory circuit 136. Over the period 164, this latch-up period 166 and the period of existence of the valid read data 161 overlap, so that the first
The valid read data 161 existing at the th address from one horizontal scanning period ago is as shown by an arrow 167.
The valid output data 170a is held in the third digital latch circuit 136 for nine periods 166. Similarly, at the timing 163a of the pulse train 164, the second
The digital latch circuit 134 becomes a latch amplifier,
Input data 171a held in the first digital latch circuit 146 is transferred to the second digital launch circuit 134 as indicated by an arrow 172 and held as valid input data 169a. Over a period 166, the period 166 for holding this valid input data overlaps with the period of existence of the valid write data 162, so this valid input data 1e9aij is stored in the first position of the random access memory circuit 136 as shown by an arrow 168. to the address of
It is stored as write data 162. This new write data 162 is stored as read data until the next horizontal scanning period arrives and the first address is designated again.

As is clear from the above description of each operation related to the first address, the second address data 169b of the random access memory circuit 136 can be specified at timing 168b, and at timing 163b.

Valid output data 170b can be output to the third digital ratte circuit 135 and valid input data 169b can be input to the random access memory circuit 136. below,
1 of the digital pixel signal 12 or 27 by sequentially updating the address at a timing repeated at a period of 1/fo during the pulse trains 153, 154, 157.
Pixel information over a horizontal scan period can be simultaneously read and written via the random access memory circuit 136.

As described above, the random access memory circuit 136
The digital one horizontal scanning period memory circuit 23 can be realized from the address counter circuit 137, the second and third digital latch circuits 134 and 135, and the timing pulse generation circuit 144. Note that the first digital latch circuit 146 and the fourth digital latch circuit 146 are driven by the pulse train 153, whereas the second digital latch circuit 134 and the third digital latch circuit 135 are driven by the pulse train 164. , respectively configured as input and output interface circuits.

In particular, the fourth digital latch circuit 146 can share the function of the first digital circuit 117 of the digital color difference signal processing circuit 24 or 26 shown in FIG. Also,
In the configuration of the color camera device shown in FIG. 2, the first digital latch circuit 145 can also be regarded as a digital vanguard circuit that connects the digital white balance circuit 22, the digital 1 horizontal scanning period memory circuit 23, and the digital white balance circuit 22. Furthermore, in the configuration of the color camera device shown in FIG. 3, it may be regarded as a digital converter circuit that connects the A/D converter 2 and the digital one horizontal scanning period memory circuit 23.

As an example of the memory capacity of the random access memory circuit 136, the repetition frequency fc of pixel information is 7.2vik (
If the color burst signal modulation frequency is selected, approximately 40
The memory capacity is approximately 0 address x 8 bits. In addition,
For convenience of explanation, the number of bits of digital data for one pixel is assumed to be 8 here, but it is not necessarily limited to this value.

The timing pulse generation circuit 144 shown in FIG.
In this embodiment, two D flip 70 tube circuits 138,1
Although the configuration is made up of 39 and 4 (7) NOR circuits 140 to 143, the configuration is not necessarily limited to this configuration as long as various timing pulse trains as shown in FIG. 11 are realized. In addition, in Fig. 10, the terminal 14
7 and a timing clock pulse of repetition frequency 2fo applied to terminal 148 and repetition period 1H applied to terminal 148.
The synchronizing pulse corresponds to the control pulse signal 20a shown in FIGS. 2 and 3.

FIG. 12 shows another embodiment of the digital one horizontal scanning period memory circuit 23. This digital 1 horizontal scanning period memory circuit 23 stores digital pixel signals 12.2
7 as an input signal consisting of N bits in parallel, it can be constituted by a parallel digital shift register with M transfer stages of N-bit parallel type.

Hereinafter, the explanation will be developed assuming that N=s bits. Taking the case of an NTSC television signal as an example, one horizontal scanning period (
IH) and color burst signal conversion frequency fb key 3.68
What is the relationship between meters?

It is determined by. On the other hand, the 8-pit parallel digital shift registers 173 to 180 have a frequency f per pixel.

If the data is transferred as follows, the number of stages M required for each bit of the parallel digital shift registers 173 to 180 is as follows.

becomes. Therefore, f =7.2I/! If h is selected, M=455 bits; if lfo=14.4 is selected, M=910 pintos. In this way, as fc, f
If an integer multiple of b is selected, M becomes an integer, and actual parallel digital shift registers 173 to 180 can be constructed. To summarize, when fo = 7.2, the number of stages M =
455 stages x 8 bit parallel, for fo=14.4,
In this case, it is sufficient to configure parallel digital shift registers 173 to 180 in which the number of stages is M=910×8 bits in parallel. In FIG. 12, parallel digital shift registers 173 to 180 perform parallel transfer at a common transfer lock pulse frequency fc. This clock pulse frequency f.

is Figure 2.

The control pulse signal 20 a i/i shown in FIG. 3 corresponds accordingly. Note that the first digital latch circuit 146 and the fourth digital latch circuit 146 shown in FIG. May be connected.

As described above, the memory circuit 23 for one horizontal scanning period can be realized by using a plurality of digital shift registers arranged in parallel with a transfer lock pulse having a repetition frequency f0 that is continuously applied.

FIG. 13 shows an embodiment of the digital color difference signal switching circuit 26, in which the first digital latch circuit 181.
Second digital latch circuit 182. Third digital latch circuit 183. Fourth digital latch circuit 184
The input parts of the first digital latch circuit 181 and the second digital latch circuit 182 are commonly connected, and the input parts of the third digital latch circuit 183 and the fourth digital latch circuit 1840 are commonly connected. The output parts of the first digital latch circuit 181 and the third digital latch circuit 183 are connected in common, and the output parts of the second digital latch circuit 182 and the fourth digital latch circuit 184 are connected in common. , the output gate switching timing of the first and fourth digital latch circuits 181 and 184 and the second and third digital latch circuits 18
The 2,183 output gate switching timings are configured to be opposite to each other in synchronization with the horizontal scanning period.

FIG. 14 shows the digital color difference signal processing circuits 24 and 2.
6, and the digital color difference signal switching circuit 2
A digital color difference signal 29.30 serving as an input signal of 6,
The relationship between the digital color difference signals 14°15, which are the output signals of the digital color difference signal processing circuit 26, is expressed as follows:
It is expressed by repeating 1H). Below, the 14th
The operation of the digital color difference signal switching circuit 26 shown in FIG. 13 will be explained with reference to the drawings. From FIG. 14, the digital color difference signals 29 and 30 are digital (M-
G) A color difference signal sequence and a digital (C-Y) color difference signal sequence are repeated, and the information contents such as (,MG) information or (C-Y) information are mutually inverted.

From these digital color difference signals 29 and 30, a digital color difference signal 14 having only a digital (MG) color difference signal train in all horizontal scanning periods, and a digital (C-Y
) The purpose of the digital color difference signal is to create a digital color difference signal 16 having only a color difference signal sequence in all horizontal scanning periods. The digital color difference signal 29 is transmitted to the first digital latch circuit 181 and the second digital latch circuit 18.
2, and a digital color difference signal 30 is applied to the third input.
When a switching timing pulse 186 with a repetition period of 2H is applied to the input parts of the digital latch circuit 183 and the fourth digital latch circuit 184 through the terminal 185, the first digital latch A timing pulse 187 is applied to the output gate CG of the circuit 181 to bring it into a conductive state, and a timing pulse 186 is applied to the output gate CG of the third digital latch circuit 183 to bring it into a cutoff state.
Digital (MG) information 29a/Ig1 digital latch circuit 181 and third digital latch circuit 183
is output to the common output terminal 189 of the second digital latch circuit 18 at the same time in one horizontal scanning period 188a.
A timing pulse 186 is applied to the output gate CG of the fourth digital latch circuit 1, and the output gate CG of the fourth digital latch circuit 1 is cut off.
84 output game) Timing pulse 187-f for CG
i is added and becomes conductive, so digital (C-Y
) Information 30a is the common output terminal 19 of the second digital latch circuit 182 and the fourth digital latch circuit 184
Output to 0. Similarly, timing pulse 186
, 187, the first digital latch circuit 1
Since the output gate CG of the third digital latch circuit 81 is cut off and the output gate CG of the third digital latch circuit 183 is turned on, the digital (MG) information 30b is output to the common output terminal 189, and at the same time, the second digital latch circuit 183 is output to the common output terminal 189. circuit 182
Since the output gate CG of the fourth digital latch circuit 184 is conductive and the output gate CG of the fourth digital latch circuit 184 is cut off, the digital (cy) information 29b is output to the common output terminal 190. Hereinafter, as shown by the dotted line 196 in FIG. 14, the digital MG information 29a, 30b, 29c,
0d .
6, digital (cy) information 30a.

29b, 30C929d, . . . are selected and output to the common output terminal 190, and become the digital color difference signal 16. Still, the digital color difference signal 29.30 has a repetition period of 1/fo within one horizontal scanning period.
Since the pixel information is 1. 2nd゜3rd. The fourth digital latch circuits 181 to 184 perform a latch-up operation by supplying a clock pulse with a repetition period of 1/fo from the terminal 197 to each clock gate, and the digital color difference signal processing circuits 24 and 25 perform a latch-up operation. is configured to synchronize. Here, a timing pulse train 186 with a repetition period of 2H is applied to the terminal 185.
and the above clock pulse applied to terminal 197 is
This corresponds to the control pulse signal 2od in FIG.

In FIG. 14, the digital color difference signal 29 is a digital color difference signal 38, the digital color difference signal 30 is a digital color difference signal 39, the digital color difference signal 14 is a digital color difference signal 42, and the digital color difference signal 15 is a digital color difference signal 43. In other words, in exactly the same way, the thirteenth embodiment of the digital color difference signal switching circuit 26 constituting the Tacolor camera device shown in FIG.
The configuration shown in the figure can be applied in the same way.

As described above, the digital color difference signal switching circuit 26 shown in FIGS. 2 and 3 can be realized using a digital latch circuit.

FIG. 16(a) is a block diagram showing a configuration example of the digital video signal processing device 31, respectively.

In the present invention, as shown in FIG. 4 as an embodiment of the solid-state imaging device 1, the color filters include magenta M, magenta M,
By selecting a filter array consisting of green G, cyan C, and yellow Y, M.

A means for generating a digital pixel signal 12a consisting of G, M, Ci, . . . and a digital pixel signal 12b consisting of C, Y, C, Y, . . . is presented, and the reason thereof is as follows. This is because the sum of the magenta M signal and the green G signal (M + G) and the sum of the green C signal and the yellow signal (C+Y) can be made equal to the video (white) signal y. That is, Y=M+G (3) y=
The optical sensitivity of the color filter is selected so that C+ Y (4). Therefore, from the digital pixel signal 12, the digital image (white)
The operating functions forming the signal 34 are M, G, M,
G-i or c, y.

MUG, M+ci from the digital signal string consisting of C9Y
, MUG or C+ Y , C+ Y , C+ Y
If the video signal correction circuit 198 executes the operational function of forming a digital signal string consisting of the following, the function of the video signal processing circuit 310 can basically be achieved. An example of this configuration is shown in Figure 15 (
a).

The digital video signal processing circuit 31 illustrated in FIG. 16(b) is composed of a first video signal correction circuit 199, a second video signal correction circuit 200, and an averaging circuit 203. The digital pixel signal 12 or 27 is applied to the first video signal correction circuit 199, and the above formula (3), (4
) Digital addition is performed as shown in (). It's Kade, 1
The digital pixel signal 28 or 37 delayed by one horizontal scanning period by the horizontal scanning period memory circuit 23 is applied to the second video signal correction circuit 200, and Equations (3) and (4)
A digital addition operation as shown in is performed. Then, the digital video signals 201 and 202 from the video signal correction circuits 199 and 200 are added and divided by 2 in an averaging circuit 203 to obtain a digital video signal 34 as an output. Digital video signal 3 in this case
4, as is clear from the above configuration, is an image signal in a form in which image information in one horizontal scanning direction is correlated with an image in the next horizontal scanning direction, so the vertical resolution of the television signal is It is possible to achieve the effect of smoothing the image, and the effect of improving image quality can be expected. Furthermore, by including in the averaging circuit 203 a function of varying the addition ratio of the digital video signal 201 and the digital signal 202, it is also possible to adjust the optimum image quality in the vertical direction.

As described above, the digital video signal processing circuit 31 shown in FIG. 15 has the effect of improving image quality in the vertical direction. In Figure 4, M, G, C, and Y colors were selected as the four different color filter configurations, but even if these are replaced with other color filter systems, equations (3) and (4) will still be satisfied. If you want to do it, you can do it in the same way.

FIG. 16 shows the video signal correction circuit 198, 199° 20
FIG. 2 is a block diagram showing a configuration example of 0. This consists of a 1 pixel shift circuit 204 and a digital addition circuit 205.
The functions of 05 are the digital color difference signal processing circuit 2.
The functions are the same as those of the one-pixel shift circuit 110 and digital adder circuit 112, which are the components of 4.25. Therefore, the purpose of the 1 pixel shift circuit 11o is M, G, M.

A row of digital pixel signals 12 consisting of G or C, Y, C, Y, digital G signal or digital Y
This is to selectively time shift only the signal by one bit. The digital C signal or digital Y signal shifted in this way.

Unshifted digital M signal or digital C
If the signal is added with the digital addition circuit 205, MUG
, MUG, MUG,... or C+ Y, C+ Y, C+ Y,...
A digital video signal consisting of... is obtained.

As described above, the digital video signal correction circuits 198, 199, and 200 can be configured by the one-pixel shift circuit 204 and the digital addition circuit 205.

Figure 17 shows the video signal correction circuit 198.199°20.
FIG. 18 shows a time chart and input/output digital data for explaining the operation of this embodiment. 1st
As is clear from a comparison between FIG. 7 and FIG. 8, the circuit shown in FIG. 17 is the circuit from which the digital inverter circuit 121 in FIG. 8 is removed. Therefore, the first digital latch circuit 2o6. in FIG. Second digital latch circuit 207. Third digital latch circuit 2
08. The operation of the D flip Flora 1 circuit 209 is similar to that of the first digital latch circuit 117 .
Second digital latch circuit 118. The operation of the third digital latch circuit 119 is the same as that of the D clip flop circuit 120. That is, when the pulse train 123 with a repetition period of 1/fo is applied to the terminal 210, the pulse train 126 is applied to the Q terminal of the D slip flow loop circuit 209, ◇
A pulse train 127 is generated at the terminal, and by inputting the digital pixel signal 12a to the first digital latch circuit 206, the second digital radial M signal information 130 can be selectively latched up, and the third digital latch circuit In 208, 131 can be selectively latched up, and the digital M signal information 130 and the digital G signal information 131 are relatively phase-shifted by 1/f corresponding to one pixel period.

In this way, if the digital M signal information 130 and the digital G signal information 131 are added by the digital addition circuit 205, the desired M+G, M+G, M+G, etc.
A digital video signal 214 consisting of columns can be obtained. A synchronizing pulse train is still applied to terminal 211, which is repeated nine times in one horizontal scanning period, and this pulse train is applied to reset the entire system. This pulse train and the pulse train 123 correspond to the control pulse 19a shown in FIGS. 2 and 3. In the manner described above, the video signal correction circuits 198, 199, and 200 are realized.

From a comparison between FIG. 17, which is an embodiment of the video signal correction circuit, and FIG. 8, which is an embodiment of the digital color difference signal processing circuit, it is clear that, as discussed above, the circuit means constituting the one-pixel shift circuit consists of three components. They consist of digital latch circuits and have exactly the same operating mode.Moreover, both circuits have digital pixel signals 12, 27, 28, or 37 at their inputs.
is input, the digital color difference signal processing circuit 2
The portion of the one-pixel shift circuit 110 that constitutes 4.25 and the portion of the one-pixel shift circuit 206 that constitutes the video signal correction circuits 198, 199, and 200 can be mutually used as one circuit.

Such sharing is particularly important when the digital video signal processing device 3 and the digital color signal processing device 4 are configured as an integrated digital integrated circuit.

FIG. 19 shows the digital gamma correction circuit 32.

7” read-only memory IJ (ROM) capable of o-gram
Table integrated circuit 215 (e.g. 5N74S471)
This is an example showing that it can be configured with This embodiment shows a case of parallel 8-pit digital input/output. The digital video signal 36 is applied to the parallel 8-bit digital input terminal 216, and the parallel 8-bit digital output terminal 2
A digital video signal 36 is output to 17. An example of the gamma characteristic 218 shown in No. 20 is the analog conversion value E1 of the digit signal applied to the parallel 8-bit digital input terminal 216 and the analog value E1 of the digit signal applied to the parallel 8-bit digital input terminal 216.
17 shows the relationship between the value E2 obtained by converting the digit signal output to the analog signal E2. This gamma characteristic 218 can be changed by rewriting the contents of the ROM table.

As described above, the digital gamma correction circuit 32
This can be realized with read-only memory (ROM), and this RO
If M is a rewritable programmable ROM, the gamma characteristics can be changed using information 19b from an external terminal.

FIG. 21 shows an embodiment of the digital white balance circuit 22 in the color camera device shown in FIG. This digital white balance circuit 22
consists of a digital multiplier circuit 221, first to fourth digital latch circuits 222 to 226, and a digital latch switching circuit 226, and the output terminals of the four digital latch circuits 222 to 226 are connected as a common output bus 233. A digital latch switching circuit 226 is configured to control the latch amplifier timing of the four digital launch circuits 222 to 226. The operation will be explained below when the solid-state imaging device 1 shown in FIG. 4 is used and the digital pixel signal 12 output from the A/D converter 2 is added as an input signal to the digital multiplication circuit 221. Let's do it.

As shown in FIG. 22 (,), in a certain horizontal scanning period H1, the digital pixel signal 12 is magenta M.

This becomes a green G repeating signal. The digital switching circuit 226 latches up the first digital latch circuit 222 at timing 227a and outputs the magenta M signal multiplication term 229 to the common output bus 233, so the digital M signal 234 is multiplied by the digital multiplication circuit 221. A digital M signal 236 is obtained after receiving the multiplication term 229. Similarly, at timing 227b, the second digital latch circuit 223 is latched up and outputs the green G signal multiplication term 230 to the common output bus 233.

The digital C signal 236 is sent to the digital multiplication circuit 221
The digital C signal 2 is multiplied by 9 and receives the multiplication term 230.
It becomes 37.

Hereinafter, digital pixel signals that are repeated as M, G, M, Ci, .
The digital latch circuits 222 and 223 also launch up, as shown in FIG. 22(b).

M, G, M, G,... after a certain multiplication operation.
The digital pixel signal 27 consists of . In the next horizontal scanning period H2, as shown in FIG. 22(a), the digital pixel signal becomes a repeating signal of cyan C and yellow Y, and the third digital latch circuit 224 is latched up at timing 228a. , Sian C.
Signal multiplication term 231 is output to common output bus 233 and digital C signal 238 is output.

Similarly, at timing 228b, the fourth digital latch circuit 225 latches up and outputs the yellow Y signal multiplication term 232 to the common output bus 233, and the digital Y signal 240 is multiplied by the digital multiplication circuit 221. , and is multiplied by a digital multiplier circuit 221, resulting in a digital Y signal 241 that has received a multiplication term 232. Hereinafter, the digital pixel signal that is repeated as C9y, c, y, . Since latch-up occurs, certain multiplication terms 231, 232 as shown in FIG. 22(b)
A digital pixel signal 27 consisting of the received C, Y, C, Y, . . .

As described above, the four digital latch circuits 222 to 2
26 is selected according to the four different digital pixel signals that enter the digital multiplier circuit as an input, and by adding independent multiplication terms 229 to 232, four types of digital pixel signals 2 with white balance correction are generated.
7 can be output to the output of the digital multiplier circuit 221. In addition, in FIG. 2, the control signal 36 applied to the digital white balance circuit 22 is the multiplication term 22.
It consists of digital data 9.230, 231, and 232, signal information with a repetition period of 2H for controlling the digital latch switching circuit 226, and pulse information with a period of 1/f.

FIG. 23 shows an embodiment of the digital wide balance circuit 40 in the color camera device shown in FIG. This digital white balance circuit 4o consists of a first digital multiplication circuit 242 and a second digital multiplication circuit 243, and a digital multiplication term 244. which is a white balance control signal. 245 is configured to be supplied to the multiplication term input terminals of the digital multiplication circuits 242 and 243. Hereinafter, when the solid-state imaging device 1 shown in FIG. Regarding the case where it is input to the digital multiplication circuit 243 of No. 2.

Let's explain its operation.

As shown in FIG. 24(a), in one horizontal scanning period, the digital color difference signal 42 has a repetition period of 1/f.
o is a digital pulse train consisting of M-G, M-G, . . . , and the digital color difference signal 43 is as shown in FIG.
As shown in b), c-y with a repetition period of 1/fc,
This is a digital pulse train consisting of c-y, . These digital color difference signals 42° 43 are applied to a first digital multiplication circuit 242 and a second digital multiplication circuit 243, respectively, and a constant digital multiplication term 24
4 and the digital multiplication term 245, the digital color difference signal 14 and the digital color difference signal as shown in FIG. 16 can be obtained.

The digital color difference signal 14 is a digital multiplication term 244
The digital color difference signal 16 has a digital multiplication term 245 added thereto.

As described above, the digital multiplication circuits 242 and 243
Additionally, since the two independent digital color difference signals can be varied, it is possible to obtain digital color difference signals 14 and 15 with white balance correction.

In addition, in FIG. 3, the control signal 41 applied to the digital white balance circuit 40 is the digital multiplication term 244, 24 consisting of constant digital data.
5, and as a control method, the digital multiplication terms 244, 245 are controlled by a microcomputer.
It is possible to control the value of .

FIG. 26 shows an embodiment of the standard color television signal synthesis device 6 shown in FIGS. 1 to 3, which includes:
First digital-to-analog CD/A) conversion circuit 246
, a second digital-analog (D/A) conversion circuit 247, a color difference signal modulation circuit 248, a third digital-analog (D/A) conversion circuit and synchronization pulse addition circuit 249, and a synthesis circuit 260. Consisting of The operation will be explained below.

The digital color difference signal 14 is input to the first D/A conversion circuit 246.
is applied to generate an analog color difference signal 260. The digital color difference signal 16 is still applied to the second D/A conversion circuit 247, and an analog color difference signal 261 is generated. At this time, a control pulse signal with a repetition period of 1/f for driving the D/A conversion circuits 246 and 247 is applied to the terminal 264. Also, 1st. 2nd D/A
The converter circuits 246 and 247 are connected to the drive circuit arrangement 6 via terminals 252 and 253, respectively, and are provided with blanking pulses that define the vertical and horizontal blanking periods of the television signal, and output flags that define the burst period. pulses are applied and over these periods the first
The analog color difference signals 260 and 261, which are the outputs of the second D/A conversion circuits 246 and 247, are held at constant levels. Next, the analog color difference signals 260 and 261 are applied to a color difference signal modulation circuit 248 and modulated with two independent phase modulation axes to become a color signal 263. Color difference signal modulation circuit 24
8, a blanking pulse that defines the vertical and horizontal blanking periods of the television signal and a burst flag pulse that defines the parsing period are applied via the terminals 262 and 253, and the blanking period of the color signal 263 is and the burst signal addition period. terminal 26
4, a pulsed carrier pulse with a repetition frequency of 3.58M is applied. On the other hand, the third D/A conversion circuit and synchronization pulse addition circuit 249 receives a white level reference signal that defines the black and white level of the video signal at the terminal 266.
Blanking pulses defining vertical and horizontal blanking periods are applied to terminal 67, vertical and horizontal synchronizing pulses are applied to terminal 268, and a control pulse signal with a repetition period of 1/f is applied to terminal 269, respectively, and a digital video signal is input. 13 and generates a black and white standard television signal 262 as an output. The color signal 263 and the monochrome standard television signal 262 are converted into the standard color television signal 16 by the combining circuit 250. It should be noted that a control pulse signal with a repetition period of 1/f is applied to terminals 264 and 269, a planking pulse that specifies the vertical and horizontal blanking periods is applied to terminals 262 and 267, and terminal 253 The burst carrier pulse with a repetition frequency of 3.6811B applied to terminal 264, and the vertical and horizontal synchronization pulses applied to terminal 268 are as follows:
The control shown in FIGS. 1 to 3 corresponds to the pulse signal 21.

As described above, the first step. Second D/A conversion circuit 246
, 247, a third D/A conversion circuit and a synchronization pulse addition circuit 249, a color difference signal modulation circuit 248, and a synthesis circuit 2.
50, a standard color television signal synthesis device 5 can be constructed, but the first and second digital color difference signals 1
4.15 and digital video signal 13 as input,
The means for realizing the standard color television signal synthesis device 6 for obtaining the standard color television signal 16 is not limited to the configuration shown in FIG. 25.

In addition, in the embodiment of the digital signal processing unit of the present invention, the number of data bits of digital data is described as 8, but the present invention is not limited to this value, and may be determined according to the design concept of the entire color camera system. Of course, the clock frequency f can be any value, such as 6 bits or 10 bits. When obtaining an NTSC color television signal as output, 1. f,=7
．． 2 storage or f. Although it is preferable to select = 14.41 &, in other systems, the effects of the present invention can be achieved even if other values are selected as appropriate.

Effects of the Invention As is clear from the above description, one aspect of the present invention is to receive an optical signal and, during a certain horizontal readout scanning period, to synchronize with the readout clock frequency (fo>) and to alternately read different color signals for each pixel. A first pixel signal consisting of repetitions is output, and in synchronization with the readout clock frequency (fo>), the information of the first pixel signal is different from the information of the first pixel signal, and alternately for each pixel in the next horizontal readout scan amount. an imaging device that outputs a second pixel signal consisting of repetitions of different color signals; an A/D conversion device that performs analog-to-digital conversion of the first and second pixel signals output from the imaging device; A
a digital color signal processing device that receives a digital pixel signal output from the /D conversion circuit as an input and outputs two systems of independent first and second digital color difference signals; and a digital color signal processing device that receives the digital pixel signal as an input and outputs a digital video signal. a digital video signal processing device that outputs the first . Second
a standard color television signal synthesis device which inputs digital color difference signals and digital video signals and outputs standard color television signals; a drive circuit device which drives the imaging device; the A/D conversion device; and a digital video signal. It is equipped with a processing device, a digital color signal processing device, and a control circuit device that generates timing pulses to drive a standard color television signal synthesis device, so it is the core of the signal processing section of a color camera device. The digital color signal processing device and the digital video signal processing device can be realized with a new digital circuit, which makes it possible to eliminate the need for adjustment and make the color camera device ultra-compact, which was a limitation in color camera devices using conventional analog signal processing circuits.・It has the advantage of being lighter, more reliable, and lower in price.

Margin below

[Brief explanation of the drawing]

FIG. 1 is a block diagram of main parts showing the basic configuration of a color camera device of the present invention, FIG. 2 is a block diagram of main parts of a color camera device according to an embodiment of the invention, and FIG. FIG. 4 is a block diagram of main parts of a color camera device according to an embodiment, and FIG. 6 is a schematic configuration diagram of an example of an imaging device used in the present invention.
The figure shows the output waveform output from the imaging device in Figure 4 and the operating waveform of the A/D converter that converts the waveform from analog to digital. Figures 6 (a) and (b) show the A/D converter. Main part circuit configuration diagram showing each configuration example of the D conversion device, No. 7
Figure 8 is a block diagram showing a configuration example of a digital color difference signal processing circuit, Figure 8 is a circuit configuration diagram showing a specific example of the main parts of the digital color difference signal processing circuit, and Figure 9 explains the operation of the digital color difference signal processing circuit. FIG. 10 is a block diagram showing a configuration example of a memory circuit for one horizontal scanning period, and FIG. 11 explains the operation of the memory circuit for one horizontal scanning period. FIG. 12 is a block diagram showing another configuration example of a memory circuit for one horizontal scanning period, and FIG. 13 shows a configuration example of a digital color difference signal switching circuit. Block Diagram,
Figure 14 is a signal waveform diagram for explaining the operation of the digital color difference signal switching circuit, and Figures 16 (a) and (b).
16 is a block diagram showing each configuration example of a digital video signal processing device, FIG. 16 is a block diagram showing a configuration example of a digital video signal correction circuit, and FIG. 17 is a block diagram showing a configuration example of a digital video signal correction circuit. Fig. 18 is a time chart and a waveform diagram showing input/output digital data to explain the operation of the digital video signal correction circuit, Fig. 19 is a diagram showing an example of the configuration of the digital gamma correction circuit, and Fig. 20 is its gamma characteristic. 21 is a block diagram showing a configuration example of a digital white balance circuit in the color camera device shown in FIG. 2, and FIG. 22(a)
, (b) is a waveform diagram for explaining its operation, FIG. 23 is a block diagram showing a configuration example of the digital white balance circuit in the color camera device shown in FIG. 3, and FIG.
), (b) is a waveform diagram for explaining its operation, and FIG. 25 is a block diagram showing an example of the configuration of a standard color television signal synthesis device. 1... Solid-state imaging device, 2... A/D conversion device, 3... Digital video signal processing device, 4
...Digital color signal processing device, 5...
・Standard color television signal synthesizer, 6...
・Drive circuit device, 7... Control circuit device, 8...
...Optical signal, 9,1o...Pixel signal, 11...
...Control signal, 12...Digital pixel signal, 13...Digital video signal, 14°15...
... Digital color difference signal, 16 ... Standard color television signal, 17 ... Control element, 18
゜19.20.21... Control no (lus signal, 2
3...Digital 1 horizontal scanning period memory circuit, 2
4.25...Digital color difference signal processing circuit, 2
6...Digital color difference signal switching circuit, 27.28
...Digital pixel signal, 29.30...
...Digital color difference signal, 31...Digital video signal processing circuit, 32...Digital gamma correction circuit, 33...Digital delay circuit, 34
．． 36...Digital video word code, 36...
...control signal, 37...digital pixel signal,
38.39...Digital color difference signal, 41...
・Control signal, 42.43...Digital color difference signal, 96.104.106...A/D conversion circuit, 106.107...Digital latch circuit,
110...1 pixel shift circuit, 111...
...1 pixel inversion circuit, 112...Digital addition circuit, 117-119°134.136.145,1
46...Digital latch circuit, 136...
・Random access memory circuit, 173-180...
...Digital shift register, 181-184.
...Digital latch circuit, 198~2o○...
...Video signal correction circuit, 203...Additional averaging circuit, 204...1 pixel shift circuit, 206...
...Digital addition circuit, 206-208...
・Digital latch circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 4
Figure 5 Figure 7 Range 8 Figure 9 //6 (Z?: jO, jB, j'/) Figure 16 Figure 18 Figure 3, 7 (im.1..v6 fitG Mt6 Mt
6□74 Figure 23 weak ((12-) (B > 25th
figure

Claims (6)

[Claims] (1) Upon receiving the optical signal, the first pixel signal consisting of repeating alternately different color signals for each pixel is fully output in synchronization with the readout clock frequency during the horizontal readout scanning period, and the next horizontal readout period is performed. The second pixel signal is synchronized with the readout clock frequency and is configured to fully output a second pixel signal which is different from the information of the first pixel signal and consists of repeating different color signals alternately for each pixel. an analog-to-digital converter that converts first and second pixel signals output from the image pickup device into digital signals, and a digital pixel signal output from the analog-to-digital converter as input; , a digital color signal processing device that outputs independent first and second digital color difference signals; a digital video signal processing device that receives the digital pixel signal as input and outputs a digital video signal; and the first and second digital color difference signals. a standard color television signal synthesis device that inputs a color difference signal and the digital video signal and outputs a standard color television signal; a drive circuit device that drives the imaging device;
A color camera device comprising a control circuit device that generates timing pulses for driving the analog-to-digital converter, the digital video signal processor, the digital color signal processor, and the standard color television signal synthesizer. (2) The imaging device has six colors, β colors, six colors,
β color... (however, a and β are arbitrary hues) are arranged repeatedly, and for the next horizontal scanning direction, γ color, δ color,
γ color, δ color・・・・・・(However, γ and δ are arbitrary hues)
2. The color camera device according to claim 1, wherein the color camera device is repeatedly arranged as follows, and the arrangement is repeated alternately in the vertical scanning direction. (3) The analog-to-digital conversion device includes a two-man power, single-output type analog switch circuit into which each pixel signal information output from the imaging device is input, and an analog-to-digital conversion device into which the output of the analog switch circuit is input. circuit, and performs a switching operation to conduct one of the two input terminals at said A (where fC is the readout clock frequency), and synchronizes the analog-to-digital conversion circuit with a repetitive periodic force [ The color camera device according to claim 1, wherein the color camera device is configured to perform a conversion operation at a repetition period of 1/fo that is twice as high. (4) The analog-to-digital conversion device includes first and second analog-to-digital conversion circuits into which each pixel signal information output from the imaging device is input, and the first and second analog-to-digital conversion circuits.
and a second analog-to-digital conversion circuit, the output terminals of the first and second analog-to-digital conversion circuits are respectively inputted, and corresponding ones of the respective output terminals are connected in common. It is characterized in that the operation timings of the digital conversion circuit and the first digital latch circuit are configured so that the operation timings of the second analog-digital conversion circuit and the second digital latch circuit are opposite to each other. A color camera device according to claim (1). (5) A digital video signal processing device includes a digital video signal processing circuit for converting a digital pixel signal provided from an analog-to-digital converter into a digital video signal, and a gamma correction for the output signal of the digital video signal processing circuit. Claim No.
1) The color camera device described in item 1). (6) The standard color television signal synthesis device includes first and second digital-to-analog conversion circuits that convert first and second digital color difference signals output from the digital color signal processing circuit into analog color difference signals, respectively. ,
A third unit that converts the digital video signal output from the digital video signal processing device into a standard black and white television signal.
A color difference signal for obtaining color signals modulated by two independent phase modulation axes by inputting the analog color difference signals from the digital-to-analog conversion circuit and the synchronous pulse addition circuit, and the first and second digital-to-analog conversion circuits. Claim (1) characterized in that it is configured to include a modulation circuit and a synthesis circuit that inputs the black and white standard television signal and the color signal to obtain a standard color television signal. Color camera equipment.