KR0149532B1 - Encoding apparatus and method using digital signal processor - Google Patents

Abstract

The present invention relates to an encoding apparatus and method using a processor for digital signal processing. The present invention executes a program in a digital signal processing processor to balance the two color difference signals (RY, BY) data input, and generates a burst signal from the inputted carrier frequency data to generate balanced modulation data and burr. The stre signal is added to generate a chroma signal. Therefore, the present invention provides the effect of simplifying the device configuration and improving the overall performance.

Description

Encoding device and method using processor for digital signal processing

1 is a block diagram showing an encoding apparatus in a general video camera.

2 is a block diagram showing an encoding apparatus using a processor for digital signal processing according to a preferred embodiment of the present invention.

3 is a flowchart for explaining an encoding method of a processor for digital signal processing in the FIG. 2 apparatus.

4 is a timing diagram of signals input and output by a digital signal processing processor of the FIG. 2 apparatus.

* Explanation of symbols for main parts of the drawings

21, 22: A / D converter 23: ½ minute period

24, 25: line memory 26: input buffer

27: central processing unit (CPU)

The present invention relates to an encoding apparatus and method for modulating and synthesizing a signal photographed by a video camera, and the like. In particular, a process of modulating and synthesizing a color signal by executing an internal program of a processor for digital signal processing is performed. The present invention relates to an encoding apparatus and method using a processor for digital signal processing that can be performed.

In general, when a subject is photographed, an output is obtained at a ratio of R, G, and B by a red, green, and blue camera, and the output is combined to synthesize a luminance signal (Y). At the same time, chromaticity signals (I and Q signals) representing color and saturation are similarly synthesized at the camera output. The chroma signal is represented by two waveforms of an I signal and a Q signal, but in order to be sent to the same channel as the luminance signal Y, these signals must be combined into one. Such a conventional encoding apparatus is shown in FIG.

FIG. 1 is a block diagram showing an encoding apparatus of a general video camera, which is a well-known technique.

The I-matrix unit 11 obtains an I signal by mixing the output signals R, G, and B of the red, green, and blue color imaging tubes in the following ratios.

I = 0.60R-0.28G-0.32B

That is, the I-matrix unit 11 receiving the R, G, and B signals combines the I signal by combining the R signal 60%, the G signal 28% with the changed polarity, and the B signal 32% with the changed polarity. Make.

The Q-matrix unit 12 mixes the three primary colors signals R, G, and B of the camera as follows to produce a Q signal.

Q = 0.21R-0.52G + 0.31B

That is, the Q-matrix unit 12 that receives the R, G, and B signals together produces a Q signal by combining the R signal 21%, the G signal 52% having changed polarity, and the B signal 31%.

The I signal balance modulator 13 connected to the I-matrix unit 11 modulates the input I signal to a carrier (color carrier) frequency (Subcarrier; SC) of 90 ° and 270 °. The Q signal balance modulator 14 connected to the Q-matrix unit 12 modulates the input Q signal to a carrier frequency SC of 0 ° and 180 ° and outputs the modulated signal. Here, the carrier frequency SC supplied to the I signal and the Q signal balance modulators 13 and 14 uses 3.579535 MHz. The I signal balance modulated output I _M and the Q signal balance modulated output Q _M are synthesized with each other in the adder A to generate and output a Chroma (Croma) signal representing the color of the image signal.

However, since such an encoding apparatus has conventionally been processed in a analog manner through a plurality of passive elements, there is a problem in that the variation is large for each set, so that there are many adjustment specifications, and characteristics change according to time and temperature. In addition, it takes up a lot of PCB space because of the large number of parts, the reliability was low and the production cost was high. Therefore, in order to solve the above problems, the ASIC chip which combines a plurality of logic elements was developed and processed digitally, but if the characteristic is to be changed, the ASIC chip must be developed from the beginning again. There was a problem.

Accordingly, an object of the present invention is to execute a process of modulating and synthesizing a color signal through an internal program of a digital signal processing processor to solve the above-described problems, and to provide a digital signal processing processor capable of changing its characteristics only by changing the program. It is to provide an encoding device used.

Another object of the present invention is to provide an encoding method in an encoding apparatus using the aforementioned digital signal processing processor.

The encoding apparatus using the digital signal processing processor of the present invention for achieving the above objects, in the encoding apparatus for the modulation and synthesis of three color signals in processing a video signal, subtracting the luminance signal from two of the three color signals An input terminal for receiving two color difference signals, a plurality of A / D converters for converting two color difference signals inputted through the input terminal into digital data, and outputting the same; A divider for outputting a carrier frequency, and an input buffer connected between the plurality of A / D converters and the divider to store two color difference data in synchronization with a predetermined clock frequency, when a horizontal synchronous signal is inputted. Each color difference signal data stored in the input buffer is read each time, and the double carrier frequency and the divided carrier are read. Receives the frequency and burr host flag pulse and a digital signal processor for generating a modulated chroma signal having balanced the two color difference signal data and to generate a burr host signal synthesizing balanced modulation signal and the host signal burr.

An encoding method using a digital signal processing processor for achieving another object of the present invention is a method for executing an encoding function through an internal program of a digital signal processing processor, wherein a plurality of color difference signals are received and respectively received. A conversion step of converting the signal to a color, a storage step of storing the color difference signal data according to a predetermined clock frequency, receiving a frequency of n times the carrier frequency and dividing the signal at 1 / n, and whether or not the horizontal synchronization signal is inputted A balance modulation step of reading the stored color difference signal data, receiving the n times the carrier frequency and the divided carrier frequency, respectively, and executing a balance modulation program of the two color difference signal data; and after the balance modulation program is executed, Burst signal generation step for executing a test signal generation program, and said balance modulation program And to execute the burr host signal generation program by summing the balanced modulated data signal obtained with the burr host includes the step of generating the chroma signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an encoding apparatus using a processor for digital signal processing according to an embodiment of the present invention. The encoding apparatus shown in FIG. 2 is provided with two A / D converters 21 and 22 which perform analog digital conversion on two input color difference signals RY and BY, respectively. A plurality of line memories connected to two A / D converters 21 and 22, respectively, for serially reading and storing two digitally converted color difference signals RY and BY according to a predetermined clock signal CLK. Also provided is a central processing unit (CPU) 27 which is a digital signal processing processor having an input buffer 26 composed of (24, 25). The encoding apparatus of FIG. 2 also includes a ½ divider 23 for dividing and outputting twice the carrier frequency 2FSC that is input. The central processing unit 27 connected between the two A / D converters 21 and 22 and the ½ divider 23 has a program for executing a modulation and synthesis process of the color signal. The central processing unit 27 is also configured to receive a horizontal sync signal H _sync and a Burst Flag Pulse BFP. The operation of the encoding apparatus using the digital signal processing processor of FIG. 2 having such a configuration will be described in more detail with reference to FIGS. 3 and 4.

In FIG. 2, two color difference signals RY and BY input through the input terminal are applied to the respective A / D converters 21 and 22. FIG. The first A / D converter 21 converts the received red difference signal RY into digital data and outputs the digital data. The second A / D converter 22 converts the received blue difference signal BY into digital data and outputs the digital data. The input buffer 26 having the first line memory 24 and the second line memory 25 embedded in the central processing unit 27 is connected to the first A / D converter 21 and the second A / D converter 22. The digitally-converted red difference signal RY and blue difference signal BY are serially read and stored in accordance with a predetermined clock signal CLK. On the other hand, the ½ divider 23 receives the double carrier frequency (2FSC) is divided into ½, and outputs the divided carrier frequency (FSC) to the central processing unit (27). Here, the carrier frequency FSC uses 3.579545 MHz as in the first carrier frequency SC. The double carrier frequency 2FSC input to the ½ divider 23 is also input to the central processing unit 27. The central processing unit 27 synchronizes with the horizontal synchronization signal H _sync and the red difference signal RY and the blue difference stored from the first line memory 24 and the second line memory 25 of the input buffer 26. Read and supply the data of the signal BY, and receive the carrier frequency (FSC) and the burst flag pulse (BFP) divided by the double carrier frequency (2FSC) and the ½ divider (23) and receive the chroma signal (C). Create and print The built-in operation of performing the modulation and synthesis process of the color signal in the central processing unit 27 will be described in detail with reference to FIGS. 3 and 4.

FIG. 3 is a flowchart for explaining an encoding method of the central processing unit 27 which is a processor for digital signal processing in the apparatus of FIG. 2, and FIG. 4 is a signal timing diagram for explaining the operation of the central processing unit 27. As shown in FIG.

In FIG. 3, the central processing unit 27 checks whether the horizontal synchronization signal H _sync is input (step 101). The signal from the horizontal synchronizing signal (H _sync), type checking step (step 101) until the signal having the logic value 1 to the HD terminal of the central processing unit 27 is input, the standby state having the logic value 1 to the HD terminal When inputted, the data of the red difference signal RY and the blue difference signal BY stored in the first and second line memories 24 and 25 of the input buffer 26, which are internal storage means, is read and received. The carrier frequency 2FSC and the carrier frequency divided by ½ at the ½ divider 23 are input (step 102). The central processing unit 27 then balance modulates the two color difference signals RY and BY data input from the data input step 102.

In the balanced modulation process, the central processing unit 27 complements the double carrier frequency (2FSC) data shown in FIG. 4 (a), and the double carrier frequency (repaired) ) Multiply the data by the red difference signal (RY) data. In other words, the central processing unit 27 has the waveform shown in FIG. The red difference signal RY is kept as it is during the high (H) level period, and the red difference signal (RY1) which is ignored during the low (L) level period is obtained (RY1 = (RY) (step 103). The blue difference signal BY data is multiplied by twice the carrier frequency 2FSC data shown in FIG. 4 (a), and the blue difference signal BY is applied during the high (H) level section of the waveform 2FSC. The data is kept as it is, and the blue difference signal BY1 in the ignored state is obtained during the low (L) level section (BY1 = 2FSC × (BY)) (step 104). The two newly obtained color difference signal (RY1, BY1) data are added together to obtain RB1 data having a timing as shown in Fig. 4C (RB1 = RY1 + BY1) (step 105). RB1 data as shown in FIG. 4 (c) is multiplied by carrier frequency (FSC) data divided in the ½ divider 23 shown in FIG. The data is kept as it is, and RB2 data in which the RB1 data is ignored during the low (L) level period is obtained (RB2 = FSC x RB1) (step 106). The central processing unit 27 also reverses the divided carrier frequency (FSC) data as shown in FIG. 4 (d) as shown in FIG. Multiply by the waveform shown in the figure). In other words, the central processing unit 27 has the waveform shown in FIG. RB1 data is maintained for the high (H) level interval of RB3 data is obtained while RB1 data is ignored during the low (L) level interval of RB3 = RB3 = X RB1) (step 107). Then, by subtracting the RB3 data from the RB2 data, the equilibrium-modulated data RB4 of the two color difference signal (RY, BY) data as shown in FIG. 4 (f) is obtained (RB4 = RB2-RB3) (step 108). . After performing these steps to obtain the balanced modulated RB4 data (waveform shown in FIG. do.

Looking at the burst signal generation process, the central processing unit 27 is a state inverted carrier frequency ( The carrier frequency (the state reversed) by multiplying the data (waveform shown in FIG. Create SC1 with size k times () (SC1 = k × ) (Step 109). Here, k value is a value for determining the burst size. After determining the burst size (step 109), SC1 to SC1 Subtract the size by twice to make the DC (DC) component value of SC1 zero, and make SC2 with only the AC component (SC2 = SC1-). X SC1) (step 110). The SC2 thus obtained is delayed by 45 ° in phase compared to the BY1 data obtained in step 104. In order to create a burst using this SC2, the phase is delayed by 45 °, so that the phase is delayed by 90 ° compared to the BY1 data, thereby producing an SC3 waveform as shown in FIG. 4 (g) (step 111). ). In this way, the SC3 waveform (shown in Figure 4 (g)) is multiplied by the burst flag pulse (BFP) as shown in Figure 4 (h), and the burst signal SC4 (waveform shown in FIG. 4 (i)) taking only the burst signal is obtained (SC4 = BFP x SC3) (step 112). After these steps are executed to obtain the burst signal SC4 (waveform shown in FIG. 4 (i)), the chroma signal C is generated.

Referring to the chroma signal generation process, the central processing unit 27 shows the burst signal SC4 (shown in FIG. 4 (i)) on the balanced modulation data RB4 (waveform shown in FIG. 4 (f)) obtained by performing the above-described steps. And a chroma signal C as a color signal (C = RB4 + SC4) (step 113). After the generated chroma signal C is output (step 114), the process returns to step 101 to repeat the process.

As described above, the encoding apparatus and method using the digital signal processing processor of the present invention is encoded through an internal program of the digital signal processing processor as compared to the conventional encoding using the analog method or the digital method using an ASIC chip. By executing the circuit, the scale of the circuit is also simplified, and the overall performance is improved.

Claims (6)

An encoding apparatus for modulating and synthesizing three color signals in processing an image signal, comprising: an input terminal for receiving two color difference signals obtained by subtracting a luminance signal from two color signals among three color signals; A plurality of A / D converters for converting two color difference signals input through the input terminal into digital data and outputting the digital data; A divider for dividing an input double carrier frequency by ½ and outputting a divided carrier frequency; And an input buffer connected between the plurality of A / D converters and the divider to store two color difference data in synchronization with a predetermined clock frequency, each time being stored in the input buffer whenever a horizontal synchronous signal is input. Reads the chrominance signal data, receives the double carrier frequency, the divided carrier frequency and the burst flag pulse, balances the two chrominance signal data, generates a burst signal, and synthesizes the balanced modulation signal and the burst signal. An encoding apparatus using a digital signal processing processor comprising a digital signal processing processor for generating a chroma signal. 2. The encoding device according to claim 1, wherein the input buffer of the digital signal processing processor comprises a plurality of line memories. A method for executing an encoding function through an internal program of a digital signal processing processor, the method comprising: a conversion step of receiving a plurality of color difference signals and converting them into digital data; A storage step of storing the color difference signal data at a predetermined clock frequency; receiving the carrier frequency of n times and dividing by 1 / n; A balanced modulation step of reading the stored color difference signal data according to whether a horizontal synchronization signal is input, and receiving an n-times carrier frequency and a divided carrier frequency, respectively, and executing a balanced modulation program of the two color difference signal data; A burst signal generation step of executing a burst signal generation program after the balance modulation program is executed; And generating a chroma signal by adding the balanced modulation data and the burst signal obtained by executing the balanced modulation program and the burst signal generation program. 4. The encoding method according to claim 3, wherein n is 2 and a carrier frequency is 3.579535 MHz. 5. The method of claim 3 or 4, wherein the balance modulation step is performed by multiplying the first color difference signal data by the n times the carrier frequency of the two color difference signal data and performing the repair processing on the n times the carrier frequency by the second color difference signal data. Then summing up each data obtained by multiplying; And multiplying the summed carrier frequency by the divided carrier frequency, inverting the summed carrier frequency with the summed data, and subtracting each data obtained by multiplying to calculate the balanced modulated data. An encoding method using a digital signal processor. 6. The method of claim 5, wherein the burst signal generating step comprises: determining a burst size by multiplying the state inverted carrier frequency by an arbitrary real value; Making only a DC component by setting a DC component value to 0 at a carrier frequency at which the burst size is determined; Delaying a phase of a carrier frequency having a burst size having only the AC component by a predetermined magnitude so that the phase is delayed by 90 ° compared to data obtained by multiplying the first color difference signal data by the n times the carrier frequency; And taking a burst signal by multiplying a burst flag pulse signal inputted to the phase delayed carrier frequency.