JPS58219893A - Digital color encoder - Google Patents

Abstract

PURPOSE:To add a burst signal a synchronizing signal without using a specific envelope generating circuit by controlling the output of a digital filter and data switching by a burst flag signal and synchronizing these signals by a modulating and mixing circuit. CONSTITUTION:Digital chroma signals 10, 11, 12 are converted into Y, I and Q signals by a matrix circuit. A selector 16 is arranged between digital low pass filters 14, 15 which form the envelope of a burst signal and limit the band. A burst flag signal controls the selector 16 through a delay circuit 17. The output of the filter 15 is passed through a blanking gate 18 controlled by a BF signal and a blanking signal and supplied to a Y/C mixer circuit 21. The slop of the rise and fall of the synchronizing signal is added to a luminance signal Y by the digital low pass filter. The circuit 21 mixes a chroma signal with the synchronizing signal to obtain a digital composite color video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is applied to studio equipment as one of the standards for a digital color encoder, particularly for the 0NTB C-type spliced cathide S signal regarding the addition of burst signals and synchronization signals (EIA provisional standard). is proposed. FIG. 1A relates to a burst signal in this standard, in which a burst signal BS with an amplitude of ±201 RE units is added in 9 cycles to the back porch of the horizontal synchronizing signal 5YNC. The burst signal Bs has a predetermined slope in its rise and fall edges.

Furthermore, FIG. 7B shows an enlarged view of the horizontal synchronizing signal S Y N C, which corresponds to the blanking level (
It falls at a predetermined slope from IRE:0) to (IRE knee 1IO) and rises at a predetermined slope.◇The length of the horizontal blanking period, the length of the sync tip level period, etc. are also specified. It is stipulated in

When processing the output of a color camera with a digital color encoder to generate a composite color video signal that meets the above-mentioned standards, it is necessary to add the above-mentioned burst signal and synchronization signal. This shows a configuration for adding a burst signal and a synchronization signal. In the figure, 1 and 2 indicate input terminals to which a digital chroma signal C and a digital luminance signal Y are supplied, and these signals are supplied to an adder circuit 3 and a Y/c mixer 4. Further, 5 indicates a burst envelope generation circuit, and 6 indicates a synchronous envelope generation circuit. For the burst envelope generation circuit 5, the burst flag BF
is supplied, data is generated at a predetermined timing, this is added to the chroma signal C by the adder circuit 3, and then supplied to the digital balanced modulator, and the first
A chroma signal including a digital burst signal conforming to the standard as shown in FIG. A appears and is supplied to the Y/C mixer 4.

Further, by supplying the Z signal C-i'YNc corresponding to the pulse waveform to the synchronous envelope generating circuit 6, rises and falls of a predetermined slope are imparted.

It is added to the output of the Y/C mixer 4 in an adder circuit 8, and a digital composite color video signal is taken out at an output terminal 9.

The above-mentioned burst envelope generation circuit 5 and synchronization envelope generation circuit 6 use a multiplier that multiplies video data by a predetermined envelope constant or a memory that stores burst data and synchronization data as they are, as well as a burst flag BF and a signal C-8YNC. It is configured to read and operate from the timing of the previous edge.

However, since such a special envelope generating circuit is required, there is a problem in that the hardware becomes complicated.

The object of the present invention is to realize a digital power encoder that can add predetermined burst signals and synchronization signals without requiring a special envelope generation circuit.

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 3 showing the overall configuration of this example, 10
．． 11 and 12 are input terminals to which digitized green, red, and blue signals output from the camera are supplied. By supplying this chroma signal to the matrix circuit 13, a luminance signal Y00, a color difference signal, 2, 9 color difference signals Q, are respectively formed. The present invention can also be applied to cases where U and V components are used as color difference signals.

The color difference signal I is filtered by a digital p-pass filter.
One color difference signal Q is band limited to 5MHz.

Band-limited to 0.5 MHz by a digital p-pass filter. This digital low-pass filter for color difference signals has a configuration in which a transfer function for exhibiting desired frequency characteristics is expanded into a plurality of polynomials, and partial filters with characteristics corresponding to each of the plurality of polynomials are connected in cascade. .

A portion of the digital low-pass filter for this color difference signal is also used to form a 1y-wave to the edge of the parsed signal. The low-pass filter for color difference signal processing is
It is divided into two digital filters 14 and 15 having transfer functions H11 and HI, and a selector 16 is inserted between these digital filters 14 and 15. Digital filter 114 as one input of selector 16
The output of one is supplied, and the editor is supplied as an input of the other. This selector 16 is controlled by a burst flag passed through a shift register 17. ■The data is converted to the standard level (20IRg units) after digital modulation using the IRE
This is a digital signal of IO bits corresponding to the DC signal of the unit.

The shift register 1T delays the burst flag BF by an amount equal to the delay caused by the digital filter 14, and the compensated burst flag selects the data for a predetermined period and appears at the output of the selector 16. Therefore, at the output of the digital filter 15, a one-color difference signal signal and an edited data (that is, a vermilion modulated burst signal) to which a predetermined envelope loop has been added by the digital filter 15 appear. This digital filter 15
The output of is supplied to the blanking gate 18.

Blanking gate 18 is controlled by the output of logic circuit 19. In this logic circuit 19.

The output of the shift register 1T is supplied via the shift register 20, and a blanking signal CBLK is also supplied. 1. Among the blanking signals C and BLK, a control pulse is generated from the logic circuit 19 to operate the blanking gate 18 except for the burst flag period and the rising and falling loop periods. The color difference signal I output from the blanking gate 18 is supplied to a modulation and Y/C mixer circuit 21.

Similar to the color difference signal generator described above, the digital low-pass filter for one color difference signal Q is the digital filter 22 and 2.
It is divided into three parts, and a selector 24 is inserted between the two parts. In addition, shift register 2 for compensation delay
5.28 is provided.

Furthermore, a blanking gate 26 and a logic circuit 27 forming its control signal are provided. The Q data added to the color difference signal Q is as follows.

(-20mln33°) This is a digital signal of IO bits corresponding to the DC signal of the IRE unit.

In this way, the color difference signals I and Q to which unmodulated burst signals are added are processed in the modulation and Y/C mixer circuit 21.
1/2f8o (/sc: color subcarrier frequency)
The signal is dot-sequentialized so that the period of the signal is reduced to 1/2, and further multiplied by a coefficient of 10 or -/ at a predetermined timing to perform digital balance modulation.

An example of the transfer function of each of the digital filters 4 and 15.22°23 described above is shown below.

HI, =' (/+Z) HQs "'(/+Z-")・(jZ +gZ
-1-4)2 HQ2=i(/+Z)・(/+z)2The above formula Tez-1
C represents an operator that gives a delay of 1/2fSC, and 2f
Each digital filter operates with SC as four frequencies.

Here, the reason why the transfer functions HI and HQt are different is that in the modulation and Y/C mixer circuit 21, the positive and negative of the burst envelope are This is to compensate for the waveform shift caused by 0. The luminance signal Y appearing from the matrix circuit 13 is supplied to the selector 30 via a compensation delay circuit 29. This selector 30 is supplied with sync chip data corresponding to a predetermined DC level, and is controlled by sync signals C and 8YNC. The output of this selector 30 is supplied as one input of a selector 31, which in turn is supplied to a digital low-pass filter 32. The output of this digital low-pass filter 32 is used as the other input of the selector 31. The digital low-pass filter 32 is for adding a standard-compliant slope to the rising and falling edges of the synchronization signal. The sync signals C, 5YNC and the signals delayed by the shift register 33 are supplied to an AND gate 34, and the selector 31 is controlled by the output of the AND gate 34.

Figure q shows the sync signal C, 8YNC.

FIG. 3B shows this delayed by the shift register 33. Since the selector 30 selects the sync chip data while the sync signals C and 8YNC are at low level, the output of the digital low-pass filter 32 has a predetermined rising and falling edge as shown in analog form in FIG. 1C. A sync tip signal with sleep is generated. Further, the AND gate 34 generates a control signal as shown in the diagram, whereby the above-mentioned sync chip signal is selected and output, and is supplied to the blanking gate 35. During a period in which the output of the AND gate 34 is at a high level, the selector 31 selects the luminance signal from the selector 30.

The buten king gate 35 is controlled by the input signal formed by the fill logic circuit 36. The logic circuit 36 is supplied with the sync signals C, 8YNC and the blanking signals C, BLK, and the luminance signal Y is set at the blanking level during the blanking period excluding the sync chip signal and its loop period. In this way, the luminance signal to which the synchronization signal has been added is modulated in the Y/C mixer circuit 21.

The modulated signal is mixed with the chroma signal and a digital composite color video signal is obtained at output terminal 9.

The delay time caused by both the dual compensation delay circuit 29 and the digital low-pass filter 32 is equal to the delay time caused by the digital low-pass filter for one color difference signal system. Also.

The digital low-pass filter 32 operates with a clock of 4fSc (0 frequency), and its transfer function Hy is.

For example, (HY=L(/+z)).

FIG. 5 shows another configuration for adding a synchronization signal, in which digital modulation having pH1 and H3 transfer functions is used.3T and 39 are for one color difference signal. A selector 38 controlled by sync signals C and BYNC is provided between these two digital filters 37 and 39, so that sync chip data can be added. During the period when this sync chip data was added,
Digital modulation of the color difference signal in the subsequent stage is stopped.0 The color difference signal supplied to the digital filter 37 may be a color difference signal (■ or Q) with a sampling frequency of 2/sc, as in the above embodiment, or As shown in FIG. 6, two color difference signals and Q may be dot-sequential. If the color difference signals I and Q are independent, the transmission of the digital filter 39 is 1 -12 ? (/+Z). Also 1 color difference signal engineer.

In the case where Q is point sequential, the transfer function H! is, for example, 7(/+Z). In the transfer function Ht for this point-sequential color difference signal, Z-1 is
('/4fsc) is a delay operator.

As can be understood from the description of one embodiment above.

According to his invention, a digital composite signal with a predetermined envelope burst signal and a synchronization signal having a predetermined slope edge can be generated without the need for a special envelope signal generation circuit like a conventional color encoder. Color video signals can be generated. Therefore, the configuration of the color encoder can be simplified. Since the envelope of this seven-destination signal is generated using a part of the digital filter for band-limiting the one-color difference signal, there is an advantage that no special digital filter is required.

Note that digital filters that are configured to delay each upper l bit or multiple bits (referred to as a slice) by l sampling period in order to perform operations such as multiplication and addition of coefficients are used. It's okay. In this case, burst.

The higher the flag, the more the flag is applied with a phase delayed by l sampling period.

[Brief explanation of the drawing]

Fig. 1 is a waveform diagram of a 7<-st signal and a synchronization signal in a composite color television signal, Fig. 2 is a block diagram showing a configuration for adding a conventional burst signal and a synchronization signal, and Fig. 3 is a waveform diagram of a 7<-st signal and a sync signal in a composite color television signal. A block diagram of one embodiment of the invention, Fig. 5 is a time chart used to explain the operation of adding a synchronization signal in one embodiment of the invention, and Figs. 5 and 5 are part of other embodiments of the invention. 2 is a splitter diagram showing the configuration of the printer and a time chart used for explaining the splitter diagram. 10.11.12... Digital chroma signal input terminal, 14, 15.22.23, 37.39...
...Digital filter for color difference signals, 29...
...Compensation delay circuit, 1B, 24.30.31゜3
8... Selector, 21... Modulation and Y
/Cme+S circuit, 32...Digital low-pass filter for forming the slope of the synchronization signal. Agent Masato Sugiura

Claims (1)

[Claims] 0) A burst flag is applied to the first stage or between the stages of a digital filter to which a digital PM signal is supplied, and a digital clock signal containing unmodulated burst data having a predetermined envelope at a normal level is generated. A digital color encoder that outputs a color signal from the digital filter. (2) Adding a synchronization signal having predetermined rising and falling edges formed by a digital me-pass filter or a digital filter for the 4-major signal inserted into the digital luminance signal path, or a part thereof; A digital color encoder in which a burst flag is applied to the first stage or between the stages of the digital filter for the above-mentioned 4-major signal, and unmodulated burst data having a predetermined escipelope at a normal level is added.