JPH09146506A - Ramdac device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an inexpensive system having a small board scale by making NTSC encoding digital-processable and making it on-chip together with RAMDAC. SOLUTION: The RAMDAC DEVICE 1 has a RAMDAC section 15 and a NTSC encoder section 16. A second PLL circuit 6 generates a clock having a frequency 4 fsc synchronizing with a pixel clock of 12.273MHz, a conversion circuit 7 converts signals R, G, B into a luminance signal Y and color difference signals (R-Y), (B-Y), a sampling frequency conversion circuit 8 converts a frequency of both color difference signals from 12.273MHz into 4fsc . Further, A LPF 9 limits a frequency band of the color difference signal after conversion into approximately 1MHz, a chroma encoder circuit 10 generates a chroma signal C by performing balanced modulation for the color difference signal. On the other hand, the luminance signal Y is delayed by a time required for the above-mentioned processing for the color difference signal by a delay adjusting circuit 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a RAMDAC device used for, for example, three-dimensional graphics, and particularly, an NTSC system output section (NTSC encoder) for a TV port is provided in the same chip as the RAMDAC section. The device provided in.

[0002]

2. Description of the Related Art Conventionally, a RAMD for three-dimensional graphics
The AC1P has a block configuration as shown in FIG. Here, as is known, the term “RAMDAC” means that the palette RAM 3P is addressed by the 8-bit pixel data 71 read from the frame buffer 70 outside the RAMDAC, and the 3 output from the palette RAM 3P is thereby generated. RGB for primary color components
A device having a function of outputting RGB signals by D / A converting the data 74 by the corresponding DA converters 4P.

The palette RAM 3P functions as a table for converting the input pixel data 71 into RGB data 74. Moreover, since the relationship between the pixel data 71 and the RGB data 74 needs to be variable, the contents of the palette RAM 3P can be read / written (R / W) by the MPU 2P.
For this reason, the RAMDAC 1P has an MPU port 72, and the control signal 73 from the MPU 2P and the horizontal synchronization signal HS read and input from the frame buffer 70.
The YNC and the vertical synchronization signal VSYNC are accessed to the timing generator 5P, so that the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC as shown in Table 1 below are obtained.
The output of C is obtained.

[0004]

[Table 1]

The values shown in Table 1 are the same as the standards of the NTSC system.

[0006]

Problems to be Solved by the Invention RA shown in FIG.
When connecting the output port of the MDAC1P to an NTSC system device, as shown in FIG. 15, RAMDAC1P
Which is an analog IC for encoding the RGB signal into an NTSC video signal (luminance signal Y, chroma signal) on the subsequent side of the output signal of the RGB signal.
This has been dealt with by separately mounting the SC analog encoder 75. Therefore, there is a problem that the board scale becomes large.

The present invention has been made in order to overcome such a problem, and it is based on the RGB signal of RAMDAC to NT.
RAMDA has a function to encode the video signal of SC system
The main purpose is to provide the C device itself. As a result, the NTSC encoder can be realized on-chip, and the board scale can be reduced accordingly.

Another object of the present invention is to realize various functions such as reduction of the gate size, prevention of deterioration of image quality, adjustment of image quality, etc. in the same device.

[0009]

R according to the invention of claim 1
The AMDAC device reads out the stored three primary color component signals at the timing of a pixel clock, performs digital / analog conversion, and outputs the read signals.
A RAMDAC device for outputting as a signal compatible with the C system, converting at least the three primary color component signals into a video signal, and performing linear interpolation so that at least a color difference signal of the video signal is four times as high as a color subcarrier frequency. It is characterized in that the signal is converted into a frequency and the color difference signal is further encoded to output as a signal compatible with the NTSC system.

A RAMDAC device according to a second aspect of the present invention is the RAMDAC device according to the first aspect, wherein a clock having a frequency four times as high as the color subcarrier frequency synchronized with the pixel clock is generated, and the frequency conversion and The encoding is performed.

A RAMDAC device according to a third aspect of the present invention is the RAMDAC device according to the second aspect, wherein the frequency conversion is performed only on the color difference signal in the video signal, and a processing time for the color difference signal is applied to the luminance signal. It is characterized by performing only the delay adjustment processing.

A RAMDAC device according to a fourth aspect of the present invention is the RAMDAC device according to the third aspect, wherein the NT is provided before the encoding after the frequency conversion or after the encoding.
The color difference signal is limited to a band determined by the SC method.

A RAMDAC device according to a fifth aspect of the present invention is characterized in that, in the fourth aspect, the horizontal enhancement process is performed prior to the delay adjustment process for the luminance signal.

According to a sixth aspect of the present invention, there is provided the RAMDAC device according to the third aspect, wherein the color difference signal is limited to a band determined by the NTSC system simultaneously with the linear interpolation during the frequency conversion.

A RAMDAC device according to a seventh aspect of the present invention is the RAMDAC device according to the sixth aspect, wherein the ratio of the frequency four times the color subcarrier frequency to the pixel clock frequency is x: y.
Then, the frequency of the color difference signal is multiplied by x to interpolate data for each y, and at the same time, the band limitation determined by the NTSC method is performed, and then the frequency of the color difference signal is multiplied by 1 / y. To do.

According to a eighth aspect of the present invention, there is provided the RAMDAC device according to the second aspect, wherein the signal corresponding to the NTSC system is added with a composite synchronizing signal at the time of digital-analog conversion.

According to a ninth aspect of the present invention, in the RAMDAC device according to the eighth aspect, the DA converter for performing the digital-analog conversion is connected to the current source for the video signal and the current source in parallel via a switch. And another current source for the composite sync signal.

According to a tenth aspect of the present invention, in the RAMDAC device of the second aspect, the frequency conversion is performed separately for both the color difference signal and the luminance signal, and the luminance signal after the frequency conversion and the encoding are performed. The composite video signal obtained by performing addition processing with the obtained chroma signal is output as the signal corresponding to the NTSC system.

The RAMDAC device according to the invention of claim 11 relates to claim 2, wherein the frequency conversion is performed separately for both the color difference signal and the luminance signal, and the NT
In the step of outputting the signal corresponding to the SC system,
An adder for performing a process of adding the luminance signal after the frequency conversion and a chroma signal obtained by the encoding to obtain a composite video signal, a first primary color component signal of the three primary color component signals and the frequency converted Select the luminance signal of
A first selector for outputting, a second selector for selecting and outputting the second primary color component signal of the three primary color component signals and the composite video signal, and a third primary color component signal of the three primary color component signals A third selector for selecting / outputting the chroma signal, a first DA converter for converting the output of the first selector into a digital / analog, and a second DA converter for converting the output of the second selector into a digital / analog, And a third DA converter for converting the output of the second selector into a digital-analog format.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 shows a RAMD according to the first embodiment.
FIG. 3 is a block diagram showing the configuration of an AC device 1, which is the present device 1
Has a configuration for making the NTSC encoder on-chip, as described later. The apparatus 1 is roughly divided into a RAMDAC section 15 which is a portion surrounded by a broken line and an NTSC encoder section 16 which is a portion other than the RAMDAC section 15. Of these, the RAMDAC unit 15 is the system before the NTSC encoding is inserted, and the RAM shown in FIG.
The system is the same as the DAC device 1P.

First, in the RAMDAC section 15, R
The color palette RAM 3 is accessed by the pixel data (8 bits) read from a frame buffer (not shown here) (see FIG. 14) provided outside the AMDAC device 1, and the color palette R 3 is accessed.
The RGB signals of the three primary color components are output from AM3.

Here, when the electric image given by the RGB signals is displayed on the screen of an external device such as a personal computer, RG is displayed.
The B signal is a DA converter 4 corresponding to each color component.
Digital-analog conversion is performed by R, 4G, and 4B. The three DA converters 4R, 4G, and 4B are collectively referred to as the DA converter 4.

On the other hand, when the RGB signal is NTSC encoded, the MPU 2 sets the timing of the RGB signal read from the color palette RAM 3 to be the same as the timing of the NTSC standard. The set RGB signal (each 8-bit signal) is (RGBtoY, R
-Y, BY) input to the conversion circuit 7,
Represents the RGB signal as the luminance signal Y and the color difference signal (R−, according to the luminance signal equations given by the following equations 1 to 3.
Y) and (B-Y).

[0024]

(Equation 1)

[0025]

(Equation 2)

[0026]

(Equation 3)

The converted color difference signals (RY), (B-
Y) (9 bits each) is the sampling frequency conversion circuit 8
And the conversion circuit 8 performs linear interpolation to obtain a color difference signal (RY) having a frequency of 12.273 MHz,
(BY), the frequency fsc (3.5
4 times the frequency 4 fsc (14.31818)
Frequency conversion to MHz). In this linear interpolation, the integer ratio (14.31818 MHz: 12.
273 MHz = 7: 6) is used.

Next, the color difference signal (R-
Y) and (B−Y) are input to the low-pass filter (LPF) circuit 9, and the LPF circuit 9 outputs the color difference signals (R−).
The frequency bands of Y) and (BY) are limited to the 1 MHz band determined by the NTSC system. Then, the chroma encoder circuit 10 uses the band-limited color difference signal (R-
Y) and (B−Y) are encoded and modulated into a chroma signal (carrier color signal) C, and the chroma signal C is output to the DA converter 11. The DA converter 11 performs digital / analog conversion on the input chroma signal C and outputs the chroma signal C as an analog signal.

In this example, the band limiting circuit for limiting the frequency band to about 1 MHz is constructed by providing the LPF 9 in the preceding stage of the chroma encoder circuit 10.
Alternatively, the band limiting circuit can be configured by providing a bandpass filter BPF in the subsequent stage of the chroma encoder circuit 10.

On the other hand, the luminance signal Y converted by the (RGBtoY, RY, BY conversion circuit) 7 is input to the delay matching circuit 12. The circuit 12 has a color difference signal (B-
Y), (RY), the luminance signal Y is delayed by the processing time required to generate the chroma signal C, and both signals Y,
Match the phase of C. The delayed luminance signal Y is digital-analog converted by the DA converter 13 and output. Output video signal (Y, C)
Is a "signal compatible with the NTSC system".

As described above, in the first embodiment,
In the chroma encoder circuit 10, the color difference signal (R-
Y), (B-Y) to 4fsc (14.31818MH
z), the sampling frequency conversion circuit 8 encodes the pixel clock frequency 12.
Frequency from 273MHz to 4fsc (14.31818M)
Sampling frequency conversion to (Hz).

In this case, not only the color difference signal but also the luminance signal Y, that is, the pixel clock 12.273 MHz
It is also possible to perform the above sampling frequency conversion on all of the video signals of. However, when the luminance signal Y is similarly subjected to the above frequency conversion, the band falls, so that the processing of edge enhancement in the horizontal direction is further required for the luminance signal.

Therefore, in the first embodiment, the sampling frequency conversion is performed only for the color difference signals (BY) and (RY), and the sampling frequency conversion is performed for the luminance signal Y. Without the color difference signal (B-
Y) and (RY) are processed for delay matching the processing time. Moreover, in the case of adopting this configuration, the delay matching circuit 12 can be configured by only the D flip-flop (hereinafter, simply referred to as DFF), and the frequency conversion, the horizontal edge enhancement, and the color difference with respect to the luminance signal Y are performed. Signal (B-
There is an advantage that the gate scale can be reduced as compared with the case where the respective processes of Y) and (RY) for the processing time corresponding to the processing time are performed.

Further, in the RAMDAC device 1 of FIG. 1, the basic clock from the oscillator 14 having an oscillation frequency of 13.5 MHz is supplied to the first phase locked loop circuit (hereinafter referred to as the first PLL).
(Referred to as a circuit) 5 and the first PLL circuit 5
12.273M synchronized with 3.5MHz basic clock
Generate a pixel clock of Hz. This 12.273
The pixel clock of MHz is supplied to the RAMDAC unit 15,
(RGB to Y, RY, BY conversion circuit) 7, sampling frequency conversion circuit 8, delay adjustment circuit 12, DA converter 13 for luminance signal Y, and second PLL circuit 6 are input. Further, in the second PLL circuit 6, 12.273 MH
frequency 4 fsc (1
4.31818 MHz) clock is generated. The generated clock having a frequency of 4 fsc (14.31818 MHz) is input to the sampling frequency conversion circuit 8, the LPF circuit 9, the chroma encoder circuit 10, and the DA converter 9 for the chroma signal C.

As described above, by using the first PLL circuit 5 and the second PLL circuit 6 equivalent to 14.31818 MHz.
The clock is generated at a frequency of 4 fsc.
If the clock of (14.31818 MHz) is composed of a free-run clock, there is a problem that the frequency shifts and a color phase shift between lines occurs, resulting in a non-standard signal. Is. Moreover, R
In the AMDAC device, a PLL circuit is usually used to synchronize a clock of 12.273 MHz with a clock of oscillating frequency 13.5 MHz. Therefore, in the present RAMDAC device 1, by using the first PLL circuit 5 and the second PLL circuit 6 having the same performance, the pixel clock of 12.273 MHz synchronized with the basic clock of 13.5 MHz and the clock of 14.31818 MHz are used. Are supposed to be synchronized. FIG. 3 shows a specific configuration diagram of the first and second PLL circuits 5 and 6.

First, in the first PLL circuit 5, 13.5M
The phase obtained by counting the basic clock 11 times with the 11 counter 18 which operates with the basic clock of Hz, and 9
The phase difference from the phase obtained by counting the VCO output clock 80 times by the 80 counter 21 working with the VCO output clock of 8.1818 MHz is detected by the phase comparator 19, and the voltage value giving the phase difference is integrator. 20.98.1818MHz voltage controlled oscillator (first VCO) 2 integrated by 20
2 into a control signal that determines the synchronization characteristic. As a result, the first VCO 22 is a VCO having a frequency of 98.1818 MHz synchronized with the basic clock having a frequency of 13.5 MHz.
Generates and outputs the output clock. Then, when the VCO clock is divided by the 8 counter 23 that counts eight times, a pixel clock having a frequency of 12.273 MHz is generated.

Similarly, in the second PLL circuit 6, the frequency 1
The phase obtained by the 6 counter 24 working by receiving the pixel clock of 2.273 MHz by counting the pixel clock as 6 times, and the 7 counter 28 working by receiving the clock of frequency 14.31818 MHz as obtained by counting the above clock 7 times The phase difference from the phase is detected by the phase comparator 26, the voltage value of the phase difference is integrated by the integrator 27, and 1
4.31818MHz Voltage Controlled Oscillator (Second VCO) 2
8 into a control signal that determines the synchronization characteristics, and as a result,
The second VCO 28 generates and outputs a clock having a frequency of 14.31818 MHz in synchronization with a pixel clock having a frequency of 12.273 MHz.

With this configuration, it is possible to prevent non-standard signals and prevent deterioration of image quality.

By taking the circuit configuration shown in FIG.
The ease with which digital processing of NTSC chroma encoding can be performed will be described below.

In the NTSC chroma encoding system, two color difference signals (RY) and (BY) are converted into two color subcarrier signals (fsc = 3.
(58 MHz), the chroma signal C after balanced modulation is expressed by the following equation 4.

[0041]

(Equation 4)

Therefore, the color difference signals (RY), (B-
When Y) is sampled with the clock having a frequency that is four times the color subcarrier frequency fsc, the chroma signal at each sampling is represented by the following equations 5 to 8.

[0043]

(Equation 5)

[0044]

(Equation 6)

[0045]

(Equation 7)

[0046]

(Equation 8)

As is clear from these equations, the chroma signals after sampling are RY, BY,-(R-
Y),-(BY), RY, BY,-(RY),
-(BY) ... is simply represented. In the present invention, since this is used, the sampling frequency is converted to a frequency four times the frequency fsc. Moreover, 14.31818M
Since it is expressed by a simple integer ratio of Hz: 12.273 MHz = 7: 6, it is possible to perform the above sampling frequency conversion by using simple linear interpolation as shown in FIG.

As described above, after the frequency-converted color difference signals (RY) and (BY) are applied with the LPF which limits the frequency to 1 MHz in accordance with the NTSC system, (NTSC ) The chroma encoder circuit 10 encodes the color difference signals to generate a chroma signal C. As a result, the band limitation defined by the NTSC system can be realized.

As described above, the frequency conversion from the pixel clock frequency to the frequency of 4 fsc is performed by the one-chip RAMD.
By implementing it in the AC device, it is possible to easily realize digital processing of NTSC encoding and its on-chip implementation. Therefore, it is possible to reduce the board scale as compared with the conventional system, and it is inexpensive. It can realize various systems.

(Modification of First Embodiment) In the first embodiment described above, the frequency is 4 fsc (14.31818 MHz).
, The color difference signal (BY),
Focusing on (RY), 2fsc (7.190)
Even if the frequency is converted to 9 MHz, the NTSC encoder section can be digitally configured. In this case, the chroma encoder circuit can be configured by the circuit shown in FIG. 4, and its timing chart is as shown in FIG.

The circuit of FIG. 4 will be described below. 2
The color difference signals (RY) and (BY) at the fsc rate are input to the same circuit in the form of offset binary, and the selector 29 outputs the color difference signals (RY) and (BY) to the frequency 2
The fsc clock is used as a control signal and multiplexed at each timing given at a frequency of 4fsc. afterwards,
The DFF 30 shifts one of the selected color difference signals by the reciprocal of the frequency 4fsc, that is, by the period. The shifted data A corresponds to A in FIG. Subsequently, FIG.
Signal a = 1, the EX-OR circuit 31 outputs “H”.
It is possible to invert the positive and negative of the data by inverting and "L" and adding +1 by the adder 32. On the other hand, when a = 0, the data of the selected color difference signal is output as it is. Here, the OR circuit 3
3 corresponds to underflow. The data output from the OR circuit 33 is shifted by the DFF 6 and the chroma signal C is output.

As can be understood from the timing chart shown in FIG. 5, the color difference signals (RY) and (BY) as the input signals of the chroma encoder circuit of FIG. 4 are 2fs.
given at c-rate. Therefore, even if the sampling frequency conversion circuit 8 of FIG. 1 performs frequency conversion to 2fsc, the same effect as that of the first embodiment can be obtained.

Although the DFFs 30 and 34 are inserted in FIG. 4, they are not always necessary if high-speed arithmetic processing is possible.

(Embodiment 2) Normally, for a chroma-encoded chroma signal C, its frequency band is 1M.
It is necessary to limit to about Hz. As a circuit for performing this band limitation, an LPF is provided in the preceding stage of the chroma encoder circuit 10.
(See FIG. 1) or by providing a BPF in the subsequent stage, the sampling frequency conversion processing unit can be provided with a 1 MHz band limitation function, that is, an LPF function. The latter case is the second embodiment.

The principle will be described below. Each of (a) to (e) of FIG. 6 shows a frequency band. First, 6.1365 MHz (12.273 MHz /
2) the color difference signal (R−) having the frequency band (FIG. 6A).
Y) and (B-Y) are multiplied by 7 (x times) (see FIG. 6).
(B)), data is interpolated every 6 (y) (see FIG. 6).
(C)). At that time, as can be seen from FIG. 6, the interpolation is 43 taps. At that time, at the same time as interpolation, 1MHz L
By multiplying by PF, it is 1/6 times (1 / y times) (FIG. 6 (d)). Although it seems complicated when written in the figure, it is sufficient to simply apply the LPF having the characteristics shown in FIG. 6C and then perform the linear interpolation as shown in FIG.

FIG. 7 shows a block diagram of the RAMDAC device 1A according to the second embodiment to which the above principle is applied.
Incidentally, the band after the chroma encoder is as shown in FIG. 6 (e).

With this structure, the same effects as those of the first embodiment can be obtained in the second embodiment, and moreover,
There is an advantage that the gate scale can be reduced as compared with the first embodiment.

(Embodiment 3) When the DA converter for luminance signal Y in the NTSC encoder section is constituted by a current source, as shown in FIG. 8 or 9, the current source 37 for video signal is used. Alternatively, by additionally arranging the current source cell 38 or 43 in parallel with 42, the composite synchronizing signal can be added to the video signal.

The operation of FIG. 8 will be described. In the figure,
Reference numeral 37 is a video signal current source, 38 is a composite sync signal current source (corresponding to another current source), 35 is a power supply potential, 36 is a load resistance, and 39 is a switch. As shown in FIG.
When the composite video signal is within the period T of the sync signal portion 47, the sync signal can be added to the video signal by controlling the switch 39 of FIG. 8 to be ON. At this time, the video signal with the composite sync signal is {V- (R. (I1 + I
2))}.

When the switch 39 is in the OFF state, the video signal is represented by (V- (R.I1)).

Conventionally, since the synchronizing signal is superposed on the video signal by using the digital section, an adder or a selector is required, and the accuracy of the DA converter is 1 bit larger than the number of bits of the video signal. Although necessary, the configuration like the third embodiment allows the current source 38 for the composite synchronizing signal and the switch 39 to easily configure the superimposing function unit.

Similarly, even in the case of FIG. 9, the functions and effects described above can be realized. In the figure, 42 is a video signal current source, 43 is a composite sync signal current source (another current source), 40
Reference numerals 41 and 41 are power supply potentials, 44 is a switch, and 45 is a load resistance. In this case, the synchronizing signal can be added to the video signal by controlling the switch 44 of FIG. 9 to be OFF at the synchronizing signal portion 47 shown in FIG.

The block configuration of the RAMDAC device according to the third embodiment corresponds to the configuration in which the DAC 13 of FIG. 1 is replaced with that of FIG. 8 or 9.

(Embodiment 4) In the configuration of Embodiment 1, as can be seen from FIG. 1, two DAs in total, that is, the DA converter 11 for the chroma signal C and the DA converter 13 for the luminance signal Y are used.
I needed a converter.

On the other hand, in the fourth embodiment, as shown in FIG.
11, the chroma signal C output from the chroma encoder circuit 10 and the luminance signal Y output from the delay adjustment circuit 12 in FIG. 1 are added by the adder 48, and the added signal is DA The converter 49 can output a composite video signal (Y + C) by performing digital-analog conversion. However, in this case, before the luminance signal Y is input to the adder 48, a separate sampling frequency conversion circuit 46, a horizontal edge enhancement processing unit 77, and It is necessary to further provide the delay matching circuit 76.

As a result, in the fourth embodiment, it is possible to reduce the number of DA converters by one and output the composite video signal.

(Fifth Embodiment) In the configuration of the first embodiment, as can be seen from FIG. 1, three RGB DA converters 4, a chroma signal C DA converter 11, and a luminance signal Y DA converter. A total of five DA converters of the device 13 were required.

On the other hand, the RAMD of the fifth embodiment
In the AC device, the three DA converters for RGB signal output can also be used as the respective DA converters for the luminance signal Y, the chroma signal C, or the composite video signal (Y + C) which are the output of the NTSC system. Is. FIG. 12 shows a block diagram of the DA converter.

That is, when connecting the RAMDAC device to a personal computer or the like, the first to third selectors 5 in FIG.
The A side is selected by 0, 51 and 52, and the RGB signal which is the output from the color palette 3 in FIG. 1 is selected. As a result, the first to third DA converters 53, 54 of FIG.
55 denotes an R signal (corresponding to the first primary color component signal here), a G signal (second primary color component signal), and a B signal (third third color signal).
The primary color component signal) is digital-analog converted and output.

On the other hand, when the RAMDAC device is connected to an NTSC TV or the like, each of the first to third selectors 50 to 52 selects the B side, and the chroma signal output from the chroma encoder circuit 10 in FIG. C, the luminance signal Y output from the delay adjustment circuit 12 in FIG. 1 and the chroma signal C are added by the adder 56 in FIG. 12 to obtain a composite video signal (Y + C), and a luminance signal Y, respectively. Selected,
These are digital-to-analog converted and output by the first to third DA converters 53 to 55, respectively.

In this way, the functions of the DA converters on the output port side of the RAMDAC device are all controlled by the three DA converters 53-53.
By making 55 also serve, the number of DA converters to be used can be reduced by two as compared with the case of FIG. At the same time, the fifth embodiment has an advantage that a composite video signal (Y + C) can be output in addition to both signals Y and C.

(Sixth Embodiment) Here, the delay adjustment circuit 12 of FIG. 1 used for delay adjustment of the luminance signal Y is used.
A horizontal enhance circuit is provided inside, and the horizontal enhance circuit itself tries to partially bear the function of delay adjustment.

Delay matching circuit 1 in the sixth embodiment
FIG. 13 shows a block configuration diagram of No. 2. In the figure, a portion 58 surrounded by a broken line is an example of a horizontal enhance circuit. The delay adjustment circuit unit 12 'includes a horizontal enhancement circuit 5
This is a part that realizes the remaining necessary delay time excluding the delay time realized in 8.

As for the enhancement component, the output data SB of the first DFF 59 and the output data SC of the third DFF 61 are added by the adder 62, and the adder output data which has been halved in level is added from the data SA to the adder 63. It is obtained by subtracting. Data S of this enhancement component
For D, the amount of enhancement can be adjusted by the GAIN circuit 64. The enhancement component adjusted by the GAIN circuit 64 is shifted by the fourth DFF 65 and then added by the adder 66 to the data S which is the luminance signal Y.
It is added to C. At this time, the enhancement component is the fourth DFF.
Since it is shifted by 65, the data C obtained by shifting the data SA by the third DFF 6 is used as the luminance signal.

Thus, the horizontal enhance circuit 58 is
It also has the DFF function for three. Therefore, the horizontal enhancement circuit section 58 is the same as the horizontal enhancement circuit section 58 shown in FIG.
Since it is possible to use the DFF function for only the number of pieces, the DFF required for the delay matching circuit 12 'of FIG.
In addition, the image quality can be adjusted as desired by adjusting the gain of the gain circuit 3 in FIG.

[Brief description of the drawings]

FIG. 1 is a RAMDA according to a first embodiment of the present invention.
It is a system block diagram of C device.

FIG. 2 From 12.273 MHz to 14.318 MHz
It is a figure which shows the model of the sample point at the time of frequency-converting to.

FIG. 3 is a diagram showing first and second PLL circuits.

FIG. 4 is a block diagram of a chroma encoder according to a modified example.

FIG. 5 is a timing chart of a chroma encoder according to a modified example.

FIG. 6 is a diagram showing frequency characteristics when the frequency conversion and the LPF are combined.

FIG. 7 is a RAMDA according to the second embodiment of the present invention.
It is a figure showing composition of C.

FIG. 8 is a circuit configuration diagram of a DA converter configured by a current source according to the third embodiment.

FIG. 9 is a circuit configuration diagram of a DA converter including a current source according to the third embodiment.

FIG. 10 is a diagram showing a composite video signal.

FIG. 11 is a block diagram showing a configuration of an NTSC encoder unit according to the fourth embodiment.

FIG. 12 is a block diagram showing a configuration of a DA converter according to the fifth embodiment.

FIG. 13 is a block diagram showing a configuration of a delay alignment circuit that also functions as a horizontal enhance circuit according to the sixth embodiment.

FIG. 14 is a functional block diagram of a conventional RAMDAC.

FIG. 15 is a block diagram of a conventional RAMDAC provided with an NTSC analog encoder.

[Explanation of symbols]

1 RAMDAC device, 15 RAMDAC unit, 16
NTSC encoder part, 5 first PLL circuit, 6 second
PLL circuit, 7 (RGB to Y, RY, B-
Y) conversion circuit, 8 sampling frequency conversion circuit, 9
LPF circuit, 10 chroma encoder circuit, 4, 11, 1
3 DAC.

Claims (11)

[Claims] 1. A RAMDAC device for reading out the stored three primary color component signals at the timing of a pixel clock, digital-to-analog converting them, and outputting them, while outputting the three primary color component signals as signals compatible with the NTSC system. Converting the three primary color component signals into a video signal and performing linear interpolation to frequency-convert at least the color difference signal in the video signal to a frequency four times the color subcarrier frequency, and further encode the color difference signal. Then, the NTSC
R characterized by outputting as a signal corresponding to the system
AMDAC device. 2. The RAMDAC device according to claim 1, wherein a clock having a frequency four times as high as the color subcarrier frequency synchronized with the pixel clock is generated, and the frequency conversion and the encoding are performed according to the clock. RAMDAC device characterized by. 3. The RAMDAC device according to claim 2, wherein in the video signal, the frequency conversion is performed only on the color difference signal, and the luminance signal is subjected to a delay adjustment process for a processing time for the color difference signal. A RAMDAC device characterized by performing. 4. The RAMDAC device according to claim 3, wherein the color difference signal is limited to a band determined by the NTSC system before the encoding after the frequency conversion or after the encoding. RAM
DAC device. 5. The RAMDAC device according to claim 4, wherein horizontal enhancement processing is performed prior to the delay adjustment processing for the luminance signal.
apparatus. 6. The RAMDAC device according to claim 3, wherein at the time of the frequency conversion, the color difference signal is limited to a band determined by the NTSC system simultaneously with the linear interpolation. 7. The RAMDAC device according to claim 6, wherein the frequency of the color sub-carrier is multiplied by x, where the ratio of the frequency of the color sub-carrier frequency to four times the frequency of the pixel clock is x: y. A RAMDAC device characterized by interpolating data for each y units and at the same time performing the band limitation determined by the NTSC method, and then multiplying the frequency of the color difference signal by 1 / y. 8. The RAMDAC device according to claim 2, wherein the signal compatible with the NTSC system is added with a composite synchronizing signal at the time of digital-analog conversion, and is output. 9. The RAMDAC device according to claim 8, wherein the DA converter for performing the digital-analog conversion is connected to the current source for the video signal and the current source in parallel via a switch. And a separate current source for the RAMDAC device. 10. The RAMDAC device according to claim 2, wherein the frequency conversion is separately performed on both the color difference signal and the luminance signal, and the luminance signal after the frequency conversion and a chroma signal obtained by the encoding are performed. RAMDA, wherein a composite video signal obtained by performing the addition processing of
C device. 11. The RAMDAC device according to claim 2, wherein in the step of performing the frequency conversion separately for both the color difference signal and the luminance signal and outputting the signal compatible with the NTSC system, An adder for adding the converted luminance signal and a chroma signal obtained by the encoding to obtain a composite video signal; a first primary color component signal of the three primary color component signals and the frequency-converted A first selector for selecting and outputting a luminance signal; a second selector for selecting and outputting a second primary color component signal of the three primary color component signals and the composite video signal; and a third selector of the three primary color component signals A third selector for selecting and outputting a third primary color component signal and the chroma signal; a first DA converter for digital-to-analog converting the output of the first selector; RAMD characterized and the 2DA converter, that the output of the second selector and a second 3DA converter for digital-to-analog converter for digital-to-analog converts the output of the second selector
AC device.