JPH0244990A - Method and device for video signal processing - Google Patents

Abstract

PURPOSE:To prevent deterioration in picture quality due to residual amount of a chrominance signal into a luminance signal even if the chrominance signal remains in the luminance signal by selecting the same frequency to a memory write clock and a read clock. CONSTITUTION:The title device consists of a video signal input terminal 1, a Y/C separation circuit 2, a demodulation circuit 3, an A/D conversion circuit 4, a signal processing circuit 5, a memory 6, a D/A conversion circuit 7, a modulation circuit 8, a mixing circuit 9, an output terminal 10, a switching circuit 11, a synchronizing separator circuit 12, a write clock generating circuit 13, a read clock generating circuit 14, a switching circuit 15, a write control circuit 16, a read control circuit 17, an identification circuit 18 and a microcomputer 19. The the frequency for the memory write and read clocks is made coincident to prevent expansion of the time base of a video signal due to the signal processing. Thus, no time base expansion and compression are caused in the chrominance signal resident in the luminance signal. Then the deterioration in the picture quality due to the remained chrominance signal in the luminance signal is not caused.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal processing method and apparatus using a memory.

[Prior Art] Conventionally, a technique is known in which a memory is used to perform still image processing, mosaic processing, noise reduction processing, etc. of a video signal.

For example, Nikkei Ellen I. Ronitas 4th
No. 06 (October 20, 1986) ppl, 195-
In No. 214, a VTR has a built-in Feel 1 memory, and this Feel 1 memory is used to improve image quality in still image playback, slow playback, and search mode. In the case of still image playback, when the magnetic tape is being fed at a normal speed, if there is a still image playback instruction, the video signal for 1 to 1 minute per file is extracted and written to the field 1 memory. Play repeatedly. Also, in the case of slow playback,
The magnetic tape is intermittently fed in the range of 115 to 1/30 times the normal playback speed, and when the magnetic tape stops, the video signal of the field part is loaded into the Field I memory, and the video signal is transferred from the field memory while the magnetic tape is moving. Read the signal. In this way, it is possible to reproduce instantaneous still images, and also to obtain slow-motion images with smooth movement regardless of the running speed of the magnetic tape. In the case of search reproduction, a portion with good 1-racking is extracted from the signal reproduced during the period in which the magnetic spatula 1~ scans the magnetic tape twice, and is imported into the field memory, and these portions are spliced together. Create a video signal for the screen and read it. As a result, noise bars are removed, and skew distortion is also removed by making write and read operations of Field 1 to memory independent, and by reattaching the synchronization signal to the read video signal.

In such conventional technology, in order to prevent phase discontinuity of color subcarriers at signal joints, the signals to be taken into the field 1 to memory are divided into luminance signals and color difference signals separated from color video signals, that is, component signals. It is used as a signal. This processing method is called component I.
This is called a signal processing method. By employing this processing method, it is possible to provide the S1-Robo effect, mosaic processing, and solarization effect.

Another example is NEC Technical Report VoQ.

4, 0 No. 3 (March 1987) pp, 4
In No. 9-52, a field memory is used for special effects and as a one-field delay element of a cyclic noise restrictor to reduce noise during normal playback.

Further, there are also known devices that have a picture-in-picture effect (for example, Nikkei Electronics No. 4.06 (October 20, 1986) pp. 1.78-1. 79).

[Problems to be Solved by the Invention] When performing processing such as special playback and noise reduction using field memory, conventionally, the method disclosed in the above-mentioned 1. As shown in FIG. 2, there are cases where a composite signal processing method is used to process color video signals as they are, and cases where a component processing method is used. When using a composite signal processing method, it is necessary to consider whether it is possible to reduce the memory capacity or the continuity of color subcarriers, which increases the complexity of the circuit and also reduces color reproducibility. There is a problem that the image quality deteriorates.

On the other hand, when using the component screw 1 to signal processing method, the signal taken into the field memory is the base handle 1.
- luminance signals and color difference signals, and synchronization signals and colorverse 1- signals do not need to be stored in the field memory, but can be added to the signals read out from the field memory, so the chrominance subcarrier There is no need to consider continuity.

On the other hand, in this component phone 1 signal processing method,
By expanding the frequency band of the luminance signal to include the frequency band of the chroma signal, the resolution of the reproduced image is increased. For this reason, during signal processing, a Y/C separation circuit consisting of a line comb filter is used to separate the luminance signal and chroma signal from the color video signal.

However, if the degree of separation of this Y/C separation circuit is not sufficient, a chroma signal will remain in the separated luminance signal. Further, even if the degree of separation of the Y/C separation circuit is sufficient, the chroma signal may leak into the luminance signal due to subsequent crosstalk between the luminance signal system and the chroma signal system.

The luminance signal in which the chroma signal remains and the color difference signal obtained by demodulating the separated chroma signal are processed using a field memory, and then the color difference signal is modulated to generate the chroma signal. This is mixed with the luminance signal to obtain a color video signal, but the chroma signal in this color video signal is the chroma signal obtained by modulating the chroma signal remaining in the luminance signal and the color difference signal. is added.

By the way, when generating a color video signal through signal processing, there is generally a slight phase difference between the color subcarriers of the chroma signal remaining in the luminance signal and the chroma signal obtained by modulating the color difference signal. Therefore, in the obtained color video signal, the hue and saturation change, and a color shift occurs with respect to the image formed by the color video signal before signal processing.

If the phase difference between these color subcarriers is constant, the chroma signal remaining in the luminance signal is small, so the color shift is fixed and hardly noticeable.However, conventionally, the chroma signal is formed by modulating the color difference signal. Since the chroma subcarrier of the chroma signal is generated by an independent oscillator, even if this oscillator operates stably, the frequency of the chroma subcarrier from this oscillator may not match the frequency of the chroma signal's chroma signal before signal processing. If there is even a slight difference, the phase difference in the color subcarrier between the chroma signal remaining in the luminance signal when forming the color video signal after signal processing and the chroma signal obtained by modulating the chrominance signal will change over time. It's going to change. For this reason, the hue and saturation of the obtained color video signal change over time, causing a time-varying color shift in the image.

As explained above, since the chroma signal remaining in the luminance signal is small, this color shift is also slight, but if it changes over time, it becomes noticeable and the image quality deteriorates significantly.

An object of the present invention is to provide a video signal processing method and device that solves such problems and can prevent image quality deterioration due to residual chroma signals in luminance signals in a component signal processing method. It's about doing.

[Means for Solving the Problems] In order to achieve the above object, the present invention uses the same frequency as the write clock and the read clock of the memory.

The present invention also phase-locks the read clock of the memory to a color subcarrier for modulating the processed color difference signal to generate a chroma signal.

Furthermore, the present invention uses a color subcarrier of a chroma signal before signal processing or a color subcarrier substantially phase-locked thereto as a color subcarrier for modulating a color difference signal after signal processing to generate a chroma signal. .

[By matching the frequencies of the write clock and read clock of the working co-memory, no expansion or contraction of the time axis of the video signal occurs due to signal processing. Therefore, the chroma signal remaining in the luminance signal is not expanded or compressed in the time axis. By phase-locking the memory read clock to the color subcarrier, the phase relationship between the chroma signal obtained by modulating the color difference signal with this color subcarrier and the residual chroma signal in the luminance signal read from the memory is fixed. If the color difference signal is modulated using the color subcarrier of the chroma signal before signal processing, or a color subcarrier that is almost phase-locked to this, the phase of the residual chroma signal in the luminance signal and the modulated chroma signal can be changed. The relationship becomes constant, and distortion of the chroma signal due to the residual chroma signal becomes less noticeable.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a video signal processing method and apparatus according to the present invention, in which 1 is a video signal input terminal, 2 is a Y/C separation circuit, 3 is a demodulation circuit, and 4 is an A/C separation circuit. D
Conversion circuit, 5 signal processing circuit, 6 memory, 9 D/A
a conversion circuit, 8 a modulation circuit, ji a mixing circuit, 10 an output terminal, 11 a switching circuit, 12 a synchronous separation circuit,] 3 a write clock generation circuit, 14 a read clock generation circuit,
15 is a switching circuit, 6 is a write control circuit, 17 is a read control circuit, 18 is an identification circuit, and 19 is a microcomputer.

In the figure, a color video signal input from an input terminal 1 is supplied to a Y/C separation circuit vt2, where it is separated into a luminance signal Y and a chroma signal C. The chroma signal C is supplied to the demodulation circuit 3 and demodulated into two color difference signals RY and BY. The luminance signal Y is supplied to the synchronization separation circuit 12 to separate the synchronization signal, and the write clock generation circuit 13 multiplies the horizontal synchronization signal to generate the write clock WCK.

This write clock WCK is supplied as a sampling pulse to the A/1 conversion circuit 4, and the luminance signal )' output from the Y/C separation circuit 2 and the color difference signal R-Y, 13 output from the demodulation circuit 3. -Y is digitized and supplied to the signal processing circuit 5. These digital signals are appropriately processed by the signal processing circuit 5, and are stored in the memory 6 under write control of the write control circuit 16, which is supplied with the synchronization signal from the synchronization separation circuit 12 and the write clock WCK from the active clock generation circuit 13. Written sequentially.

Further, digital signals are sequentially read from the memory 6 under the read control of the read control circuit 7 which is supplied with the read clock RCK supplied from the switching circuit 15, and after being processed appropriately by the signal processing circuit 5. , and are converted into analog signals by the D/A conversion circuit 7 to obtain a luminance signal Y' and two color difference signals RY' and BY'. These color difference signals R-Y
', BY' are supplied to a modulation circuit 8 and modulated with the color subcarrier SC from the switching circuit ] to generate a chroma signal C'. This chroma signal C' is mixed with the luminance signal Y' from the D/A conversion circuit 7 in the mixing circuit 9 to form a color video signal, which is output from the output terminal 10.

The microcomputer 19 includes a signal processing circuit 5, a switching circuit 1.1 . ．． 15. Thereby, the signal processing circuit 5 processes the digital signal from the A/11 conversion circuit 4 and the digital signal read from the memory 6 in accordance with the specified mode I. The demodulation circuit 3 outputs a color subcarrier WSC synchronized with the burst signal of the input chroma signal C and a color subcarrier RSC of a stable phase generated by a crystal oscillator, etc. Depending on the mode designation from the computer] 9 and the identification result from the identification circuit 18, one of the color subcarriers WSC and R5C is selected as the color subcarrier SC. This color subcarrier SC is supplied to a read clock generation circuit 14, and is multiplied to generate a read clock RCKS. The switching circuit]-5 selects either the read clock RCKS or the write clock WCK from the write clock generation circuit ↑3 as the read clock RCK in response to a command from the microcomputer]9 to the mode 1. The identification circuit 18 determines the frequency relationship between the color subcarrier WSC phase-synchronized with the burst signal of the input color video signal from the demodulation circuit 3 and the horizontal synchronization signal from the synchronization separation circuit 12, and inputs the signal to the input terminal 1. The video signal is a video signal that conforms to a standard format such as a broadcast reception signal (hereinafter referred to as a standard signal), or a video signal that deviates from this standard format such as a playback signal from a recording/playback device (hereinafter referred to as a standard signal). , a non-standard signal).

For example, in the case of the NTSC system, the frequency relationship between the general transmission wave and the horizontal synchronization signal is as follows, where f9° is the frequency of the former and fu is the frequency of the latter, and the identification circuit L8
identifies a video signal that satisfies this relationship as a 1C signal, and a video signal that does not satisfy this relationship as a non-standard signal.

In this embodiment, the switching circuit 15 is controlled by the mode I command from the microcomputer 9, so that when the read clock RCK is the same as the M-inclusive clock WCK and when the read clock RCK from the read clock generating circuit 14 is In the former case, the writing and reading of the memory 6 is said to be synchronous, and in the latter case, it is said to be asynchronous.

So, memory 6 -1,! ), we will explain the case of reading or synchronous. This is done as a noise suppression process.

In this case, the switching circuit 11 selects the first color printing general transmission wave WSC as the color subcarrier SC in response to a mode command from the microcomputer. In addition, the switching circuit]-
5 selects the write clock WCK as the read clock RCK.

Here, since the memory 6 is written and read with the same clock, the digital signal input from the A/D conversion circuit 4 to the signal processing circuit 5 and the A/D signal input from the signal processing circuit 5 are
There is no shift in the time axis, that is, no expansion or contraction of the signal between the digital signal outputted to the conversion circuit 7 and the digital signal outputted to the conversion circuit 7. Memory 6 is
Since this is a field 1-memory and a digital signal delayed by one field is obtained, a field cyclic noise reducer is formed together with the signal processing circuit 5, and noise suppression processing is performed.

Therefore, the degree of separation of the Y/C separation circuit 2 is insufficient, or there is crosstalk between the luminance signal system and the chroma signal system.
It is assumed that the chroma signal C remains in the luminance signal Y due to some reason. Here, if the phase of the chroma signal C with respect to the color subcarrier WSC is O, the amplitude of the chroma signal C is normalized to 1, and the amount of crosstalk of the chroma signal YC in the luminance signal Y is A, then the chroma signals C and YC are respectively It is expressed by the following equations (1) and (2).

C==e″(center 7″θ′ −-(2)YC=
= Ae'' slope θ (3) However, ω0 is the angular frequency of the color subcarrier WSC.

The chroma signal C shown in equation (2) is demodulated into a color difference signal, and after being processed for writing and reading in the memory 6 as described above, it is modulated in the modulation circuit 8 to obtain the chroma signal C'. However, the color subcarrier S supplied to this modulation circuit 8
If the angular frequency of C is ω1, then C′ −·j (tl), t+θ(4). Further, the chroma signal YC shown in equation (3) is processed as described in 1. together with the luminance signal Y, or the chroma signal YC' in the luminance signal Y' output from the D/A conversion circuit 7 is Memory 6 write clock WCK and read clock RCK
are equal, so YC'=Aej(OtsuGru6 1θ"Δ
It becomes θ・4Δθ Yuno. However, △0. is the chroma signal c
, c', and Δ02 is the phase difference between the luminance signals y and y' caused by circuit delay time.

The chroma signals c' and yc' shown in equations (4) and (5) are mixed in the mixing circuit 9 to form the chroma signal v of the color video signal.
C' or this chroma signal vC' is V C'
= eJ(to, \t+θn + A oJ (
ttl, t; → θ4 O θ1 + 71 θi)・・・・・・(
6) It becomes. Here, the color subcarrier S supplied to the modulation circuit 8
Since C is equal to the color subcarrier WSC output from the demodulation circuit 3, and therefore equal to the color subcarrier of the chroma signal C in equation (2), ω. =ω□, and equation (6) is expressed as follows.

VC' = (1+A e”I!11θ, →
Δθyon). J(ω,1+θn(6')) In other words, chroma signal 4 in the color video signal obtained at the output terminal 10.
As C remains, the chroma signal C becomes (''AeJ
(muθ・1Δθ^)).

Here, since the delay time of the circuit is constant, the phase difference △0□ between the luminance signals y and y' is constant, but the color subcarriers of the chroma signals c and c' are not phase locked. and,
80□ will change over time. The above formula (6')
Therefore, when Δ01 changes over time, the chroma signal VC
′ causes the hue and saturation of the image to change over time, resulting in a significant deterioration in image quality.

On the other hand, when the switching circuit 1 selects the color subcarrier WSC, since this color subcarrier WSC is generated from the burst signal of the chroma signal C, the color subcarrier SC1
Therefore, the color subcarrier of the chroma signal C' is phase-locked with the color subcarrier of the chroma signal C, and the phase difference 〇□ is fixed in time. For this reason, the deviation of the hue and saturation from the correct values due to the chroma signal vC' expressed by equation (6') is constant. Moreover, the amount of cross 1 hake is A
is generally small, so the color shift in the image caused by this is almost imperceptible. Even if the crosstalk amount A is small, if the phase difference Δ01 changes over time and the hue and saturation change over time, changes in image blurring will become noticeable.

In this way, the talos h of the chroma signal C is added to the luminance signal Y.
- Even in the evening, image quality deterioration due to color shift can be prevented.

The second point is the same even when a non-standard signal is input manually from the input terminal 1.

First, a case where writing and reading from the memory 6 are asynchronous will be explained. This process includes still image processing, enlargement/reduction processing, variable magnification processing, horizontal reversal processing, mosaic processing and variable size processing, and bit removal processing (processing to create an oil painting-like display by removing lower bits). It is performed during various signal processing such as solarization processing (also called solarization processing) and gradation level variable processing. In these signal processings, it is not necessary to process the signal input from the A/D conversion circuit 7 to the signal processing circuit 5 in synchronization with the signal read out from the memory 6, so writing and reading from the memory 6 are performed in synchronization. There's no need to do it. In particular, since non-standard signals reproduced from home VTRs have jitter, etc., asynchronous signals have the advantage that stable video signals (from which jitter and the like are removed) can be obtained from the memory 6.

Here, the designation to each mode 1 as described in "1" is performed by the microcomputer], 9, and the switching circuit 15 receives the read clock RCK from the read clock generation circuit 14.
Select S. Also, the video signals handled here are NTS
If the C method is used, the frequency relationship between the horizontal synchronization signal and the color subcarrier is expressed by the above equation (1), and the write clock generation circuit 13 generates the write clock WCK for synchronization, and the read clock generation circuit]4 generates the read clock RCKS by multiplying the color subcarrier SC by four.

First, a case will be described in which the writing and reading of the memory 6 are asynchronous and the color video signal input from the input terminal is a standard signal.

In this case, the identification circuit 18 determines the frequency relationship between the color subcarrier WSC from the demodulation circuit 3 and the horizontal synchronization signal from the synchronization separation circuit 12, but since these do not satisfy the relationship of equation (1) above, , identifies the input color video signal as a standard signal, controls the switching circuit "-1-" together with the mode command of the microcomputer 19, and outputs the color subcarrier WSC.
is selected as the color subcarrier SC.

Therefore, the frequency relationship between the color subcarrier SC and the horizontal synchronization signal from the synchronization separation circuit 12 satisfies Expression (1). Therefore, the write clock WCK and the read clock RCK have the same frequency and phase. [Since this means that the data is being read, it is the same as when writing and reading to the memory 6 are synchronized. Further, since the color subcarrier SC supplied to the modulation circuit 8 is phase-locked with the color subcarrier of the chroma signal C, the chroma signal of the color video signal obtained at the output terminal 10 is Δ01. This is expressed by equation 1 (6') where .DELTA.02 is constant. Therefore, it is possible to prevent image quality deterioration due to cross-reflection of chroma signals.

Next, the case where the input terminal is a color video signal or a non-standard signal will be explained. For example, household V 1”
The R reproduced color video signal has skew distortion and jitter, and the S/N ratio has also deteriorated. For this reason, the phase of the color subcarrier WSC varies, albeit slightly. For this reason, if this color subcarrier W SC is used as the color subcarrier of the chroma signal C', the phase of this chroma signal C' will fluctuate, causing deterioration in image quality.

Therefore, the identification circuit 18 uses the color subcarrier W from the demodulation circuit 3.
The frequency relationship between the SC and the horizontal synchronization signal from the synchronization separation circuit 12 is determined, and the phase fluctuation of the color subcarrier WSC is used to determine whether this is the case. Error video is identified as a non-standard signal. Based on this identification result and the designation to mode 1 of the microcomputer 19, the switching circuit 11 selects the stable color subcarrier R8C from the demodulation circuit 3 as the color subcarrier SC.

As a result, a stable read clock RCK is obtained from the switching circuit 15, and the luminance signal Y', color difference signals Tl-Y', and BY' read from the memory 6 are stable signals without skew distortion or jitter. Become. Since these color difference signals RY' and BY' modulate the stable color subcarrier SC in the modulation circuit 8, a stable chroma signal C' is obtained and distributed.

In the case of a non-standard signal, since the N-inclusive clock WCK and the read clock are not synchronized, strictly speaking, the A.11 relationship between the chroma signal YC' and the chroma signal C' in the luminance signal Y' is not constant. However, as described in -1-, since the stable color subcarrier SC is modulated, a stable chroma signal C' is obtained, and the image quality is improved.

As described above, in this embodiment, even if a chroma signal remains in the luminance signal, image quality deterioration due to this can be prevented.

FIG. 2 is a block diagram showing a specific example of the A/D conversion circuit in FIG. In the generating circuit, 28 is an output terminal.

Further, FIG. 3 is a diagram showing the timing relationship of signals of each part in FIG. 2, and signals corresponding to those in FIG. 2 are given the same reference numerals.

In FIGS. 2 and 3, the write clock WCK with a frequency of 4f96 is inputted from the input terminal 23 as described above, and the pulse generation circuit 27 receives the write clock WCK from the input terminal 23.
The switching control signals sw, sw' and the sampling pulse SP of the luminance signal Y,] and the sampling link pulse SP2 of the color difference signals R-Y and B- are generated. Here, −
As an example, the frequency of the sampling pulse SI) is 4f56, and the sampling pulse SP2 of the color difference signal I, Y, B-Y whose frequency band is sufficiently narrow relative to the luminance signal Y is
The frequencies of are respectively f, , , /2. In this way, by lowering the frequency of the sampling pulse SP2, a low-speed and inexpensive A/D converter can be used for the color difference signals R-Y and B-Y.

The luminance signal Y input from the input terminal 20 is supplied to the A/D converter 25 and converted into a digital luminance signal DY using the sampling pulse SPI. In addition, input terminal 2
1. ．． The color difference signals R-Y and B-Y inputted from 22 are supplied to a switching circuit 24, and are alternately selected by switching control signals sw and sw to form time-division multiplexed (dot sequential) color difference signals R/Y.
B is generated. Here, the switching control signal SW is the write clock WCK (i.e., the sampling pulse S P
], ) is a pulse signal with a duty ratio of 50% and a cycle of 8 times that of the switching control signal "W". The switching control signal "W" is an inverted version of the switching control signal SW. The color difference signals R-Y,
Select B-'Y. This time-division multiplexed color difference signal R/B is supplied to the A/D converter 26, and the time-division multiplexed color difference signal D
Converted to R/B. Therefore, the color difference signal R-Y.

This means that B-Y has been digitized using sampling pulses each having a frequency of f, , /2.

The digital luminance signal DY and the digital time-division multiplexed color difference signal DR/B are outputted from the output terminal 28 separately or combined as appropriate.

In this specific example, since the color difference signals R-Y and B-Y are time-division multiplexed and digitized, the A/D converter for these can be shared, and this A/D converter can be used at a low speed. The operation can be made inexpensive.

FIG. 4 shows the first circuit for the A/D conversion circuit 4 shown in FIG.
, is a block diagram showing a specific example of the D/A conversion circuit 7 in the figure, in which 29.30 is an input terminal, 31 to 33 are D/A converters, 34 is a pulse generation circuit, and 35 to 37 are output terminals. It is.

Moreover, FIG. 5 is a diagram showing the timing relationship of the signals of each part in FIG. 4 when processing such as signal rearrangement and time axis conversion is not performed in the signal processing circuit 5, and corresponds to FIG. The same symbols are given to the signals.

4 and 5, the read clock RCK is input from the input terminal 30, and the pulse generation circuit 34 generates sampling pulses SPI'SP2', SP
2# is generated. Here, sampling pulse SPI
' has a frequency of 4f, , and the sunblink pulse S
P2' and SF3'' have frequencies f and ./2, respectively, and are inverted from each other.

Digital luminance signal DY' input from input terminal 29
is supplied to the D/A converter 3], and the sampling pulse S
It is converted into an analog luminance signal Y' using PI'. Further, the digital time-division multiplexed color difference signal DR/B' input from the input terminal 29 is supplied to the D/A converter 32, and is converted into a digital color difference signal RY□ by the sampling pulse SP2'.

R, -Y3. are sampled and linked and converted into analog color difference signals RY'. Similarly, the D/A converter 33 converts the digital time-division multiplexed color difference signal DR/B' into digital color difference signals B-Yo, B-Y2° or sampler' using the sampling pulse SP2'', The luminance signal Y' and the color difference signals RY' and l3-Y' are outputted from output terminals 35 and 36.degree. 37, respectively.

As mentioned above, in the A/D conversion circuit 4 shown in FIG.
The color difference signals R-Y and B-Y are dot-sequentially converted, and the color difference signals R-Y and B-Y are alternately sampled and digitized by the sampling pulse SP2. In the D/A conversion circuit 7 shown in FIG. 4, the D/A converter 32 converts the digital time-division multiplexed color difference signal DR/B' into the digital color difference signal RY1. R-
Y3. ... is taken in and converted into a color difference signal RY', and the D/A converter 33 outputs the sampling pulse SP2
'', the digital color difference signals B-Y, , B-
Y2. ... is taken in and converted into a color difference signal B-Y'. In this way, since each digital color difference signal is captured from the same digital time-division multiplexed color difference signal DR/B' by sampling pulses SP2' and SP2'' having mutually opposite phase relationships, the obtained color difference signal RY', There is no time lag between B-Y', and therefore no color shift occurs in the image either.

FIG. 6 shows the A/D converter 4 shown in FIG. 2 and the A/D converter 4 shown in FIG. 4 when the A/D converter 4 shown in FIG. 3 is a timing chart showing the operation of the D/A converter 7.

In FIGS. 2 and 6, the pulse generation circuit 27 is
From the write clock W CK input from the input terminal 23, the color difference signal R-Y in the time division multiplexed color difference signal R/B
A sampling pulse SP2 is generated to sample the rear part of the color difference signal B-Y and the front part of the color difference signal B-Y. In this case, the sampler interval between the color difference signal RY and the next color difference signal B-Y is set to be one period of the write clock WCK. As a result, the sampled color difference signals R-Y and B-Y have information content at times when they are close to each other.

In FIGS. 4 and 6, the D/A conversion circuit 7 is
The D/A converter 32 converts the digital time-division multiplexed color difference signal DB.
A sampling pulse SP2' is formed to capture the color difference signal RY of /B', and the D/A converter 33
The sampling pulse SP2'' is formed so that the color difference signal B-Y is taken in. In this case, the timing of taking in the color difference signal B-Y is determined by the digital time-division multiplexed color difference signal D.
Since the period of the color difference signal B-Y in R/B' is long, it can be set in a sufficiently wide range. However, since the color difference signals R-Y and B-Y are sampled and digitized at almost the same timing in the A/D conversion circuit 4, the D/A
By bringing the input timings of the converters 32 and 33 as close as possible, the obtained color difference signals R-Y' and B-
It is better to make the time difference of Y' as small as possible. For this purpose, the difference between these acquisition timings is minimized to one cycle of the read clock RCK.

As described above, it is possible to prevent time deviations caused by time-division multiplexing of the color difference signals R-Y and B-Y, and thus color deviations in image quality caused by this.

Next, the operation of the D/A conversion circuit 7 shown in FIG. 4 when performing the mosaic process in FIG. 1 will be explained with reference to FIG. Here, the length of one side of the mosaic is 2/f. That is, it is eight times the period of the sampling pulse SPI'.

As shown in FIG. 7, the digital luminance signal DY' input to the D/A converter 31 has the same information content during the eight cycles of the sampling pulse SPI' due to processing in the signal processing circuit 5, etc. ing. Then, in the next period of eight cycles, the information content on the sample is shifted by eight cycles from the previous period.

On the other hand, in the case of mosaic processing, the luminance signal Y and the color difference signals RY and BY must be sampled and digitized at the same timing within the mosaic. However, the color difference signal [-Y.

Since B-Y are time-division multiplexed by the A/D conversion circuit 4 shown in FIG. 4, they cannot be sampled and digitized at the same timing.

By the way, even if the color difference signals RY and BY are not sampled as described in item 1, it is sufficient as long as there is no color change within the mosaic. As shown in FIG. 5, the D/A converter 32
．． 33 is constant, the color difference signal R-
Since the timing of capturing Y and B-Y is greatly delayed, the colors change within one mosaic.

Therefore, as shown in FIG. 7, the color difference signal RY of the digital time division multiplexed color difference signal DR/B' and the next color difference signal B-
The border with Y is the border of the adjacent mosaic "+1"-2+
The mosaic processing is performed so that the D/A converter 3
2 takes in the rear part of the color difference signal RY in the digital time-division multiplexed color difference signal DR/B', and sends it to the D/A converter 33.
captures the front part of the color difference signal B-Y, and
The capture pulses SP2' and SP2' are formed so that the time difference between these capture timings is a minimum of one period of the read clock RCK. As a result, within the same mosaic, the information contents of the color difference signals RY' and BY' do not change, and no color change occurs.

Now, mode specification for the various signal processing mentioned earlier, such as still image processing, is shown in the microcomputer 19 in Figure 1.
It is carried out by Conventionally, a signal line has generally been assigned to each mode signal. For this reason, as the number of signal lines increases, the number of signal lines also increases.
For example, when a circuit for capturing such a mode signal provided in the signal processing circuit 5 or the like is integrated, the number of pins increases, which poses a practical problem. Therefore, a mode signal acquisition circuit according to the present invention that solves this problem will be explained.

FIG. 8 is a block diagram showing a specific example of a circuit for taking in a signal to the mode 1, in which 38 to 40 are input terminals, 41 is a protection circuit for taking in the signal to the mode 1, 42 is a divisor circuit, 43 is a delay circuit, 44 is a coincidence detection circuit, and 45 is an antenna key 1-14.
6 is a register for shift 1, 47 is a latch circuit, and 48 is an output terminal.

[Microcomputer] 9 is a timing shown in FIG. 9, and includes a serial mode signal MOD having a number of bits corresponding to the number of modes to be set, a serial clock MSC for taking in this mode signal MOD, and a mode signal MOD.
A synchronization signal RES indicating the start and end of the process is output.

Therefore, in FIGS. 8 and 9, first, the input terminal 40
When the synchronization signal RES is input to the
is supplied to the anchor 45 and delayed by the delay circuit 43 to form reset I to pulse RP.

The divisor circuit 42 resets I to pulse RP resets 1 to
It is reset by being supplied to terminal R. This reset 1~timing is the mode signal MO input to the input terminal 38.
Before D starts to be supplied, set I becomes like this.
- The delay time of the delay circuit 43 is set so as to achieve the timing.

Thereafter, the mode signal MOD is input from the input terminal 39, and the clock MSC is input from the input terminal 38, and the signals MOD1 to MOD are sequentially taken into the shift register 46 bit by bit by the clock MSC. This shift register 46 contains bins 1 to 4 of the mode signal MOD.
It has two stages, and the mode signals M and OD are sequentially input from the first pin l-.

On the other hand, the divisor circuit 42 inputs the input clock signal MSC one bit at a time, and the revised value is supplied to the coincidence detection circuit 44. This coincidence detection circuit 44 is set with a base 19 value equal to the pitch 1 to number of the mode signal MOD, and when the counted value of the divider circuit 42 matches this reference value, that is, the mode signal MOD is input. When finished, a high level match signal E is output. At this time, all the pins I of the mode signal MOD are taken into shift 1 to register /36.

After that, there is no clock MSC input, so the matching circuit 44
continues to output a high-level coincidence signal E. Then, when the synchronization signal RES of Kin is input from the input terminal 40, the AND gate 45 is turned on by the coincidence signal E.
This synchronization signal RES passes through A1 to K1-45,
The latch pulse RC is supplied to the enable control terminal G of the latch circuit 47. As a result, the mode signal MOD taken into the shift 1 heresister 46 is transferred to the launch circuit 4.
7 and output from the output terminal 48. Also,
The input synchronization signal RES is delayed by the delay circuit 43 and becomes the reset 1-pulse RP.
2 is reset to 1 and the output E of the coincidence detection circuit 45 becomes low level. Therefore, 1-45 are turned off. In this way, the signal MOD is correctly taken into MOD1.

According to this specific example, when the number of modes increases, it is sufficient to increase the number of pins of the mode signal MOD and change the reference value set in the matching circuit 44 accordingly. Regardless of the number of modes set, the signal line from (1st session) to the mode signal acquisition circuit is
Only three signal lines are required to transmit the mode I signal MOD, the clock MSC, and the synchronization signal RES, and even if the mode signal acquisition circuit is integrated into an IC, the number of pins will increase. There's no need.

Note that the mode signal is taken in within the vertical blanking period of the color video signal. This is to prevent the mode switching portion from appearing on the screen. Furthermore, by capturing the mode signal once every field, even if the mode designation is erroneous due to the influence of noise, the influence can be minimized. The mode capture protection circuit 4 prevents an erroneous mode I signal from being captured, for example, when the field length changes when the mode changes.

The synchronization signal RES may be any signal that is vertical and included within the ranking period; for example, a vertical synchronization signal can be used.

Further, when the delay circuit 43 outputs the coincidence signal E, the synchronization signal RES is input to the latch circuit 47 via the antgame 1 to the circuit 45, and then
A time difference is provided for closing the circuit 45.

Note that although the above embodiment has been described using the NTSC system as an example, other standard systems may be used.

[Effects of the Invention] As explained above, according to the present invention, the phase relationship of the chrominance subcarrier between the crosstalk component of the chroma signal to the luminance signal before signal processing and the chroma signal after signal processing is made constant. Therefore, even if the luminance signal and chroma signal are added after signal processing, image quality deterioration due to interference between the chroma signal and the cross 1 hake component in the luminance signal can be minimized.

Further, according to the present invention, even if color difference signals are processed point-sequentially,
By arranging the sampling positions close to each other, it is possible to minimize the deterioration of the transient characteristics of the color signal due to point-sequential sampling.

Further, according to the present invention, in mosaic processing when color difference signals are processed point-sequentially, by making the acquisition phases of the color difference signals close to each other during D/A conversion, the switching positions of the signals can be made to almost match. It is possible to prevent color changes within the mosaic.

Furthermore, according to the present invention, by serially transmitting mode signals, many mode specifications can be made with a small number of signal lines, and by protecting the mode I signal from being taken in, it is possible to prevent malfunction of the taking in. Never.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the video signal processing method and apparatus according to the present invention, and FIG.
A Broschiff diagram showing a specific example of a D conversion circuit, FIG.
FIG. 4 is a block diagram showing a specific example of the D/A conversion circuit in FIG. 1, and FIG. 5 is a diagram showing an example of the timing relationship of signals in each part in FIG. 4. Figure 6 shows an example of Figure 2, Figure 4.
Figure 7 is a diagram showing the timing relationship of signals in each part in Figure 4 in mosaic processing, Figure 8 is a signal processing circuit in Figure 1, etc. FIG. 9 is a block diagram showing a specific example of a mode signal acquisition circuit used in the present invention, and FIG. 9 is a timing chart showing the operation of this specific example. 1... Color video signal input terminal, 2...
・Y/C separation circuit, 3 ・・Demodulation circuit, 4・・・・A/
D conversion circuit, 5... Signal processing circuit, 6... Memory, 7. D/A conversion circuit, 8... Modulation circuit, 9...
. . . Mixing circuit, 10 . . . Output terminal for color video signal, "-1 switching circuit, 12 . . . Sync separation circuit,] 3
Write clock generation circuit, 4... Read clock generation circuit, 15... Switching circuit, 16... Write control circuit, 17... Read control circuit, 18 Separate circuit, 19 - Microcomputer .

Claims (1)

[Claims] 1. Demodulate the chroma signal into a color difference signal, write the color difference signal and a luminance signal extending to at least the frequency band of the chroma signal into a memory, and extract the color difference signal and the luminance from the memory. A video signal processing method that reads a signal, modulates the read color difference signal with a color subcarrier to generate a chroma signal, mixes the chroma signal with the luminance signal read from the memory, and outputs the mixed signal. A video signal processing method, characterized in that the frequency of a write clock for controlling writing of the memory and the frequency of a reading clock for controlling reading of the memory are made equal. 2. Demodulating the chroma signal into a color difference signal, writing the color difference signal and a luminance signal extending to at least the frequency band of the chroma signal into a memory, reading the color difference signal and the luminance signal from the memory, In the video signal processing method, the read color difference signal is modulated with a color subcarrier to generate a chroma signal, and the chroma signal and the luminance signal read from the memory are mixed and output. A video signal processing method comprising phase-locking a memory read clock to the color subcarrier. 3. The video signal processing method according to claim 1 or 2, wherein the write clock and the read clock of the memory are the same clock. 4. The video signal processing method according to claim 3, wherein the clock is generated by multiplying a horizontal synchronization signal of the luminance signal before the signal processing. 5. The video signal processing method according to claim 3 or 4, wherein the color subcarrier is phase synchronized with the burst signal of the chroma signal before demodulation. 6. Video signal processing according to any one of claims 1 to 5, characterized in that the color subcarrier frequency of the chroma signal before demodulation and the horizontal synchronization signal frequency of the luminance signal before processing do not satisfy a standard system relationship. Method. 7. Claims 1 and 2, wherein the memory write clock is generated by multiplying the horizontal synchronization signal of the unprocessed luminance signal, and the memory read clock is generated by multiplying the color subcarrier. Featured video signal processing method. 8. Claim 7, wherein the chroma subcarrier frequency of the chroma signal before demodulation and the horizontal synchronization signal frequency of the unprocessed luminance signal satisfy a standard system relationship, and the chroma subcarrier frequency is the chroma signal before demodulation. A video signal processing method characterized by phase synchronization with a burst signal of a signal. 9. In claim 7, the chrominance subcarrier frequency of the chroma signal before demodulation and the horizontal synchronization signal frequency of the unprocessed luminance signal do not satisfy a standard system relationship, and the chrominance subcarrier is stable. A video signal processing method characterized by outputting from an oscillator. 10. A demodulation circuit that demodulates a chroma signal into a color difference signal, a memory that stores the color difference signal and a luminance signal extending at least to the frequency band of the chroma signal, and writes the color difference signal and the luminance signal in the memory. a write control circuit for controlling, a reading control circuit for reading and controlling the color difference signal and the luminance signal from the memory, and a modulation circuit for generating a chroma signal by modulating the color difference signal read from the memory using a color subcarrier; , a video signal processing device comprising a mixing circuit that mixes the chroma signal and the luminance signal read from the memory, generating a reference color subcarrier phase-synchronized with the color burst of the chroma signal before signal processing. A first means;
second means for multiplying the reference color subcarrier to generate a read clock for the memory; third means for supplying the read clock generated by the second means to the read control circuit; and fourth means for supplying a color subcarrier to the modulation circuit as the color subcarrier. 11. A demodulation circuit that demodulates the chroma signal into a color difference signal, a memory that stores the color difference signal and a luminance signal extending at least to the frequency band of the chroma signal, and controls writing of the color difference signal and the luminance signal in the memory. a write control circuit; a read control circuit that reads and controls the color difference signal and the luminance signal from the memory; a modulation circuit that modulates the color difference signal read from the memory with a color subcarrier to generate a chroma signal; A video signal processing device comprising: a mixing circuit for mixing a chroma signal and a luminance signal read from the memory; a clock generation circuit that generates a clock by multiplying a horizontal synchronization signal; a means for generating a reference color subcarrier that is phase-synchronized with a burst signal of the chroma signal before the signal processing; means for providing a write clock for a control circuit and a read clock for the read control circuit;
A video signal processing device comprising means for using the reference color subcarrier as a color subcarrier of the modulation circuit. 12. A shift register that sequentially captures a mode signal consisting of received n (where n is a positive integer) bits of serial data along with the mode signal using an n-bit serial clock, and a a mode capture protection circuit that determines the mode signal based on the received synchronization signal and generates a latch pulse upon completion of reception of the mode signal; and the mode signal captured by the shift register by the latch pulse. A mode signal acquisition circuit characterized by comprising a latch circuit that latches. 13. The mode signal acquisition circuit according to claim 12, wherein the mode signal, clock, and synchronization signal are received during a vertical blanking period of a video signal.