JPS61196497A - Memory control circuit - Google Patents

Abstract

PURPOSE:To lower remarkably a scale of a memory by simultaneously inputting address designating data of different designating positions to a memory capable of reading and writing at the same time. CONSTITUTION:With respect to a memory RAM 21 capable of performing a writing and a reading at the same time (a condition in which designated addresses are different) address designated data from address designating circuits 23, 25 is simultaneously inputted. In this case, shift speeds of one address designating data and the other address designating data are made different by clock frequencies 3fsc and 4fsc so as to make the respective address designating positions different.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a memory control circuit, and is particularly designed to reduce memory capacity. analog co
In the digital television data transmission system using AC signals, the signal format is as shown in FIG. D is the data section, 100s/
Pull (6,98μs@C), CffR beam c! ! Signal section, 248 samples (17,3μ8・C), LUMA
is the luminance signal part, with 496 samples (34,6μ5
ec). These signals have a horizontal line of 910
The chroma signal part Cf (R is compressed by ten times), and the luminance signal part I
, Uμ are compressed by 7〇Here, focusing on the luminance signal part LUMA, in order to reproduce the distortion, it is first necessary to expand it to 4/3.

The luminance signal section LUMA is normally 4 X fac (f
3/3 at the sampling rate of ac; color subcarrier frequency)
To 4! Since it is compressed by E, in order to expand it to 4/3, it is expanded at a rate of 3xfac. A circuit for performing this data expansion is constructed as shown in FIG.

The input is taken into a random access memory (hereinafter referred to as RAM) 12k or 12B via the first selector 11. Addresses of 12B in the RAM 12 are designated by 13B in the corresponding address designation circuits 13, respectively. The addressing circuit 13, 13B, is composed of a counter that counts the input clock and a decoder that decodes the counter output, and the address transition speed changes depending on the frequency of the input clock. For addressing circuits lJA, , JjB,
A clock of 3 fsc or 4 fsc can be inputted arbitrarily through the clock switching circuit 15.

Now, RAMJ ZA is in the read state and RA12B is in the write state.
The fsc clock is input to the addressing circuit 13AK through the AND circuit 16 and the clock switching circuit 15, and the 4 fsc clock is input to the addressing circuit 13B through the AND circuit 11 and the clock switching circuit 15 in response to the write gate signal. Further, the selector 11 introduces the input signal to RAMZ2B, and the selector 14 introduces the input signal to RAMJ!
Outputs the signal from A.

In the next 2 ins, the above read/write state is changed to RA
Inverted between MJ2A and 228.

This switching is performed by a line switching signal.

As a result, the data written using the 4fsc clock as a reference will be read out using the 3fsc clock as a reference, and the output data will be expanded to 4 times. [Problems with Background Art] The above-mentioned conventional In the data expansion circuit of RAV12fi
, , 11B have the same capacity and have a much larger memory scale.

[Purpose of the invention]

This invention has been made to address the above-mentioned circumstances, and its purpose is to provide a memory control circuit that can significantly reduce the size of memory used to decompress and output data. Our goal is to provide the following.

[Summary of the invention]

In order to achieve the above object, the present invention provides a memory RAM f that can be written and read simultaneously (provided that the designated addresses are different), as shown in FIG.
Addressing data from addressing circuits 23 and 25 is simultaneously input to f1. In this case, not only do the respective addressing positions differ, but also the transition speeds of one addressing data and the other addressing data are made different by the clock frequencies 3 fac and 4 tea K.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows one embodiment of the present invention, and a MAC signal (explained in FIG. 3) is input to the random access memory 21. In FIG. This RAMj J includes write and read designation bits in its address data, so that
By specifying different addresses, writing and reading can be performed at the same time. Therefore, the input line and output twin are provided separately.

The read address of the RAMj 1 is specified by data from the read address designation circuit 23, and the write address is specified by data from the write address designation circuit 25. The read addressing circuit 23 consists of a clock that counts 3 fsc clocks from the AND circuit 22 and a decoder that decodes the output of this counter. It consists of a counter that counts the clocks of , and a decoder that decodes the output of this counter. The AND circuit 22 outputs a K,3-fee clock when the read gate signal is at a low level, and a blanking pulse train, for example, is used as the read gate signal.

-17t, the AND circuit 24 outputs a 54faa clock when the write gate signal is at a high level, and this write gate signal is obtained from a timing circuit that detects the luminance signal period. Furthermore, initial setting values are input to the read address designation circuit 23 and write address designation circuit 25 in order to designate different addresses, respectively. The initial setting value is inputted, for example, at the leading edge of the luminance signal LUMA.

According to this invention, since the RAh121 is configured to perform writing and reading at the same time, its processing efficiency is significantly improved, and the memory capacity of the decompression processing circuit is reduced to about TK compared to the conventional one. It is decreasing.

FIG. 2 is a timing chart shown to explain the operation of the circuit of the present invention described above.

Now, in order to understand the explanation, the luminance signal data of the input signal is 8 bits in series, and RAMZ 1 is also 8 bits.
This will be explained assuming that it is a bit capacity. In the case where the MAC signal is multiplied by Suff2, the luminance signals f, t
In 7MA, one block is included in one horizontal period IH, but
The arrangement positions for the chroma signal CHR and data D are, for example, random as shown in the figure. In addition, the luminance signals are also placed at random positions. In addition, the read address designation circuit 23
, it is assumed that the write address designation circuit 25 uses a decimal counter.

Here, assuming that each of the addressing circuits 23 and 25 is initialized to start from addresses 11'' and @9@, respectively, the read address is set to 1 by the read clock of 3fsc, as shown in FIG. The change from address 111 is repeated.On the other hand, the write address repeats the change from address 9 to address 8 using the clock of 4f5c.In the example of Fig. 2, at time t
The data written at time t2 will be read at time t2.

As described above, in this invention, a single RA
Data expansion can be obtained using M.

Next, the relationship between the number N of bits for 12 input signals, the number of bits of the conversion RAM x, and the frequencies of the write and read clocks will be explained.

Write clock frequency 1nHz Set read clock frequency to mHz (n>m) (the reverse is also possible) Then 1 ,1 Writing time, -XN = 5 hours n Readout time; fragrance Xl = base time I will make a hail.

The maximum time difference between writing and reading is N N-N (n-m) time m n mn . To find out how many bits of the read clock this corresponds to, we get: Tantachi+1:N(n-m) hi, tmn
m Corresponds to n.

Therefore, if the number of bits of the RAM is increased by a maximum of five bits, the positions of the write address and the read address can be shifted.

Also, considering 1 bit to compensate for the deviation, (for the minimum number of bits N (same as the number of input signal bits), if you prepare s + "-Ω fuse + 1 bit ORAM, the address transition cycle by the write clock will be reduced. Regardless of the time position of the address transition cycle by the read clock, as long as the initial designated positions are different, the same address will not be designated.

The above explanation was about the luminance signal LUMA, but
A similar idea can be applied to sampling frequency conversion of chroma signals.

That is, as shown in FIG. 2, when the data is 14 bits, the write address of the chroma RAM is generated at a position synchronized with the chroma signal, and the read address is generated at a position synchronized with the previous RAM 21. 14 bits are generated.

〔Effect of the invention〕

As explained above, according to the present invention, compared to the conventional method, 2n-bit to τ compression can be realized with 4-n+1 bits of memory, and 10-bit compression can be realized with n+1 bits. In a system using a large capacity such as a line data memory, the number of elements can be significantly reduced, which is advantageous for integrated circuits.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a timing chart shown to explain the operation of the circuit of this invention, Fig. 3 is an explanatory diagram showing the format of the tfuAc signal, Fig. 4 1 is a circuit diagram showing a conventional memory control circuit. 21...Memory (RAM), 2 Z e II 4.
. . . At circuit, 23 . . . Read address designation circuit, 25 . . . Write address designation circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (1)

[Claims] a memory that can be read and written at the same time if the addresses are different; a first addressing circuit that transitions and outputs addressing data of the memory at a first frequency; and a first addressing circuit that changes and outputs addressing data of the memory at a second frequency; a second addressing method for inputting output addressing data to the memory even while addressing data from the first addressing circuit is being input to the memory; A memory control circuit comprising: a circuit; and means for inputting different initial setting values to the first and second addressing circuits.