JPS5947887A - Digital scramble system - Google Patents

Abstract

PURPOSE:To halve the amount of memory for scramble signal, by taking a readout address as a write address of the next scramble signal. CONSTITUTION:A switching circuit 14 is switched alternately, also bring alternately picture element memories 141, 142 and field memories 151, 152 into the write state, a pattern of a scramble signal at a transmission side is changed alternately for an odd and an even number of times, the readout and write to memories at the receiving side are done alternately at a read/write control circuit 13, which takes a readout address generated at an address circuit 16 as a write address of the next scramble signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital scrambling system for preventing wiretapping of TV broadcast signals such as CATV.

The digital scrambling system digitalizes the image signal from the TV right camera, and within a certain scrambling period (
For example, after randomly intersecting the positions of one frame, one field, or one line of technical images according to a certain pattern, it is converted into an analog image signal and transmitted as a television signal, and the receiving side converts it into a regular image signal. It is something that converts. Therefore, it is impossible to receive scrambled signals with a normal television receiver. Frame scrambling is shown as an example of such scrambling.

FIG. 1 shows a block diagram of a system for receiving a frame scramble signal using conventional digital signal technology.

In the same figure, 1Q, j video No. 46 input terminal, 2 is a video detection circuit, 6 is an A-D converter, 4 is a switching 1-way, 5 and 6-digit frame memory, 7 is a DA converter, 8 is a synchronization signal separation circuit, 9θ verbatim Shintan separation 1i□-I circuit, 10
i-1: IT write address circuit, 12 is readout at 1/s I1.il path, 15
is the read-out control circuit and the 14-digit video signal output terminal A.

The video signals from the video input terminal 1 to the inputs 1 to 1 are detected by the video detection circuit 2, and the A-D changes 4! ! After being converted into a digital signal by the I/O unit 6, the switching circuit 4 controls the read/write control circuit so that either one of the frame memories 5 or 6 which is being processed is set to correspond to the address generated by the write address circuit 11, for example. be remembered. The layered address circuit 11 generates seven addresses in synchronization with a clock generation circuit 10 whose timing is determined by a synchronization separation circuit 8 that separates a synchronization signal from a detected video signal, and generates a digital scramble signal for one frame. is stored in the frame memory 5. When the digital video signal for one frame is stored, the switching circuit 4 is switched by the read/write control circuit 15, and the digital scramble signal of the next frame is stored in the frame memory 6, and at the same time, the digital video signal for the next frame is read out from the frame memory 5 and the address circuit The digital signal of the previous frame is read out according to the address to be converted into a regular sandwich signal generated in step 12, and converted into an analog signal by the D-A converter 7. At this time, read address circuit 1
The pin and timing of address No. 2 were added to video No. 411 on the transmitting side): The pin signal separation circuit 9 and black, is determined by the generation circuit 10. moreover,
When the digital scramble signal of the next frame is manually generated, 1 is written into the frame memory 5, the frame memory 6 is still in the read state, and the above-described process is repeated.

As explained above, in conventional digital signal technology, two frame memories are required to receive frame digit scramble number 1, and the purpose is achieved by reading them alternately and switching to a dry state. reach At this time, the required amount of frame memory is twice the number of picture elements in one frame, and if one picture element is stored in 8-bit digital memory, 2 x 525 x 525 XX 8 = 5.1
It becomes 0.000 bit. Therefore, a memory with a large capacity of 5.8 Mbit is required, which is a major obstacle in receiving one frame digital scrambled signal.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide a digital scrambling system in which the amount of memory required for reception is reduced by approximately half.

In order to achieve the above object, the present invention alternates the number of turns of the scrambled signal on the transmitting side between odd and even times, alternately writes and reads 41 into the memory on the receiving side, and further reads the signal. The 7th address is the write address for the next scramble signal.

An embodiment of the present invention will be described below with reference to FIGS. 2 and 6. Figure 2 is a block diagram of the configuration for receiving the frame dicicle scrambled bone in which the present invention is implemented, and the first
Descriptions of components having the same functions as those shown in the figures will be omitted. In FIG. 2, reference numeral 14 denotes a buffer memory consisting of n picture element memories.In this embodiment, the buffer memory 14 consists of two picture element memories 11141 and 142. ! , 15 is a frame memory divided into n memory blocks, and in this embodiment, it is divided into two, consisting of two field memories 151 and 152, and an address for generating 16-digit input addresses and read addresses. It is a circuit. FIG. 6 is a diagram explaining the operating principle of the present invention, and the explanation is fi? 1. To simplify the process, 1) the frame is set to 8 picture elements, and as shown in (A2) of FIG. Regular signal sequences a-h and a'-h' are shown in (A1). Also the third
(B1) in the figure shows the n-111th stage scramble signal sequence, and (El) in FIG. 3 shows nI! :! The first digital scramble number 11 sequence, (Fl)Kn+1st digital scramble signal sequence is shown. Same figure (B2)
In (B2), n-1 [the storage state of the frame memory when the 1iilth digital scramble signal is received;
The storage state of the frame memory when the digit scramble signal (number 8) is received, (F2) the storage state of the frame memory when the n + 1st digit scramble signal is received, and (B3) the n 710th digit scramble signal. (B3) is an address string that occurs during the scrambling period 101, (B3) is an address string that occurs during the nth scrambling period, (B3) is an address string that occurs during the scrambling period 101,
+ Indicates the address string that occurs during the first null pulse period. Also, the same figure ((:1), (C2), (
C3) shows the digit scramble signal, frame memory storage state, and generated address when the nth digit scramble signal is received at time t4, and (DI), (B2), and (B3) in the same figure The digit scramble signal, frame memory storage state, and generated address when the nth digit scramble signal 48 is received at time t2 are shown. Note that the horizontal axis t of the signal string and address string indicates time.

Here, when the n-1th scramble is performed, A
The output Δ)+- digital signal train from the -D converter 6 is shown in FIG.
7 Shintan generates an at1/s circuit 16. The address string is 9:P, as shown in FIG. 3 (B3), and the state of the frame memory 15 in note 1 and C1 is as shown in FIG. 6 (B2).

Next, when the n-th digital scramble signal sequence shown in FIG. 3 (El) is received, the address circuit 6 detects the pattern (M'+4) in the i-bin signal separation circuit 9 as shown in FIG. The digital scramble signal sequence at this time needs to be scrambled so that the n + 1st address sequence matches the n-1th address sequence. n − same as the address of the first time, n − corresponding to the address of the first time
The digitized scrambled signal is transmitted at the same sampling time as the first regular digitized signal and the digitized scrambled signal is transmitted with a slight deviation. For example, when the address circuit generates 4 at time t1 to read the regular digital readout signal a as shown in (C3) in Figure 3, the address at the n-1st scramble is as shown in (B3). The regular digital f-word of No. 4 is g, and g' may be transmitted as a digital scramble signal. 1. At the same time, the field memory 151 is read by the readout control circuit 1,
When the state is turned on, the digital signal a is output L7, and then turned off. ! 11, and the digital scramble signal g' is stored in the picture element memory 141.

Next, the time is read at 2 o'clock and the control 101 circuit 15 causes the field memory 152 to be in the reading state, the field memory 151 to be in the 1 writing state, and the switching circuit 4 to be switched to the pixel memo mode 142. The pixel memory 142 is controlled to be in the manual state, and the picture element memory 141 is controlled to be in the output state. At the same time, the read/write control circuit 16 holds the address 6 generated by the address circuit 16 as a read address, and also holds the previous read address 4 as a write address. At this time, since the address of the (n-1)th digital scramble signal is d, the regular digital signal of 6 is d, so it is sufficient to transmit digital scramble (Fi-cross dJ) at time t2. , the digital signal is read out from the field memory 152 at time t2,
Digital scrambling of picture element memory 141 (g
' is stored at address 4 of the frame memory 151, and a digital scramble signal d' is stored in the picture element memory 142. I can praise you. Under the moon, the 1liLi next flexural circuit 4 is alternately switched, and the pixel memory 141 and 1
42, by alternately putting the field memories 151 and 152 in the field memory state, finally the frame memo IJ 153J n times 1'' digital scrambling (
All convex rHs are given one edict.

At that time, the memory state is as shown in FIG. 6 (B2), the digital scramble signal string is as shown in FIG. 3 ('li:1), and the address string is as shown in FIG. 6 (E).

Next, when scrambling the n+11φ1th
), (F2), CF5), the normal digital signal strings a' to h' can be read out using the same digital scramble signal and address as in the n-1st null pulse, and the Freno memory is n-1. The memory state will be the same as the first time.

Although the above explanation has been made with the frame memo 11 as 8 picture elements, the present invention can be implemented in the same way even with an actual number of picture elements of 525 x 525 x 7.Furthermore, the present invention can also be implemented in the case where the frame memory is not configured with 2 field memories and with +ib memories. It can be implemented even if configured.

In this way, according to this embodiment, the receiver 4i side 1/(one (l
A digital scramble system can be realized simply by preparing a D7 frame memory.

Further, although this embodiment has been described with respect to a frame digital scrambling system, it goes without saying that a field gauge scrambling system and a line digital scrambling system can be similarly configured with one field memory and one line memory.

As explained above, the VC twist of the present invention can reduce the amount of memory required to receive the digitally scrambled 4F signal by almost half, and has a significant effect on reducing the circuit scale and lowering the cost.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a circuit +14 constructed using the prior art for receiving digital scrambled signals, Fig. 2 is a block diagram of an embodiment of the present invention, and Fig. 6 (1) of the present invention.
It is a clear picture of the principle. 6...A-D converter, 4...Switching l+'jl
7... D-A converter, 9... Bakun Shingei separation circuit, 16... Read/write control 1/1 path, 14...
・Buffer circuit, 141, 142...1 picture element memory,
15... Frame memory, 151, i52... Field memory. 3rd row 479- (F3)

Claims (1)

[Claims] 1. A scrambled signal obtained by scrambling a random-tilt television signal with alternately different push patterns is transmitted from a broadcasting station, a memory for storing the digital scrambled signal, and a pin separation circuit for separating the scrambled pattern signal from the scrambled signal. , a digital scrambling system comprising: an address circuit that generates an address for the memory in response to a pattern signal detected by the Bakun separation circuit; and a read 1 control circuit that controls reading and writing of the memory. , wherein reading and writing of the memory are performed alternately with the read address of the memory as the next write address, and the address pattern generated in the address giant path corresponds to a scramble pattern and is alternately switched. scramble system.