JP2515793B2 - Image descrambler - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image descrambler for receiving a transmitted image signal by concealing the image content by scrambling the configuration of the image signal and restoring the image content. Regarding, in particular,
Changed the order of scanning lines to conceal image contents so that the memory capacity required for descrambling on the receiving side of so-called line permutation can be reduced without compromising the confidentiality of image contents. It is a thing.

(Prior Art) When broadcasting or transmitting a television or high-definition image signal, for example, in order to conceal the image content so that it cannot be viewed by anyone other than the receiving contractor, the image signal is scrambled and transmitted. Various so-called image scrambling methods have been conventionally studied in which descrambling is performed on the side to restore image contents.

Among various image scrambling systems, the so-called line permutation system, that is, the scanning line transition system, converts the arrangement order of the scanning lines of the image signal and sends it out, so that it is not possible to view the image on a normal receiver. It makes the contents indistinguishable. That is, in principle, for example, as shown in FIG. 1, the effective screen of the normal image Fl is divided into a plurality of blocks for each L scanning lines, that is, for each line, and the arrangement order of the scanning lines is converted for each block. If the image is received as it is, it is sent so that only the scrambled image (Fl) in which the scanning line order is disturbed can be observed if it is received, and the receiving side operates the operation line order conversion that is the reverse of the scanning line order conversion on the transmitting side. To restore the normal image Fl. In addition,
In general, the scanning line order conversion of both transmission and reception is performed by correlating each other independently with a random number generated through a key code that is secretly transmitted.

As can be seen from the operating principle shown in FIG. 3, when each block dividing the effective screen includes L lines, the receiving side basically has a line having a capacity of L lines. A memory is provided, and L lines of the received image signal are once written in the line memory in the order of arrival,
The normal image Fl is reproduced by reading in the normal order. Therefore, if the number of lines L included in each block is small, the memory capacity of the line memory provided on the receiving side can be small. However, since the correlation between adjacent lines in the normal image Fl is considerably high, if the number L of lines in each block is small, the image content can be easily discriminated and the concealment effect of image scrambling is reduced. Therefore, in the image scrambling of the line permutation method, regarding the number L of lines in the image block for which the scan line order conversion is performed, the required image content confidentiality and the capacity of the line memory which is a burden on the receiver, It is necessary to carefully consider the conflicting relationship with the cost.

(Problems to be Solved by the Invention) Therefore, when the effective screen is divided into a plurality of blocks and image scrambling is performed as described above, transmission or restoration of an image signal after scan line order conversion or after inverse conversion is performed. Since it has to be continuously performed between adjacent blocks, conventionally, as shown in FIG. 10, two systems of line memories LM ₁ and LM ₂ each having a memory capacity of L lines are provided.
While the image signal before scanning line order conversion is being written to _one line memory, for example LM ₁ , the image signal after scanning line order conversion is read from the other line memory, for example LM ₂ and is input. The input image signal from the end In is alternately supplied to the line memories LM ₁ and LM ₂ by the switch S _w1, and the output image signal is alternately taken out from the line memories LM ₁ and LM ₂ by the switch S _w2. The switches S _w1 and S _w2 that lead to Out and switch the input / output image signal at the L line cycle are interlocked, and the scanning line order of writing and reading of the image signal in the line memories LM ₁ and LM ₂ is controlled by the address control circuit AC. It was controlled in common.

If two scanning line sequence conversion memories are provided as described above, it is extremely easy to smoothly perform signal processing for image permutation line scrambling, but since the memory capacity doubles, the number of lines in a block is increased. If L is increased to increase the confidentiality, there is a problem that the receiving equipment cost increases significantly.

(Means for Solving Problems) It is an object of the present invention to solve the above-mentioned conventional problems and impair the image content concealment effect of image scrambling by reducing the capacity of the line memory used for line permutation. It is to provide an image scramble method and a descrambler that can be reduced.

That is, according to the image scramble system of the present invention, the line memory is used very efficiently by chasing the reading of the image signal from the line memory and writing a new image signal. In the image descrambler that receives the image signal transmitted by performing the image scrambling to convert the order of the scanning lines of the image signal to conceal the image content and restore the image content, a plurality of scanning lines Minute image signals can be stored in scanning line units, and a memory address for controlling writing and reading of the receiving memory unit in scanning line units is generated to continuously read and write the memory addresses. Image signal scrambled for each field of the image signal, provided with receiving memory control means When receiving and sequentially writing to the receiving memory means, the receiving memory control means sets the first block in which the memory addresses of the plurality of scanning lines are arranged once in an arbitrary order, and the validity of the field. A second block in which the memory addresses of the plurality of scanning lines are randomly arranged corresponding to the remaining scanning lines in the screen and a third block in which the memory addresses of the plurality of scanning lines are arranged once in an arbitrary order It is characterized in that blocks are sequentially arranged to generate a memory address of the receiving memory means.

(Operation) Therefore, in the image descrambler of the present invention,
The line memory capacity required for descrambling on the receiving side is reduced as compared with the conventional one without impairing the confidentiality of the image content.
It can be at least halved.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

First, FIG. 3 shows a basic configuration of an image memory device used in the image descrambler of the present invention. In the illustrated basic configuration, memory address numbers (1) to
A line memory LM having a memory capacity of L lines with (L) is controlled by an address control signal including a controlled memory address number from the address control circuit AC,
The output image signal Out for each line is read from the line memory at the specified address, and the input image signal I for each line is read.
write n

The operation mode of the scanning line forward conversion of the method of the present invention using the image memory device having such a basic configuration will be described below with reference to the scanning line forward inversion conversion, that is, image descramble, which is related to simplification of the main receiver configuration. I will explain mainly.

The principle operation of line permutation consisting of scanning line sequence conversion and inverse conversion will now be described with reference to FIG. 2. For the sake of simplicity, for example, lines having memory addresses (1) to (4) for four lines will be described. 4 scan lines using memory LM When the array order conversion and the inverse conversion are performed, on the receiving (descrambler) side, the transmitted image signals for four lines are transmitted in the order of arrival from the address (1) to the line memory LM.
Write in (4). Subsequent to the writing, under the control of the address control signal, the address numbers (3), (1),
Image signals are read out in the order of (4) and (2), and as a result, the normal arrangement order is obtained. So that the image signal of is restored. To do this, the image signal must be the line number as shown. Therefore, on the transmission (scrambler) side, as shown in the figure, the line numbers in the normal arrangement order must be transmitted. Image signals are sequentially written to the address numbers (1) to (4), and then, under the control of the address control signal, the address numbers (2), (4), (1), and (3) are sequentially written. The read image signals are transmitted in the order of reading.

However, in the case of such a scan line forward reverse conversion, since the new image signals that have been sequentially transmitted arrive without interruption even while the image signals are being read from the line memory LM, it is necessary to write the image signals at the same time. I won't. Therefore, conventionally, as shown in FIG. 10, two lines of line memories LM ₁ and LM ₁ each having a memory capacity of 4 lines,
With the LM ₂ provided in the descrambler, the incoming image signal is written to the other while the image signal is being read, and the reading and the writing in this manner are alternately switched.

On the other hand, in the image descrambler of the present invention,
As shown in FIG. 3, the descrambler is provided with only a single line memory LM for four lines, and the read / write operation shown in FIG. 4 is performed to achieve the necessary reverse scan line conversion. . That is, when the address control signal sequentially designates the address numbers (3), (1), (4), and (2) of the first block shown in the upper part of FIG. 4, first, the number (3) At the same time that the image signal of the line number stored at that time is read from the memory address of The image signals of are sequentially written in the read vacant space. The read / write operation is continued with the address number (1),
When the memory addresses of (4) and (2) are repeated in sequence, the line number already written The line numbers that arrived at the same time as the image signals of Image signals of the address numbers (3),
It is sequentially written in the memory addresses of (1), (4), and (2).

Address numbers (3), (1), shown in the upper part of FIG.
Following the read / write operation performed as described above in response to the address control signal composed of (4) and (2), the address number (4) of the second block shown in the lower part of FIG.
In response to the address control signal composed of (1), (2) and (3), the image signal written as described above has the memory of the address numbers (4), (1), (2) and (3). Line number read sequentially from address Image signal of the first block and the second block
Line numbers in a normal array order according to the block address control signal The image signal of is restored.

Therefore, in order to achieve the restoration of the normal image signal as described above, the memory addresses of the address numbers (3), (1), (4), and (2) according to the address control signal of the first block. The image signals sequentially written to the line number Must arrive in order. Therefore, in the transmitting side scrambler, the address control of the first block in the receiving side descrambler is performed by the same random number control by the same logic as the address number generation by the random number control for forming the address control signal in the receiving side descrambler. The line number is calculated by performing a logical operation that predicts signal formation. The image signals are transmitted in this order.

It should be noted that the transmitting side scrambler converts the normal scanning line arrangement order of the original image signal by a logical operation based on the prediction of the random number control as described above, and the line number of the line number suitable for the scanning line order reverse conversion in the receiving side descrambler. In order to send out image signals sequentially in a timely manner, together with a logical operation device,
It is necessary to provide an image memory device having a sufficient memory capacity such as at least two lines of line memory as shown in FIG. 10. However, on the transmitting side in broadcasting, for example, the receiving device can be simplified, inexpensive, and of high quality. Since retention of image quality is given priority in consideration, there is no particular problem.

Therefore, in the image descrambler of the present invention, as described above, in order to enable the sending side and the receiving side to cooperate with each other to perform scrambling and descrambling under the same random number control, the same random numbers are synchronized with each other. Need to be generated. Usually, in order to perform such coordinated random number control,
A method of providing the same feedback shift register on the transmitting side and the receiving side and generating the same pseudo-random (PN) signal by simultaneously loading the respective initial values is used. At that time, it is necessary to separately transmit the initial value data to be loaded at the same time from the transmitting side to the receiving side. As a safe method of transmitting the initial value data, for example, Japanese Patent Publication No. 60-134643 of the applicant's application can be used. There is a "control information transmission system" described in the publication. Further, as a method of loading the initial value in synchronization between transmission and reception, there is, for example, the "timing information transmission method" described in Japanese Patent Application Laid-Open No. 62-77730, which is also filed by the present applicant.

As described above, when the same PN signal is generated at the transmitting side and the receiving side at the same time, the sequence of random number values used for address control of the line memory is sequentially obtained at the receiving side, and at the same time, the same at the transmitting side. The random number value of the sequence is obtained, and therefore, the aspect of descrambling on the receiving side can be predicted on the transmitting side. Therefore,
In order to be able to restore the image signal of the same scan line array as the original image signal as the scan line forward reverse conversion output on the receiving side,
It is possible to predict how the scanning line array of the original image signal should be converted and transmitted on the transmitting side, and such cooperative random number control between transmission and reception is described in, for example, Japanese Patent Laid-Open No. 60- 8
This can be achieved by using the "image scramble system" described in Japanese Patent No. 3670. Therefore, on the transmission side, it is necessary to advance the scanning line forward reverse conversion on the reception side by at least L lines of the memory capacity of the line memory to obtain the above-mentioned random number sequence, but the sequence is transmitted to the reception side. If the initial value data described above is generated in advance, a required random number value sequence can be generated in advance in a timely manner.
For example, if the same random number sequence is generated ahead of the number of lines N ₀ for one field, if the required random number sequence is generated before the vertical blanking period preceding the field, the original image signal is generated. Then, the necessary scanning line order conversion can be performed in advance and the data can be transmitted at a proper time.

Note that if the same initial value is loaded for each field for a certain period, the scramble pattern will appear to be fixed when viewing the scrambled image on a normal receiver, and for each field. When the initial value is not loaded, the scramble pattern always appears to be flowing, and the appearance of the scrambled image can be variously controlled depending on the initial value data and the loading method.

Next, various embodiments of the structure of the address control signal in the receiving descrambler, which is the main object of the image descrambler of the present invention, will be described.

First, for the line memory LM for L lines having the configuration shown in FIG. 3, the address number (1) is assigned to each block obtained by equally dividing the effective screen into L lines as shown in FIG.
As described above with reference to FIG. 4, when the address control signal is constructed so that (L) is generated once in an arbitrary order, the line permutation as shown in FIG. 1 is performed. . In this case,
Since the scanning line order conversion for each L line is performed only within each block obtained by equally dividing the effective screen into L lines, when the number L of lines in each block is small, the correlation is relatively large. Since the scrambling is performed within the strong range, the confidentiality of the image content is reduced along with the reduction of the memory cost. Further, in the scrambled image, the boundaries between the blocks for each L line may be conspicuous, which may cause a feeling of strangeness.

The first embodiment of the address control signal configuration which avoids the above problems is shown in FIGS. 5 and 6 (a),
To explain (b), the read / write operation of the line memory LM having the configuration shown in FIG. 3 is controlled by the address control signal having the configuration shown in FIG. In the address control signal having the configuration shown in the figure, the first address control block I is
In the same manner as described above with reference to FIG. 4, address numbers (1) to
Arrange (4) once in any order, and first,
At each memory address of the line memory LM, four lines of the new image signal that has arrived at that time are sequentially written. Then, in the succeeding address control block II, as described above with reference to FIG. 4, the remaining lines in the effective screen are not divided into four lines, that is, the effective screen is not changed. If it consists of 16 lines, the remaining 12 lines except the 4 lines written by the control address of the first block,
The address numbers (1) to (4) are randomly generated repeatedly, and thereafter, the address numbers (1) to (4) are arranged once again in the arbitrary order in the address control block III, and at that time All input lines 1 to 16 on the valid screen of the field
All the input lines 1 to 16 are read out in the order shown by reverse conversion while being written once to any of the memory addresses of the address numbers (1) to (4). As a result, the scanning line forward reverse conversion is completed for each field of the image signal, the sense of discomfort in which the boundaries between the control blocks are conspicuous in the scrambled image is eliminated, and the range of random number control is expanded to increase confidentiality.

FIG. 5 shows a mode of line number array order restoration in the case where the scanning line order reverse conversion of an image signal having an effective screen of 16 lines is controlled to be completed every field period by using the address control signal of the mode described above with reference to FIG. Referring to FIG. 6 (a), in the address control block 1, slightly before writing the image signals of the input lines 1 to 4 to the memory addresses of the address numbers (1) to (4), respectively. Dummy signal 1 for 4 lines written
~ 4 are read. It should be noted that such a dummy signal is useless in view of the operation principle of the scanning line forward reverse conversion and is not displayed on the restoration screen, but is inserted in order to make the operation of each part of the receiving circuit steady. Subsequent address control block
In II, the image signal of the input line 5 arrived at that time is written in the memory address of the earliest designated address number (1), and is written in that memory address in the address control block I. The image signal of the input line 1 is read. Subsequently, the image signals of the input lines 6 to 16 are successively written to the memory addresses having the address numbers in the order shown, and the image signals of the input lines already written to the respective memory addresses are shown in the order of conversion shown. It is read. Then address control block II
At the end of, the writing of the image signals of all the input lines of the effective screen has been completed, but since the image signals of the input lines of four lines remain in the memory address of any address number, the address control block In III, the address numbers (1) to (4) are generated in an arbitrary order, the image signals of the input lines remaining in all the memory addresses are read out without fail, and the scanning line forward reverse conversion of the field is completed. For the same reason as described above, the dummy signals 1 to 4 are written in all the memory addresses.

Therefore, the input line 1 to the line memory is input by the above-mentioned scan line forward inverse conversion in the descrambler on the receiving side.
Line numbers in the effective screen of the original image in the reproduced image when -16 are read after being converted in the order shown. Must be restored and arranged in the normal order,
For that purpose, each line number in the effective screen of the original image must be converted in advance in the order shown and arranged as the input lines 1 to 16. The line number array forward conversion for such an original image is performed in the transmitting side scrambler by the prediction of random number control of the receiving side address number generation and the logical operation of the scanning line order conversion based on the prediction, which is exactly the same as described above with reference to FIG. It can be done in cooperation with the descrambler on the receiving side. As shown in FIG. 5, in order to smoothly and easily perform the scan line sequence conversion within a single address control block for almost all the scan lines in the effective screen of the original image, the field cycle is set. It is common to require an entire line memory, that is, a field memory. Further, the line numbers of the image signals written in the memory addresses of the address numbers (1) to (4) in the line memory LM are as shown in FIG. 6 (b), and the address numbers (1) to (( It is not always necessary to evenly distribute to 4).

Therefore, when line permutation is repeated in the field cycle of the image signal by the address control signal having the configuration as shown in FIG. 6, the scanning line order conversion and the inverse conversion for the effective screen of a certain field are performed as follows. It is necessary to complete the line memory LM before starting the scanning line order conversion and the reverse conversion for the effective screen of the field, and therefore, in the memory address control of the configuration shown in FIG. 6 (a). In the final address control block III, the address numbers for 4 lines are arranged once for the first address control block I, and the image signal reading for 16 lines of the effective screen is completed.

However, in general, as shown in FIG. 7, if the memory capacity line number L of the line memory LM is made larger than the line number N ₂ in the vertical blanking period interposed between the effective screens consisting of N ₁ lines of each field. , Before the start of scan line conversion and reverse conversion for the effective screen of the next field, that is, within the vertical blanking period following the effective screen of the previous field, scan line forward conversion and reverse conversion for the effective screen of the previous field Can't be completed. For example, 52 scan lines
Explaining 5 standard system television image signals, the number of lines in one field N ₀ = N ₁ + N ₂ is 262.5, the number of lines N _{1 in} the effective screen of one field is 242, and Since the number of lines N ₂ is 20.5, the memory capacity of the line memory LM is the number of lines L in order to complete the order conversion and the reverse conversion of the effective scanning lines in each field period.
Should be L ≦ N ₀ −N ₁ = 20.5. Therefore, in order to increase the confidentiality by increasing the range of random number control by selecting the memory capacity line number L to 20 or more, the effective screen of the field is exceeded beyond the vertical blanking period following the effective screen of each field. It will be necessary to configure the address control signals so that the line permutation for However, in general, during the vertical blanking period of the image signal,
Since various control information is often encoded and transmitted, it is desirable not to scramble from the viewpoint of stabilizing the screen synchronization control.

However, in the case where the confidentiality of the line permutation is emphasized, the address control signal configuration is configured so that the line permutation of the effective screen can be continued beyond the subsequent vertical blanking period. As shown in FIG.

Now, as shown in the drawing, line numbers arranged in the writing order over the N ₁ line of the effective image in the field [I] of the image signal and the N ₂ line of the succeeding vertical baseline period. And the address control numbers A _{1 to} A _N1 arranged in the order of operation, the address control numbers A _{1 to} A _L in the address control block I are assigned to the address numbers of the line memory LM as in the above-described embodiments. (1) to (L) are each assigned once in an arbitrary order, and the address control number A in the address control block II corresponding to the remaining valid screen is assigned.
The _{L + 1} to A _N1, as in the Figure 6 (a), assigns the address number (1) to the line memory LM (L) is repeated at random. Therefore, the address control block that follows the address control block II In the same way as in FIG. 6A, the address control number A for the memory capacity L line of the line memory LM
_If the address numbers (1) to (L) are assigned once to _{N1 + 1} to AN1 _{+ L in} an arbitrary order, all line numbers in the valid screen of field I Line permutation is completed, but since the memory capacity line number L is larger than the line number N _{2 in the} vertical blanking period, the above address control numbers A _{N1 + 1 to} A _N
Address control number corresponding to the vertical blanking period of _{N1 + L}
For A _{N1 + 1 to} A _{N1 + N2} , dummy signals are written in the line memory LM as in the case of FIG. 6A, but the remaining address control numbers A _{N1 + N2 + 1 to} A _{N1. For + L} , the line number of the effective screen in the next field [II] Image signal is written in the line memory LM. Accordingly, as shown in FIG. 7, with respect to the subsequent argument the final address control number A _{N1 + L} corresponding to the field (I) N ₂ line of address control signals, N ₂ lines in the vertical blanking interval Address control signals A _{N1 + 1 to} A _{N1 + L} , the final address control number A _{N1 + L} corresponding to the field [I] can be assigned by assigning the same combination of address numbers even if the arrangement order is different.
Next, after the dummy signals for N ₂ lines are read out, the line number of the effective screen in the next field [II] is read. The image signal of is read out, and the line permutation for each field is smoothly performed on the effective screen of the successive fields.

Here, the line memory control circuit device for forming the address control signal according to the various embodiments described above is generally configured by using a feedback shift register or the like, but here, a schematic configuration example in the case of simple configuration is given. 8th
As shown in the figure, in the circuit configuration shown in the figure, the address control circuit AC in the basic configuration shown in FIG. 3 is modulo modulo the clock pulse generator Cl and the memory capacity line number L of the line memory LM. L counter Ct, and controls the counter Ct according to the clock pulse generation method in the clock pulse generator Cl. That is, for example, for the first L lines in the effective screen, one clock pulse is generated for each line, and the address number designated by the address control signal formed by the counter Ct is incremented by 1 to obtain the line memory. LM
After clearing the dummy signal written in each memory address of, the input / output image signal of the line unit corresponding to the effective screen is sequentially written. Then, for example, as shown in FIG. 7, for (N ₁ -L) lines in the effective screen,
A random number of clock pulses is generated for each line, and L kinds of numerical values in the range of 1 to L from the counter Ct modulo L are formed in random order as address numbers. Then, for the vertical blanking period following the effective screen and the first L line in the effective screen of the next field, one clock pulse is generated for each line,
The portion not displayed corresponding to the blanking period is read without scrambling.

However, when a color image scrambled by line permutation is viewed with a normal color receiver, it is difficult to distinguish the image contents due to the conversion of the scanning line order, and there is no color or the original image. Although different hues may cause discomfort, such disturbance of coloring is caused by inverting the phase of the color subcarrier for each line in a general color television system, This occurs because the color signal processing circuit of the receiver does not operate normally when the phases of the color subcarriers do not invert between the adjacent lines in the line permutation state.

A memory used for line permutation will be described with reference to FIG. 9 which is a third embodiment of the address control signal configuration in which the line permutation can be performed while avoiding the unstable operation of the color signal processing circuit. The line memory LM for the capacity L lines is divided into an odd-numbered line and an even-numbered line of the original image, and two line memories LM each having a memory capacity of L / 2 lines.
₁ and LM ₂ , each of which is controlled by a common address control circuit AC and works in conjunction with each other depending on whether the input / output lines are odd-numbered or even-numbered
The image signal of the input / output line is switched by Sw ₁ and Sw ₂ . Therefore, if the number L of memory capacity lines in the above-described first and second embodiments is an even number, the line memory LM ₁ and LM ₂ can be used without changing the configuration of the address control signals according to the first to third embodiments. Can be applied to the address control of each.

The problem of the color subcarrier phase in the image scrambling by the line permutation described above is not limited to the NTSC system which is the standard system of Japan, but the image scrambling by the line permutation is performed on the encoded high-definition signal by the so-called MUSE system. Although the same occurs in the case, it can be dealt with similarly by the address control of the third embodiment described above.

Further, in the above description, in order to simplify the idea, two line memories are provided, but only a single line memory LM for a memory capacity of L lines is used, and an odd-numbered line memory in the effective screen is used. The same effect can be obtained by configuring the address control signal so that the line group is processed by the odd-numbered memory address group of the line memory LM and the even-numbered line group is processed by the even-numbered memory address group. You can

Further, in the image scrambling according to the line permutation of the present invention, the address control is performed so that the line permutation is performed by using only a part of the memory address group of the capacity L lines of the line permutation line memory. By doing so, the range of line permutation is reduced, so that the contents of the scrambled image can be easily identified. Therefore, the confidentiality of the image content due to scrambling can be increased or decreased by increasing or decreasing the usage range of the memory capacity of the line memory.

However, when the image is scrambled by the line permutation and the sag in the vertical direction is generated in the image signal due to the characteristics of the transmission line and the receiver, the following image quality deterioration occurs in the restored image. That is, for example, the image signal waveform of the line transmitted immediately after the black level of the vertical synchronizing signal may have a delayed rising edge, and the line of the image signal delayed in the rising edge of the waveform is restored by descrambling after transmission. If the image is located in the middle part of, the dark line occurs in the middle part of the restored image and the image quality deteriorates. As a countermeasure against such a case, address control in which line permutation is not applied to the upper end of the effective screen of the original image will be described as a fourth embodiment of the address control signal configuration. For K lines in the above, the original image is reproduced without line permutation. First, as in each of the above-described embodiments, the address control signal for the last L lines of the effective screen is used. After the numbers (1) to (L) are generated once in an arbitrary order, as address control signals for the succeeding K lines,
An address number having the same array as the address number array corresponding to the first K lines in the first L lines is generated.

(Effect of the Invention) As is clear from the above description, according to the present invention, it is possible to easily achieve image scrambling for a television or high-definition image signal even if the cost of a memory provided on the receiving side is reduced. .

That is, in order to increase the confidentiality of the image content by the line permutation, it is necessary to expand the range of the scanning line order conversion, and in order to restore it, it has conventionally been necessary to increase the memory capacity of the line memory provided on the receiving side. According to the present invention, the memory capacity of the receiving side line memory can be reduced to half or less, and therefore, the range of line permutation can be doubled or more with the same memory capacity as the conventional one, and the confidentiality of the image content can be improved. It can be greatly improved.

In the image descrambler of the present invention, in addition to the reduction of the receiving side memory capacity, the transmitting side memory capacity is almost the same as the conventional one, and the memory control is slightly complicated, but when applied to the broadcasting image signal. However, since importance is placed on simplification of the receiving side device, there is no particular problem.

Further, in the image descrambler of the present invention, the boundaries of the blocks that divide the image are not conspicuous in the scrambled image, and the sense of incongruity is less likely to occur, and in particular, the color disorder in the color image is not caused.

Furthermore, in scrambled image broadcasting, it is considered that the confidentiality of the image contents is reduced so that the image contents can be discriminated to some extent even by a normal receiver at the start of the program, so as to promote subscription to the scrambled image broadcast. However, according to the present invention, the variable control of the scramble effect can also be achieved by the variable control of the use range of the receiving side memory capacity.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing an operating principle of image scrambling by scanning line order conversion, FIG. 2 is a diagram showing an operating principle of address control of a line memory in image scrambling, and FIG. FIG. 4 is a block diagram showing a basic configuration of a receiving memory device in the image descrambler of the present invention, FIG. 4 is a diagram showing an example of address control of the receiving memory device, and FIG. 5 is an example of address control thereof. 6A and 6B are diagrams showing the same example of address control, respectively, and FIG. 7 is a diagram showing another example of the same address control, and FIG. Is a block diagram showing a configuration example of a receiving memory control device in the image descrambler of the present invention, FIG. 9 is a block diagram showing another configuration example of the receiving memory control device, and FIG. It is a block diagram showing a configuration of a receiving memory controller. LM, LM ₁ , LM ₂ …… Line memory AC …… Address control circuit Cl …… Clock pulse generator Ct …… Counter, In …… Input image signal Out …… Output image signal, Fl …… Normal image (Fl) ...... Scrambled image

Claims (6)

(57) [Claims] 1. An image descrambler for receiving an image signal transmitted by performing image scrambling for concealing image contents by converting the order of scanning lines of the image signal and restoring the image contents. A receiving memory means capable of storing a signal in scanning line units and a memory address for controlling writing and reading in the receiving memory means in scanning line units are generated so that reading and writing to the memory address are performed continuously. When the image signal scrambled for each field of the image signal is received and sequentially written in the receiving memory unit, the receiving memory control unit includes the memory address for the plurality of scanning lines. The first block in which each of the above is arranged once in an arbitrary order, and the plurality of blocks corresponding to the remaining scanning line segments in the effective screen of the field are A second block in which memory addresses for scanning lines are randomly arranged and a third block in which memory addresses for a plurality of scanning lines are arranged once in an arbitrary order are sequentially formed, and the second memory block of the receiving memory means is formed. An image descrambler characterized by generating a memory address. 2. Of the memory addresses of the third block generated from the receiving memory control means for each successive field of the received image signal, it corresponds to a vertical blanking period following the effective screen of the field. The image descrambler according to claim 1, wherein a memory address having the same array as the memory address array is generated subsequent to the third block. 3. The reception memory control means comprises a clock pulse generator and a counter for counting clock pulses modulo the same number as the number of scanning lines of the plurality of scanning lines, and the clock pulse generator. 3. The array of memory addresses generated from the receiving memory control means is controlled by controlling the number of clock pulses applied from the counter to the counter, according to claim 1 or 2. Image descrambler described in. 4. The image scramble is divided into an odd-numbered scanning line group and an even-numbered scanning line group for each field in an image signal, comprising two systems of the receiving memory means and the receiving memory control means. The received image signal is divided into an odd-numbered scanning line group and an even-numbered scanning line group, and the divided image signals are written in the reception memory means of the two systems. The image descrambler according to any one of items 1 to 3. 5. An image signal scrambled by dividing into an odd-numbered scanning line group and an even-numbered scanning line group for each field in the image signal, and receiving the odd-numbered scanning line group and the even-numbered scanning line group. The image signal of a scanning line group is divided and written into an odd-numbered memory address group and an even-numbered memory address group in the receiving memory means, respectively. The image descrambler according to any one of item 3. 6. A memory address of the same array as the array of a predetermined number of memory addresses in the first block is generated as the memory address of the predetermined number of memory blocks in the second block. The image descrambler according to any one of claims 1 to 5, characterized in that: