JPS58211400A - Storage device controller - Google Patents

Abstract

PURPOSE:To ensure high-speed processing for a storage device which corrects an error of the reading data and then rewriting the data to a storage part, by using an error detecting signal transmitted to a CPU from the storage device to discontinue and tries again the processing of the CPU to correct a reading error. CONSTITUTION:When a reading error is reported through an access control of a storage device, a start request 11n to a control circuit 10 and a signal indicating discontinuation of execution of a microprogram are delivered from an AND circuit 15. An access is tried again to the storage device by the request 11n. Then an instruction which is discontinued again after an access control is over is loaded and started. This can reduce the access time to the storage device and ensure high-speed processing.

Description

[Detailed Description of the Invention] [Technical field to which most of the authors belong] The present invention relates to a central auction system connected to a storage device that stores a code for detecting and correcting errors occurring in auction data together with the data. Regarding storage device controllers,
In particular, it relates to a control device suitable for a central processing unit of an electronic switching device.

[Description of prior art]

Conventionally, this type of control device includes a read error correction circuit in the storage device, and when an error is detected in the data read from the storage device, the error correction circuit corrects the read data within the same memory cycle. Control devices are known that correct and send the information back to a central control device. According to this control device, the frequency of read errors can be made considerably lower than in normal storage devices, but the read data from the t, v must always go through an error correction circuit. Since the data is sent back to the central control unit, the access time of the storage device 6-\ is due to an error in the amount of time in the storage unit.
The time required (1) will be longer. - The 91 hours required for the power and error prevention circuit is 11 hours at a time. 4. As the number of data hints increases, there is a tendency to increase. .Zoshi2
- (Double element switching equipment that requires processing power)) In multi-electronic gauge machines, there is a tendency for the amount of data to be collected at one time to be large, and for this reason, in the [Object of the Invention] The present invention is intended to solve the above drawbacks, and to solve the above drawbacks. It is configured to shorten the access time to the data processing system, and even when processing large-scale data, it is possible to perform high-speed processing of the BJI device regardless of the number of data being focused at once. The purpose of the present invention is to provide an i-storage device controller that does not suffer from a reduction in processing power (11-1).

[Key points of the invention]

The present invention operates from the storage device to the central control unit ~\UJ1. It is equipped with a storage device that sends the error detection signal +j and rewrites the data to the storage section using the output of the error side stop circuit. It is configured to interrupt (2) retry the memory cycle in which the error was detected (7), and perform greedy corrections (7).

The present invention provides means for storing a code for detecting and correcting errors occurring in the rasterization data together with the data, a detection and correction means for detecting and correcting the errors, and an output of the correction means when the error is detected. and a rewriting means for rewriting the address of the storage means from which the data was read.
In the central 11411N device 1&, 8f controls access to the storage device in parallel with the microblock.
1.1; and second means for receiving a read fJ4 code detected in a storage device, interrupting execution of the microphrogram and generating a restart signal to said first means; The M! C) fourth means for restarting the execution of the microprogram written in the third means on the storage device; The storage device is characterized in that it is configured to retry accessing the storage device when a reading error is detected.

[Explanation of Examples]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a storage device control device in a central control device pt- which is an embodiment of the present invention. The configuration of this control device consists of a 11 memory memory that stores the microprogram, and the address of the microprogram to be read next. ll @11 Selects the micro address register 2 that supplies the memory 1, the selection circuit 3 that selects the address of the micro block to be read next and supplies it to the micro address register 2, and the +1 increment result of the micro address register 2. The increment circuit 4 that supplies the circuit 3 and the microaddress
The γ-nd circuit 5 is connected to the output of the register 2, the address safe register 6 is connected to the output of the 77-do circuit 5, and saves the contents of the micro-address register 2 at a specified timing, and the contents of the address save register 6 an AND circuit 7 for supplying the selection circuit 3 to the selection circuit 3; an AND circuit 8 connected to the output of the control memory 1; and a microinstruction register connected to the output of the AND circuit 8 and storing the microprogram instruction currently being executed. 9, and a control circuit 10 that controls access to the ml storage device in parallel with the microprogram [7]. i+ll hook circuit 10 activation request 11a
, llb, ・""tin's logical sum and 9 control circuit 1
An OR circuit 12 that gives a start signal to M
The reader 2-tracing line 13 to which the error signal is sent, the control circuit 4 which performs a retry system for accessing the storage device, and the control circuit 14 which receives the read error notification line 13. and an AND circuit 15 that provides an activation signal to. The control circuit 10 directly reads data from the storage device without going through an error correction circuit, and the control circuit 10 sends information to the AND circuit 7 to indicate completion of access control to the storage device. A line 101 to which the command completion number 1g is output, and a timing signal to give the AND circuit 1b the timing to -f-nick the read 9 error count via the read f-notification line 13 from the storage device. Iwao 102 which is output is 2.L output t
1°? A 1w 141 is connected to the 1ilJ (incorporated) circuit 14, and a display code indicating that the access to the storage device is being retested is led to the AND circuit 7 via this print 141. The inverted output of this long signal is wrapped around the circuit 15. Further, a line 142 is led from this control circuit 14 to output a signal that instructs to interrupt the execution of the microprogram.
The 11th point is connected to the AND circuit 8 and there is -C. The output of the AND circuit 15 is connected to the input 11n↓ of the OR circuit 12, and the input of the AND circuit 5.
To the address safe register 6 when an error is notified, address save and access to storage device 1ltlJ
Instruct the example 14 startup.

Next, please refer to the drawings for the operation of the apparatus according to the present invention! in +,
, I will explain.

FIG. 2 shows a time chart illustrating the operation of the apparatus embodying the present invention.

JJ'T water I] To simplify I-1, ttl site
@To access the device, you must prepare 2 lessons cycle (L(1)
, and □/1. from the storage device. It is assumed that it takes 172 cycles to output 4 (1 net 13) errors.

1, the micro address register 2 is sequentially updated with the output of the increment circuit 4 and advances by 1,000 (assuming it is 7).

In the first cycle, the microphone 0 instruction A is set in the microinstruction register 9, and a storage device access activation request 11a is generated, thereby controlling access to the storage device over the second and third two operation cycles. circuit 10
fH'l is started under the control of fH'l.

On the other hand, in parallel with the opening of access to the storage device 7, control by microinstructions is performed by microinstructions B1 in the second cycle and microinstructions C in the sixth cycle. Further, in the third cycle, a completion signal 101 is generated from the circuit 10, and the access system to the storage device is completed. In the 4th year cycle, 1ti by microinstruction
l rMI is performed, but in this cycle, the access control of the storage device is reported via the L Schiller read error notification line 13. Then, the condition of the AND circuit 15 is satisfied and 7 , this AND circuit 15 generates a request 11n to save the contents of the micro address register 2 to the address register register 2 and to activate the 11Ill circuit 10 via the OR circuit 12. At the same time, a request 11n is issued via the AND circuit 142 to - Instructs to interrupt the execution of the C microprogram (No. 6 is sent to the AND circuit 8, and the AND circuit 8 reads the microinstruction register 9.
Setting to 0 is prohibited and execution of the microprogram is interrupted. At this flash, the contents of the f address safe register are set to N+5, which is the address on the K111 memory 1 of the one ficroinstruction E whose execution was interrupted.

Next, the control circuit 10 is activated by the activation request 1111, and the access to the storage device is retried in the 5th and 8th f! 6
We will use the 2-operation cycle to create a bamboo stick. Zoshi - normal access system - and "Mr. σ1, line 10 in the 6th recycle
A completion signal is generated on 1, and the access control of the storage device is completed. At this time, it indicates that a retry is in progress (l is I
Since it is output to 11!141, AND circuit 70
When the conditions are met, the contents of the address save/distal are recovered to the microatto register 1/2, the control memory 1 is started to be read, and the result and [2] When the instruction E is set, the control from the microinstruction E whose execution has been suspended is activated.

Also, from around the middle of the seventh cycle, a check timing signal is output via the line 102 in the same way as in normal access control, but due to the inverted output of the display signal during retry on the line 141F, the first manual input signal of the AND circuit 15 is output. By prohibiting the access control 41tl to the storage device, even if a read error notification occurs when retrying, the microinstruction is not interrupted. This means that if the storage device is configured to correct the error location in the storage device when a read error occurs, the possibility of a read error occurring in a retry will be reduced; If an error occurs, it is appropriate to regard this % fi as a failure because the LIJ ability to resolve the read error even if it is retried is low.

〔Effect of the invention〕

As explained above, the present invention interrupts the processing of the central control unit by a microprogram in response to a read error detection signal from the storage device to the central control unit, and causes the central control unit to retry access control to the storage device. By configuring the central system to resume processing that was interrupted upon completion of a retry with the storage device, it is possible to select a safe time for detecting read errors in the storage device, regardless of the access time of the storage device. The access time to a storage device is shortened to facilitate high-speed processing.The present invention can be applied to high-speed storage devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an eleventh apparatus embodying the present invention. FIG. 2 is a time chart illustrating the operation of the embodiment device shown in FIG. 1. 1... City 11-memory, 2... Micro address register, 3... Selection circuit, 4... Increment circuit, 5... AND circuit, 6... Address save register, 7... AND circuit , 8...AND circuit, 9...-
Microinstruction register, 10...control circuit, 11...
Start request, 12...Mare circuit, 13...Pile removal error notification line, 14...; 1lIJ Misaki circuit, 15...AND circuit, 101...Completion signal line, 102...Check timing Signal line, 141...Display signal line, 14
2... Execution interruption signal line. Patent applicant: Nippon' City, Ki Co., Ltd. Agent: Naotaka Ide, patent attorney

Claims (1)

[Claims] (1) A first storage means that carries a code for detecting errors in reading data and errors occurring in the read data along with the data, and a first storage means for detecting errors in recording. A detection and correction means for transmitting the read error number 4p and stopping the reading error; A central control unit for micro program control connected to this storage device is equipped with rewriting means for rewriting the address where the data before correction was written, and a micro program execution group I ( 7 in parallel with the microprogram of this first control means.
To access the above storage device ＼, use 2J52-1.
1111 reaching means; and a second control means for storing the address of the interrupted microphone when the first control means interrupts the execution of the microphone. and means for receiving the transverse error code sent from the detection and correction means of the storage device and generating an output signal, the generating means generating an output signal. According to
The first control means interrupts the execution of the micro-70 gram, stores the -y address of the interrupted micro-70 gram, and stores the -y address of the interrupted micro-70 gram.
The control means starts up and re-accesses the storage device, and the second control means finishes the re-access, so that the first control means "−υ The Rr2 i, Rr2 i, Rr2 i, is characterized in that it is configured to read out the -J address of the interrupted micro block from the second storage means and open the micro block to P+.
Device.